Thesis Organization - 高輕載轉換效率及最小互穩壓特性之單電感多輸出直流-直流轉換器

Chapter 1 Introduction

1.4 Thesis Organization

The organization of this thesis is as follows. Chapter 2 describes the minimum switch methodology of the SIMO converter with the load-dependent peak-current control technique in order to improve cross-regulation and light load efficiency. Chapter 3 describes the implementation of the proposed SIMO converter. Chapter 4 presents the power comparator and delta-voltage generators to smoothly switch the operating mode between the PWM and hysteresis modes. In Chapter 5, the experimental results show the minimized cross-regulation and performance of the proposed SIMO converter. Finally, the conclusion and future works are made in Chapter 6.

Chapter 2

Minimum Switch Number Structure with the Load-Dependant

Peak-Current Control Technique

2.1 Controlling Sequence Used to Minimize the Number of Switches

The controlling sequence decides how many energy stores in inductor or delivers to different output terminals. Figure 20 shows the fundamental behavior of a conventional SIDO converter with buck and boost output voltages [2 and 12] as an example for introducing the operation of SIMO converter. Five kinds of inductor current paths, operating in six switching steps, are used to regulate the output voltages during one switching cycle. As shown in Fig.

20, paths 1 and 2 provide charge to the buck output V_OA. Paths 3 and 4 deliver the charge to the boost output V_OB. Path 6 is used to hold the charge in the inductor and to function as a freewheeling current loop. The inductor current waveform of conventional control sequence [10] is shown in Fig. 21. As description in [3 and 10], the prerequisite offset level (I_FW) of inductor current (I_L) trying to handle large load current and eliminate cross-regulation.

However, it is obvious to clearly classify these paths into different regulation of output voltage levels. For boost output terminal V_OB, charge store in inductor L during path 3 while charge are delivered to boost output terminal V_OB with a negative inductor current slope ((V_OB-V_IN)/L) during path 4 which shows in Table I. That is, switches SW₁ and SW₃ efficiently

store charge in inductor L for regulation of boost output terminal V_OB. Switch SW₅ are used to isolate output terminal V_OB from output terminal V_OA. For buck output terminal V_OA, charge not only delivers to buck output terminal V_OA but also store in inductor L during path 1.

Moreover, the storage charge in path 1 is delivered to buck output terminal with a negative inductor current slope ((V_IN-V_OA)/L) during path 2. Therefore, switches SW₁ and SW₄ are used to deliver charge to buck output terminal V_OA and switch SW₄ isolates buck output V_OA from output terminal V_OB. In the meanwhile, charge store in inductor L with a small positive inductor current slope ((V_IN-V_OA)/L) which shows in Table I. Switches SW₂ and SW₄ deliver the storage charge in inductor L to buck output terminal V_OA with a large negative inductor slope (V_OA/L) during path 2. According to storage-charge and charge-delivering paths, all of paths can be classified into categories according to the inductor slope, which shows in Table I.

Fig. 20. The behavior of conventional SIDO converter with one buck and one boost output in [2, and 12].

Fig. 21. The inductor current waveform of conventional control sequence [3 and 10].

Table. I. The specific of inductor current path in conventional SIDO converter.

 L

V V_IN  _OA

L V_OA

 

L V V_IN  _OB

L V_IN





As in previous works, the minimum number of power switches is shown in [10, 11, and 13]. These works generated the boost output voltages and controlled the storage charge of the inductor L in order to regulate the output voltages during one switching cycle. Thus, to minimize the number of power switches in the SIMO converter, the dual boost output terminals converter as shown in Fig. 22 is going to generate one buck and one boost output voltage [2]. The work in [2] provides a QC method that works in PCCM to regulate output voltage V_OA is lower than source voltage V_IN and output V_OB is higher than V_IN. According to the behavior analysis of conventional SIDO converter which is shown in Fig. 20 and Table I, paths 1, 3, and 4 must be kept in the structure of SIDO converter. Path 1 is the only one path to deliver charge to the buck output V_OA. Path 3 is the only choice to store charge in the inductor with a large current slope (V_IN/L), and path 4 is the only path to deliver charge to the boost output V_OB. Furthermore, the buck output voltage can only be regulated by path 1. Thus, path 2 can be removed. This means the switches SW₁ and SW₂ which are shown in Fig. 20 are

Fig. 22. The topology of minimum number of switches in [2] with one buck and one boost output voltage.

Fig. 23. The previous proposed controlling sequence-I in [2].

removed for a minimum number of switches.

After the removal of path 2, a switch SW₆ is added to generate a freewheeling current loop. A previous controlling sequence-I in [2] is depicted for one buck output V_OA and one boost output V_OB in Fig. 23. At the beginning of every switching cycle, path 3 which is

illustrated in Fig. 22 stores charge of inductor with a positive current slope (V_IN/L) from the freewheeling current level (I_FW) to the pre-defined and fixed current level (I_DC). Then path 1 is selected to deliver charge with a positive current slope ((V_IN-V_OA)/L) to the buck output V_OA, and the inductor current level (I_L) is increased to a value (I_DC1), which is dependent on the load condition (I_OA) of the buck output V_OA at the same time. After buck output V_OA operation, the boost output V_OB draws the charge with a negative current slope ((V_OB-V_IN)/L) from path 4 and the inductor current drops back to the freewheeling current level (I_FW). Finally, the freewheeling current level (I_FW) of inductor L is kept by path 6.

Fig. 24. The cross-regulation and inductor current waveform of SIDO converter when the load changes from light to heavy at output terminal V_OA in [2].

Furthermore, the QC method can minimizes the cross-regulation as is demonstrated in Fig. 24. Suppose that the inductor current (I_L) required by load current (I_OA) of buck output terminal V_OA suddenly increases, the duration of time interval (φ_a) will then increase so that more inductor current (I_L) can be delivered to buck output V_OA. As the load condition for output terminal V_OB remains unchanged, the output of the corresponding error amplifier remains the same. Although the whole duration of time interval (φ_b) is shifted to the right, the same amount of charge is still delivered to boost output V_OB. The freewheeling level (I_FW) is

then higher at the start of the next period, and the inductor current (I_L) reaches the pre-defined and fixed current level (I_DC) sooner. Hence, the duration of time interval (φ_a) is shifted left, so as the subsequent time interval (φ_b). In the third period, the inductor current (I_L) assumes the new profile as in the second period and a new steady state is reached. All along, the inductor current (I_L) delivered to boost output terminal V_OB is not affected, and cross regulation is minimized.

However, the inefficient performance is the major disadvantage since the inductor current (I_L) is increased to a highly undesired value if the buck output V_OA is derived during heavy load condition and the boost output V_OB is derived during light load condition. The other drawback is the predefined and fixed current level (I_DC) that contributes to the highly freewheeling current (I_FW) and the serious decrease in power conversion efficiency in the light load condition. Furthermore, the highly undesired current value (I_DC1) of the inductor L also causes the serious cross-regulation in the output terminals since the energy accumulates in the inductor L. As a result, there is difficulty in ensuring the conversion efficiency and minimum cross-regulation of the controlling sequence-I [2]. Furthermore, when the load condition which is shown in Fig. 22 of the buck output V_OA is larger than that of the boost output V_OB, the storage charge of the inductor L accumulates without a releasing path. The highly current level (I_L) appears in the inductor L and results in un-regulation problem.

To address these issues, a new proposed controlling sequence-II with the load-dependent peak-current control (LDPCC) technique is presented as illustrated in Fig. 25. In the beginning of controlling sequence-II, path 1 is used to simultaneously regulate the buck output terminal V_OA and store the charge with a positive current slope ((V_IN-V_OA)/L) in the inductor L, since the voltage level of output terminal V_OA is smaller than that of supply terminal V_IN. Path 1 expires; the inductor current (I_L) then rapidly increases with a positive current slope (V_IN/L) to the LDPCC level (I_peak) by path 3. Then controlling sequence-II switches to path 4 to draw the charge of the inductor L with a negative current slope

((V_OB-V_IN)/L) to boost the output terminal V_OB; after which, it drops back to the inductor current to a freewheeling current level (I_FW). Finally, the inductor current level (I_L) is kept by path 6. Since the current level (I_peak) increases during heavy load condition and decreases during light load condition, the power dissipation during the freewheeling loop can be minimized. Due to the storage charge of the inductor L in path 1 having been fully taken into account in the proposed controlling sequence-II, the highly undesired current value (I_DC1) in previous work [2] is eliminated. Thus, power conversion efficiency and cross-regulation can be improved in the proposed controlling sequence-II. However, when the load condition of output terminals V_OA and V_OB operate in unbalance output load condition which is the buck output V_OA is derived during heavy load condition and the boost output V_OB is derived during light load condition, the energy still accumulates in the inductor L without releasing path.

Other words, when storage charge during path 1 is higher than releasing charge during path 4, the value of inductor current level (I_L) will not able to decrease inductor current level (I_L) below the LDPCC current level (I_peak) in every switching cycle. Thus, the inductor current accumulation appears during unbalance output load condition.

Fig. 25. The proposed sequence-II with LDPCC technique which eliminates the undesired value of inductor current level.

Fig. 26. The proposed controlling sequence and path 0 of the hysteresis mode control.

In order to address the inductor current (IL) accumulation in the structure of minimum power switches, a new energy delivering path, which names as path 0 and illustrates in Fig.

26, is proposed to eliminate the energy accumulation issue while the condition that storage charge during path 1 is higher than consumption charge during path 4. Therefore, a power comparator is proposed to detect the output load condition. If the output power of output terminal V_OA is smaller than that of output terminal V_OB, the proposed controlling sequence-II is use to regulate voltage level of output terminals. Oppositely, when the output power of output terminal V_OA is larger than that of output terminal V_OB, the proposed path 0 is enabled to eliminate current accumulation issue. When path 0 is enabled, switches SW₄ and SW₆ are

closed. A current path is created through switches SW₄ and SW₆ and used to regulate output terminal V_OA. Since the path 0 passes inductor L, the voltage of output V_OA is regulated by a hysteresis voltage window. Therefore, the proposed path 0 also calls as hysteresis mode control. Since the proposed hysteresis mode control is used to regulate voltage level of output V_OA and to limit regulating ripple of output V_OA, the inductor current waveform (I_L) which operates in hysteresis mode is shown in Fig. 25. At the beginning of every switching cycle, hysteresis mode is enabled. Since inductor current (I_L) flows through switches SW₄ and SW₆ to output terminal V_OA, the energy does not accumulate in the inductor L. Thus, inductor current level (I_L) does not increase until path 0 expires. The duration of path 0 is determined by hysteresis voltage window and the on-resistance of switches SW₄ and SW₆. Then, path 3 turns on, switches SW₄ and SW₆ is opened, and switch SW₃ is closed. The inductor current (I_L) is increased with a positive current slope (V_IN/L). When inductor current (I_L) raises to LDPCC level (I_peak), path 3 expires and then switch SW₃ turns off. Then, path 4 and switch SW₅ turns on, the storage charge, in form of inductor current (I_L), ramp down with a negative current slope ((V_OB-V_IN)/L), the duration of path 4 is determined by the amount of delivering charge.

Finally, the residue current level (I_FW) is held by path 6. Owing to the output voltage of output terminal V_OA is regulated by a hysteresis voltage window during path 0, the special operation which is named as hysteresis control mode caused a larger output ripple and sacrificed power conversion efficiency in the proposed path 0. However, as the analysis of the hysteresis control mode, the energy accumulation and cross-regulation during the unbalanced load condition can be eliminate through path 0.

2.2 LDPCC Method for Improving Light-Load Efficiency, Stability, and Cross-Regulation

The inductor waveform (I_L) represents status of energy storage and the order of system.

Four inductor waveforms are depicted in Fig. 27~30. At first, the inductor current waveform (I_L) of DCM is shown in Fig. 27. The characteristic of inductor current (I_L) is that current level decreases to zero before the end of each switching cycle. The order of the system is equal to one. That is, only one low-frequency pole exists in the close loop. When load current changes from light to heavy load condition, the peak value of inductor current (I_L) is increased for storage more energy. There is a maximum peak current level existed, because of the disappearance of zero-current condition and thus a maximum power limitation exists in the operation of DCM. As a result, the characteristic of inductor current waveform (I_L) changes from DCM to CCM operation as shown in Fig. 28 when the sudden power is larger than maximum power limitation of DCM operation. The order of system becomes two and the

Fig. 27. The inductor current waveform in DCM operation when the load current changes from light to heavy load conduction.

Fig. 28. The inductor current waveform in CCM operation when the load current changes from light to heavy load conduction.

compensation of system needs a complicated compensation like proportional integral differential (PID) compensator to make sure large low-frequency gain and suitable phase margin. Another serious problem is disappearance of isolation period which is zero-current stage works as freewheeling stage. Since disappearance of isolation period may cause worse cross regulation. The cross regulation and instability of system comes from the charge accumulation of inductor. A summary of the two operation modes is that disadvantage of the DCM operation is maximum power limitation while the disadvantage of CCM operation is charge accumulation of inductor L.

The PCCM operation was proposed to improve the disadvantages in DCM and CCM operation [10]. The PCCM technique sets a constant inductor current DC level to store enough energy in inductor as depicted in Fig. 29. Thus, the order of system is similar to that of DCM operation while the maximum power delivered by PCCM operation is larger than that of DCM operation. That is, the order of system is one, and thereby simplifying compensation skill. After the usage of P-I compensator, bandwidth can be extended to have better performance for transient response. Nevertheless, the advantages of the PCCM operation only exist when freewheeling stage exists at end of each switching cycle. Once disappearance of freewheeling stage happens when load current exceeds maximum power limitation or when sudden load current changes from light to heavy load level, the stability and minimized cross regulation isn’t guaranteed since the order of system becomes two. The solution of scenario is that pre-defined and fixed inductor current level (I_DC) is required large enough to provide maximum power to all output terminals. That is, the value of the pre-defined and fixed inductor current level (I_DC) causes the power conversion lower than that by CCM or DCM operation at light load condition since the freewheeling stage with high inductor current occupies the most period of switching cycle. Thus, the light-load efficiency is decreased. As well, the power conversion efficiency at light-load determines usage time of battery for portable devices.

Fig. 29. The inductor current waveform in PCCM operation of work [2] when the load current changes from light to heavy load conduction.

Fig. 30. The inductor current waveform in proposed LDPCC technique operation when the load current changes from light to heavy load conduction.

To enhance the power conversion efficiency at light-load becomes most important issue in today’s portable devices. The LDPCC technique is needed to effectively improve the power conversion efficiency at light-load condition. As illustrated in Fig. 30, the LDPCC technique is proposed to adaptively store suitable energy in inductor L. When load current changes from light to heavy load condition, the LDPCC current level (Ipeak) is raised to a higher current level to store enough charge in inductor L. On other hand, when the load current becomes small, the LDPCC current level (Ipeak) will be decreased to a small current level for ensuring high power conversion efficiency at light load condition. Besides, a minimum inductor current level (IDC(min)) is defined to prevent output terminal from large transient drop voltage.

Thus, the LDPCC technique can have advantages of simple compensation, large driving

Fig. 31. The inductor current variation when the load condition changes from light to heavy in output terminal V_OA.

Fig. 32. The inductor current variation when the load condition changes from light to heavy in output terminal VOB.

capability, and high power conversion efficiency at light-load condition. The LDPCC technique can minimizes the cross-regulation, which looks alike the QC method in [2], as is demonstrated in Fig. 31. Suppose that the current required by output terminal V_OA suddenly increases, the duration of time interval (φ_a) will then increase so that more current can be delivered to output terminal V_OA. The inductor current (I_L) then reaches the LDPCC level (I_peak) sooner. As the load for output terminal V_OB remains unchanged, the output of the corresponding error amplifier remains the same. Although the whole duration of time interval

(φ_b) is shifted to the right, the same amount of charge is still delivered to output terminal V_OB. The LDPCC level (I_peak) is then higher at the start of the next period. Hence, time interval (φ_a) is extended left, so as the subsequent time interval (φ_b). In the third period, the inductor current (I_L) assumes the new profile as in the second period and a new steady state is reached.

All along, the current delivered to output terminal V_OB is not affected, and cross-regulation is minimized. Similarly, Fig. 32 demonstrates the minimized cross-regulation in that output load current required by output terminal V_OB suddenly increases.

2.3 System Architecture of SIMO DC-DC Converter

According to the proposed controlling sequence-II and the LDPCC technique, the architecture of the proposed SIMO converter is illustrated in Fig. 33. As previous analysis of switch number, the minimum number of switch is shown in the top of Fig. 33. The main switch SW_N and freewheeling switch SW_F construct paths 3 and 6 of controlling sequence-II.

Switches SW_K1~SW_Kn and SW_T1~SW_Tm are used to extend and isolate output terminals V_OK1~V_OKn and V_OT1~V_OTm. Therefore, the total number of power switch is equal to the number of output terminals pluses two. Output voltages are detected by error amplifier array via output divider array. The output signals V_EK1~V_EKn and V_ET1~V_ETm of error amplifier array connect to the input terminals of LDPCC circuit for generating load dependant peak current signal V_Ipeak. Moreover, the LDPCC circuit also generates current signals I_EK1~I_EKn and I_ET1~I_ETm which are used to be discharging current sources in charge reservation circuit. Since the charge reservation circuit uses the output current I_SEN of current sensor and the LDPCC current signals I_EK1~I_EKn and I_ET1~I_ETm as charging and discharging current sources respectively, the storage charge on indicative capacitors C_IK1~C_IKn and C_IT1~C_ITm of charge

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