Chapter 3 Design and Analysis of Proposed SIMO DC-DC Converter
3.3 Logic Control Circuit with Automatic Mode Switch for Avoiding Instability
The control logic generator with automatic mode-switch controller is depicted in Fig. 40.
It generates logic control signals DSWN, DSWF, DSWK1~DSWKn, and DSWT1~DSWTm for driving power switches according to system clock VCLK and output signals CMKi, CMR, and CMTj of comparator array. The operation of the control logic is divided into four durations of current paths 1, 3, 4, and 6, which sustain for the four charge-delivering paths in Fig. 25. At the beginning of path 1, the system clock VCLK of control logic generator is triggered by a positive edge and 90% duty cycle of system clock VCLK. The state of logic control signal DSWKi is set to low state and converted to driving signal VSWKi for delivering charge from supply source VIN
D Q
Fig. 40. The control logic generator with the mode switch controller.
to buck output terminal VOKi. The input signal CMKi of control logic circuit, where the suffix i is from 1 to n for buck output terminals, is from output signals of related comparator i in Fig.
33, which decides the duty cycle of buck output terminal i. At the same time, the inductor current (IL) is increased with a positive current slope ((VIN-VOKi)/L). According to charge reservation circuit operation, current sensor senses inductor current (IL) for charging indicative capacitors CIKi and CITj of charge-reservation circuit. Therefore, the indicative capacitor CIKi is charged by sensing current Isense of current sensor. When the charging voltage VIKi on indicative capacitor CIKi is larger than output signal VEKi of error amplifier array in Fig.
33, the output signal CMKi of comparator array changes to a low state and path 1 then turns off. Since the control logic unit combines the system clock VCLK and comparator output CMKi
as trigger signal CKOUT, Path 3 starts to ensure sufficient energy to be stored in the inductor L at the negative edge of comparator output CMKi. That is, the inductor current (IL) is increased to the LDPCC level (Ipeak).
In path 3, the LDPCC signal VIpeak in (19) which defines charge requirement according to the LDPCC circuit in Fig. 34 and the value of current signal VRS in Fig. 36 are used to determine the time interval of output signal DSWN for increasing the inductor current (IL) to the LDPCC level (Ipeak) until the value of current signal VRS is large than that of LDPCC signal VIpeak. That is, the output signal DSWN is set to high state for increasing the value of inductor current (IL) to LDPCC level (Ipeak) until the value of current signal VRS is large than that of LDPCC signal VIpeak. However, the time interval of output signal DSWN may be zero if the inductor current (IL) is increased to exceed the LDPCC level (Ipeak) during path 1. This condition is caused by the heavy load condition at buck output terminals and light load condition at boost output terminals. This means that the inductor current level (IL) is high enough to provide sufficient energy to the multiple boost output terminals after path 1. There is no need to store more charge in the inductor L since it may cause current accumulation issue in Fig. 41. Therefore, a hysteresis mode which is shown in Fig. 26 is proposed to address the current accumulation issue and provide a new charge-delivering path rather than path 1.
Once the value of current signal VRS is large than that of LDPCC signal VIpeak, comparator output CMR changes to low state and path 3 turns off. Path 4 then is enabled by negative edge of comparator output CMR and starts to deliver charge to boost output terminals.
At the same time, the inductor current (IL) is decreased with a negative current slope ((VOB-VIN)/L) which according to the load condition of the boost output terminals. Similarly, according to charge reservation circuit operation, indicative capacitor CITj is charged by sensing current (Isense) of current sensor. When the charging voltage VITj on indicative capacitor CITj is larger than output signal VETj of error amplifier array in Fig. 33, the output
(1)
(4) (3)
(6)
PWM mode
Ipeak IL (A) VSWTj
VSWN
VSWKi
VSWF
Buck Boost FW
TS
0 time
(1) (6)
(4)
2TS 3TS
Current accumulation
Hysteresis mode
Buck Boost FW
Fig. 41. The timing diagram of the transition from the PWM mode to the hysteresis mode.
signal CMTj of comparator array changes to low state. Once comparator output CMTj is changed to a low state when the value of charging voltage VITi is larger than output signal VETj of error amplifier array, the charge-delivery to the boost output terminals is completed. Then the controlling sequence-II enters path 6 named as freewheeling stage. That is, the surplus energy is reserved in the inductor L. The longer the period of the freewheeling stage is, the lower the power conversion efficiency. Owing to the adjustment of the LDPCC circuit, the inductor current level (IL) at the freewheeling stage is kept at a low level which is limited by a minimum current level IDC(min) and thus the conduction loss can be reduced at light load conditions. All the output signals DSWK1~DSWKn, DSWN, DSWT1~DSWTm, and DSWF of the control logic circuit are converted by the dead-time controller and driver circuit which is shown in Fig.
33 to the gate driving signals VSWN, VSWF, VSWK1~VSWKn, and VSWT1~VSWTm which are used to control the power MOSFET switches SWN, SWF, SWK1~SWKn, and SWT1~SWTm.
However, the mentioned current accumulation issue which is illustrated in Fig. 41 still exists in the structure of SIMO converter. When the output power of buck output terminals is
larger than that of boost output terminals, the current accumulation occurs. The charge from supply source not only delivers to the buck terminals but also store charge in the inductor L during path 1 operation. The only way to release storage charge in inductor L is to transfer storage charge to boost terminals during path 4 operation. Thus, when charge deliver to boost terminals are smaller than that of buck terminals, the inductor current level (IL) is going to increase higher than the LDPCC level (Ipeak). Owing to the current accumulation in inductor L, the sensing current (Isense) also increase to high value. Therefore, the charging voltage VITj on the indicative capacitor CITj of charge reservation circuit rapidly increases during short period.
The operating duration of boost terminals becomes much smaller than the original due to the highly inductor current level (IL). This situation causes that the comparator array is not able to react to such a small operating duration. Thus, the accumulated current causes serious cross-regulation and poor conversion efficiency at light load conditions.
To address this problem, it is important to provide other releasing path to alleviate the instability. Hence, a new current path which is path 0 and named as hysteresis mode is proposed in Fig. 26. During operation of hysteresis mode, original path 1 in PWM mode is changed to path 0 to force the delivering current to flow through freewheeling switch SW6 to the buck terminals. Therefore, the delivering energy of the buck terminals does not cause current accumulation in the inductor L. Thus, the buck terminals works as a hysteresis buck converter, and the output voltage VOKi is directly regulated and limited by a hysteresis window.
The power MOSFET’s driving signals and inductor current waveform (IL) as depicted in Fig.
41 which shows the transition from the PWM mode to the hysteresis mode. To achieve the hysteresis control mode, a mode switch, a power comparator, and a novel delta-voltage generator are proposed. The mode switch as shown in the sub-block of control logic unit in Fig. 40 is composed of only one AND logic gate, and the output signal “hys” of mode switch is kept at a high state during the PWM operation until the input signal “modei” of mode witch which comes from the power comparator circuit is changed to a low state. Then the operation
of the buck terminals is switched to hysteresis mode. Since path 6 directly connects the buck terminals to supply source VIN, the output ripple of buck terminals is increased for ensuring system stability during hysteresis mode. The simulation results are shown in Fig. 42 and 43 which are shown the PWM mode and hysteresis mode, respectively. Next chapter discusses the power comparator and delta-voltage generators to smoothly switch the operating mode between the PWM and hysteresis modes in detail.
Fig. 42. The simulated waveforms of control logic circuit in PWM mode operation.
Fig. 43. The simulated waveforms of control logic circuit in hysteresis mode operation.