Chapter 4 Power Comparator and Delta-Voltage Generator
4.1 Power Comparator Circuit
To smoothly switch between PWM and hysteresis operation modes, the power comparator and delta-voltage generators are proposed to decide the operation mode of SIMO converter. The inductor current waveform (IL) as depicted in Fig. 60 precisely describes the boundary condition between the PWM and hysteresis modes. Assume that the current slopes mK1~mKn and mT1~mTm of the inductor current (IL) for the buck and boost output terminals are expressed as (34) and (35), respectively. The value of suffix i is from 1 to n for buck output terminal i and the value of suffix j is from 1 to m for boost output terminal j. The operation modes and boundary condition can be determined by comparing the total charge of buck output terminals operation with total charge of multiple boost output terminals operation.
Therefore, the equation (36) expresses the charge-condition in PWM mode. Equation (37) represents the charge-condition in hysteresis mode. Thus, when the total charge of buck output terminals is equal to that of boost output terminals, the boundary condition which is charge-balance condition and expresses in (38) is used to judge the operation mode of SIMO converter.
L V mKi VIN OKi
for buck output terminal i (34)
Fig. 60. the boundary condition between the PWM and hysteresis modes
for hysteresis mode operation (37)
output terminals needs to enter hysteresis operation according to the largest load current. The voltage-current converters convert the differential voltage between output voltages and supply voltage into current signal for indicating current slope of inductor L. The summation current ImK1 and ImT1 of V-I converter indicate the slope values of the buck and boost output terminals, respectively. Summation current ImK1 is used to discharge capacitor C1 during the buck operation, and current ImT1 is used to charge capacitor C1 during boost operation in first loop.At the freewheeling stage, the sample and hold (S/H) circuit sample the voltage on capacitor C1 and hold it on the capacitor C2. Thus, the boundary condition is monitored by the slope
1:
Fig. 61. The schematic of proposed power comparator circuit
INP INN
Fig. 62. The current comparator of proposed power comparator circuit.
values of buck and boost output terminals. In the operation condition of PWM mode, the value of summation current IMK1 is smaller than that of summation current IMT1, and output signal EN1 of comparator CP1 is set to a low state in the first loop. That is, the power comparator circuit is disabled. The output signals M1~Mi of registers Reg.1~Reg.i are set to a low state to disable the mode switch of control logic circuit in Fig. 40. Besides, the internal signals S1~Si are set to low state. The mirrored current signals IBK1~IBKi sum up in IMK2, which is used to compare with summation current IMT2 of boost output terminals in second loop. The other mirrored current signals IAK1~IAKi of V-I converter are switched to detect the highest current level by current comparator which is shown in Fig. 62.
When the power level of buck output terminals are larger than that of boost output terminals, the output signals EN1 and EN2 of comparators CP1 and CP2 is set to high state.
The power comparator circuit is enabled and decides the buck output terminal with highest output load condition into hysteresis mode. Thus, the mirrored current signals IBK1~IBKi sum up in IMK2, and all mirrored current signals IAK1~IAKi of the delta-voltage generator for buck are separately switched to detect the highest slope by the current comparators. In the meanwhile, the generated summation current IMK2 compares with current IMT2 and outputs the high state of output signal EN2 in the second loop. This second loop is designed to detect operating mode of each buck output according to the buck output with the largest load current selected for hysteresis mode. When the output signal EN2 is high state, the trigger signals of registers Reg.1~Reg.i are enabled by output signal EN2 and output signal DL of delay circuit.
The delay circuit is enabled to avoid the oscillation of the second loop and to ensure the storage charge in the steady state when one of the buck output terminals enters hysteresis mode. Current signals IAK1~IAKi flow into the current comparator and generate the detecting codes D1~D(i-1) during the delay period of delay circuit. The detecting code is converted to indicate which one of the buck output terminals has the highest load condition and needs to operate in hysteresis mode. The detecting code can be expressed as (39).
Moreover, the inverse signal SX of output signal modeX inhibits the related current signals IAKX and IBKX. As a result, summation current IMK2 can be expressed as (40)
) IBKX(n) are the current signals by the nth operation of the second loop according to the priority of load condition. Once current IMK2(n) is smaller than current IMT2, output signal EN2 of comparator CP2 is set back to low state. That is, the charge-detection process is ended, and the proposed converter can really avoid the current accumulation and minimize the output ripples of the buck output terminals in hysteresis mode. The hysteresis mode operates until current depend on the definitions of equations (34) and (35) to generate the different inductor current slopes for the smooth switching between hysteresis and PWM operation modes. In order to meet the input common-mode range of delta-voltage generator and measure buck and boost output voltages, two delta-voltage amplifiers with different input types are proposed for the