Simulation Results

In order to validate the accuracy of the derived model, SPICE simulations are performed by output responses for both the equivalent 3-stage circuit shown in Fig. 4.1 and the correspond-ing 3-stage model, where VDD = Vclk = 1.5 V, RL = 100 kΩ, fs = 1 MHz, and D was determined by employing the relation between C3 and CO from (4.42).

Fig. 4.13 shows the output simulation waveforms of the equivalent 3-stage circuit and the model, respectively, where the simulation conditions are Cm = 60 pF (m = 1, 2, 3), CO = 200 pF, IL = 40 µA, and D = 0.57. Under these design conditions, the output ripple ∆Vo of the equivalent 3-stage circuit is limited to 0.2 V, and the mean of this undulate output voltage is 4 V, which is equal to Vo,avg of the model in the steady state. A satisfactory agreement between

these two simulations can be observed during the procedure of boosting. In addition, from additional simulation data with different Cm values and various pump stage numbers, the output value of the model always follows the undulate output waveform of the equivalent circuit as shown in Fig. 4.14 and Fig. 4.15. Consequently, these simulation results show that the presented model can predict the output behavior of a multi-stage PGI circuit with a resistive load.

Fig. 4.13 Comparison between simulated output waveforms of the equivalent 3-stage circuit and of the corresponding model.

Fig. 4.14 Comparison between simulated output waveforms of the equivalent 3-stage circuit and of the corresponding model under different Cm values. (a) Vo,avg = 5 V and Cm

= 150 pF. (b) Vo,avg = 4 V and Cm = 60 pF. (c) Vo,avg = 3 V and Cm = 30 pF.

Fig. 4.15 Comparison between the simulated output waveforms of the equivalent circuit and of the corresponding model with various numbers of pump stages, where all pump capacitances are fixed at 60 pF. (a) 3-stage for Vo,avg = 4 V. (b) 2-stage for Vo,avg = 3.375 V. (c) 1-stage for Vo,avg = 2.57 V.

However, in common uses, the duty ratio of CPCs is usually set to D = 0.5. With this configuration, (4.42) is ineffective in finding a suitable value of CO/CN for equating Vk to Vo,avg shown in Fig. 4.7. If CO >> CN, ∆Vo1 will be close to ∆Vo2 and the difference between Vo,avg and Vk can be reduced. Otherwise, a slightly greater error will exist. Consequently, when the duty ratio D = 0.5, the accuracy of the equivalent model depends on the ratio of CN and CO. Fig. 4.16(a) shows the difference error between Vo,avg in the model and the mean of the undulate output voltage in the equivalent 3-stage circuit obtained from SPICE simulation results when a square clocks (D = 0.5) are employed. In addition, the corresponding value of the output ripple ∆Vo is shown in Fig. 4.16(b). Since the CN/CO ratio will decrease as the value of CO increases, from Fig. 4.16, the larger the value of CO is, the smaller the relative error and the output ripple ∆Vo will be. If CO is larger than 200 pF, it appears that the error and ∆Vo are less than 0.4 % and 0.2 V, respectively. Similarly, by using various numbers of pump stages as shown in Table 4.1, the relative errors and ∆Vo of the equivalent circuit with Vo,avg = 4 V and D = 0.5 are shown in Fig. 4.17.

(a) (b)

Fig. 4.16 (a) Relative errors between the model and the 3-stage circuit for different desired Vo,avg with VDD = Vclk = 1.5 V, RL = 100 kΩ, fs = 1 MHz, and D = 0.5. (b) Corresponding output ripple ∆Vo.

(a) (b)

Fig. 4.17 (a) Relative errors between the model and the equivalent circuit with different stage number N for Vo,avg = 4 V and D = 0.5. (b) Corresponding output ripple ∆Vo.

A practical embodiment of a 3-stage PGI-3 circuit, which is built by the circuit shown in Fig. 3.4, was simulated in transistor level by using parameters of a TSMC 0.35-µm mixed mode process and using general clocks (D = 0.5). With the same simulation conditions used in Fig. 4.13 except that the duty ratio D = 0.5, the transient simulation waveforms are shown in Fig. 4.18. From the simulation results, the final mean value of the practical circuit is about 3.95 V, and the error between this mean value and the Vo,avg (= 4 V) of the model is about 1.25%. In addition, other simulation results with different Cm values and various numbers of pump stages are shown in Fig. 4.19 and Fig. 4.20. The output value of the model can be demonstrated to follow the undulate output waveform of the practical PGI circuit.

Fig. 4.18 Comparison between simulated output waveforms of the practical 3-stage PGI-3 circuit and of the corresponding model.

Fig. 4.19 Comparison between simulated output waveforms of the practical 3-stage PGI-3 circuit and of the corresponding model under different Cm values. (a) Vo,avg = 5 V and Cm = 150 pF. (b) Vo,avg = 4 V and Cm = 60 pF. (c) Vo,avg = 3 V and Cm = 30 pF.

Fig. 4.20 Comparison between simulated output waveforms of the practical 3-stage PGI-3 circuit and of the corresponding model with various numbers of pump stages, where all pump capacitances are fixed at 60 pF. (a) 3-stage for Vo,avg = 4 V. (b) 2-stage for Vo,avg = 3.375 V. (c) 1-stage for Vo,avg = 2.57 V.

Besides the influence of the duty ratio D, these small errors are most likely due to the fact that switching losses and parasitic capacitances of the practical PGI circuits are taken into account in SPICE simulations but not included in the equivalent model. In addition, the full practical circuit simulation waveform lags slightly behind that of the model. This waveform lag is due to the fact that gate control voltages of the transfer switches generated by CTS’s in the PGI circuit would not be pumped to the levels for turning on the switches completely in the initial few cycles. In summary, the output behavior and the final Vo,avg of the model closely match the simulation results of the practical PGI circuit. Thus, the presented simple and regular equivalent model is useful for designing PGI circuits.