EEPROM and Flash Memory

For electrical re-programmability in floating-gate devices, EEPROMs and flash memories

depend on a technology mechanism referred to “Fowler-Nordheim (F-N) tunneling” or “cold electron tunneling”. The effect of tunneling allows electrons to pass through the energy barrier at the silicon-silicon dioxide (Si-SiO2) interface at a lower energy than the 3.2 eV required passing over this energy barrier. Based on the F-N tunneling mechanism, the floating gate tunneling oxide cell was developed by Intel and has been one of the most common EEPROM cell [8]-[9]. As shown in Fig. 1.1, a basic cell of an EEPROM contains a select transistor and a double polysilicon storage transistor with a floating polysilicon gate isolated in silicon dioxide capacitively coupled to a second polysilicon control gate which is stacked above it. A thin dielectric layer between the floating gate and the source enables the flow of electrons into and from the floating gate during program/erase operations, by means of F-N tunneling.

(a)

(b)

Fig. 1.1 (a) Circuit symbol and (b) cross section of a basic EEPROM cell [8].

In the program mode, a positive high voltage is applied to the control gate of the cell, while the drain is floating and both the source and the substrate are grounded. The floating gate is charged negatively with electrons tunneling from the source through the thin oxide. The stored negative charge on the floating gate shifts the threshold voltage of the transistor toward the positive value. In a subsequent program operation, the transistor will not conduct channel current so that the transistor will be “off”. Fig. 1.2(a) shows the floating gate transistor during programming. The erase operation removes electrons from the floating gate by applying a positive high voltage at the source, while the drain is floating and both the control gate and the substrate are grounded. As shown in Fig. 1.2(b), electrons tunnel from the floating gate to the source leaving the floating gate relatively more positively charged. Thus, the threshold voltage is shifted in the negative direction. During subsequent erase operation, the channel current would flow so that the transistor will be “on”. Fig. 1.3 shows the shift in the i_D –v_GS characteristic of a floating-gate transistor as a result of programming or erasing. To read the content of the memory cell, a suitable voltage v_GS, employed mainly by the supply voltage, somewhere between the low and high threshold voltages (VT0 and VT1) can be applied.

(a) (b)

Fig. 1.2 (a) Program configuration and (b) erase configuration of a double polysilicon storage transistor in a basic EEPROM cell [10].

Fig. 1.3: Illustrating the shift in the iD –vGS characteristic of a floating-gate transistor as a result of programming or erasing [11].

In the conventional scheme, F-N tunneling erase has been achieved by raising the source junction to a positive high voltage and grounding the control gate. The source junction is formed to be a double diffusion structure in order to obtain a high breakdown voltage. The deeply formed drain junction prevents channel length scaling, which is required for high-density memory cells. The negative-gate-biased source erase scheme can overcome this problem by applying a negative voltage to the control gate to obtain F-N tunneling. The source voltage necessary for F-N tunneling can be reduced to the supply voltage VDD. Fig. 1.4 shows a conventional double diffusion structure compared with the negative-gate-biased source erase scheme, which has the benefit of scaling down the channel length.

Fig. 1.4 Negative-gate-biased source erase scheme [1].

Due to the two-transistor type cell, byte-write and byte-erase abilities are accomplished by the EEPROM. However, a major disadvantage of the EEPROM is in a large size of the two-transistor memory cell and that has kept the cost high. Flash memory is a direct derivate of the one-transistor cell EPROM (Erasable Programmable Read Only Memory). It resulted from innovative cell designs and improved technology that allowed the one-transistor cell EPROM to be reprogrammed electrically in the system. Many of the flash memory cells that have developed use the split gate concept in which the separate select and storage transistor gates of the EEPROM are merged into a single device with the channel region shared by the two gates [10]-[12]. Thus, the flash memory has a smaller chip size and a higher density compared to EEPROM. However, unlike EEPROMs with byte-write and byte erase abilities, the flash memory only can be programmed or erased by section.

No matter which nonvolatile memory scheme is used, a high voltage with either a positive or a reverse polarity to obtain F-N tunneling is critical in a floating gate structure. As these voltages can be provided externally or generated within the device, memory chips can be divided into double-supply and single-supply devices. In the former case, one supply pin (VDD) is used for the general-purpose supply, and the other pin (V_PP) is devoted to program/erase operations (obviously, VPP is higher than VDD). In the latter case, only the VDD pin is present, and all other voltages are generated on-chip.

The charge pump circuit is a common on-chip voltage generation for producing any voltage between ground and the power supply on a memory chip [13]-[14]. Furthermore, it is also possible to generate high voltages that are below ground and above the power supply value for creating F-N tunneling. A block diagram of a common flash EEPROM is shown in Fig.

1.5. In this figure, charge pump circuits not only generate large positive and negative voltages (V_H) of up to 20 V for programming and erasing but also provide medium voltage (V_P) of around 5 V to control the operation mode. Since VH and VP are generally applied to the control gate and the source junction, respectively, the drivability of the V_H generator can be set lower

than the VP one. In addition, a reference voltage is needed to control VH and VP to achieve the required stable value which must be guaranteed for accurate read/write/erase operation of the memory cell.

Fig. 1.5 Block diagram of a common flash EEPROM [14].