Transient Responses of the Modeling Charge Pump Regulator

In section 5.3, a design example of charge pump regulator based on the proposed equivalent model is presented. The time-domain characteristics of this regulator are represented by the transient and the steady-state responses of the system when certain test signals are applied. Short disturbances or impulse inputs might alter the output temporarily, but the regulator will return to the desired operating point.

The transient performance of the compensated regulator is characterized by changing the resistive load RL and the reference voltage Vref as different step inputs. Since Vref is related to the output voltage by the feedback factor β of 1/3, the regulating output voltage should be triple as large as the voltage of Vref. Thus, in the standard case of RL = 50 kΩ and Vref = 1V, the simulated output voltage is 3.0002 V, which is very close to the ideal value of 3 V. Its percentage of error is about 0.007%, which displays the accuracy of the regulator in the standard case.

Fig. 5.25(a) shows the output waveform when RL is changed from 50 kΩ to 100 kΩ at a certain moment with Vref = 1V. The final output voltage is 3.0157 V for the error of 0.52%, and the response time is about 0.165 ms. Fig. 5.25(b) shows the output waveform when RL is changed from 50 kΩ to 25 kΩ with Vref = 1V. The final output voltage is 2.981 V for the error of 0.63%, and the response time is about 0.408 ms. Results of several different tests are illustrated in Table 5.7. It can be obtained that the response time would be extended by increasing the amount of resistive load variation (∆RL). In other words, a large response time is caused by a large fluctuation in the pump frequency for achieving the steady-state. It also can be seen that the response time resulted from the condition of decreasing RL is larger than that of increasing RL with the same amount of resistive variation. For example, from Table 5.7,

when the resistive load is reduced from 50 kΩ to 25 kΩ at Vref = 1 V, the response time is about 0.408 ms. It is larger than the response time of 0.177 ms, which is reacted by increasing RL from 25 kΩ to 50 kΩ. In addition, the reference voltage also brings about the change of the transient performance. A higher Vref will cause a rise of the response time.

(a)

(b)

Fig. 5.25 Transient output response of the compensated regulator with a resistive load variation at Vref = 1V. (a) RL is changed from 50 kΩ to 100 kΩ. (b) RL is changed from 50 kΩ to 25 kΩ.

Table. 5.7 Results of the resistive load variation tests.

Initial RL Final RL Response Time

at Vref = 0.8 V Response Time

Furthermore, it is informative to observe the system behavior by changing the reference voltage Vref as a step input. Fig. 5.26 (a) and (b) show the output waveforms corresponding to Vref changed from 1 V to 1.2 V and changed from 1 V to 0.8 V, respectively, at a certain moment with the standard case of RL = 50 kΩ. The steady state of the regulating output voltage would be very close to 3Vref by the feedback factor β of 1/3. From these figures, it can be seen that the output approaches the final value without any oscillations and overshoot.

These responses can be considered as overdamped cases of a second-order system, where the damping ratio ζ ≥0.707.

All various levels shift in the reference voltage with different RL are tested, and the results are summarized in Table 5.8 and Table 5.9. Table 5.8 illustrates the response information with respect to Vref changed from a fixed voltage of 1 V under different RL, and Table 5.9 shows the results with respect to Vref changed from different voltage level with the standard RL of 50 kΩ.

It can be seen that a large response time is caused by a large increment or decrement of the reference voltage (∆Vref). Besides, the response time resulted from the condition of increasing Vref is larger than that of decreasing Vref with the same shifted amount of the reference voltage.

For example, when Vref is reduced from 1 V to 0.8 V at RL = 50 kΩ, the response time is about 0.134 ms. It is smaller than the response time of 0.209 ms, which is reacted by increasing Vref

from 0.8 V to 1 V. In addition, a smaller RL will cause a rise in the response time.

(a)

(b)

Fig. 5.26 Transient output response of the compensated regulator with a reference voltage variation at RL = 50 kΩ. (a) Vref is changed from 1 V to 1.2 V. (b) Vref is changed from 1 V to 0.8 V.

Table. 5.8 Results of the reference voltage variation tests with respect to Vref centered at 1V with different resistances of RL.

Initial

Table 5.9 Results of the reference voltage variation tests with respect to Vref changed from different center voltage levels with the standard RL of 50 kΩ.

Initial

Further analysis of the data in Table 5.7 to 5.9 indicates that the response time might be increased if the operating pump frequency is required to increase for reaching the final steady state. Thus, a large increment of Vref or a large decrement of RL as a step input requires large time for the response to reach and stay within a range about the final value. From the simulation, the largest response time about 0.864 ms occurs in the condition of Vref changed from 0.8 V to 1.2 V at RL = 25 kΩ. Based on the design procedure mentioned above, transient-response specifications can be summarized in Table 5.10.

Table 5.10 Transient-response specifications.

Allowable Variation Range of Resistive Load 25kΩ to 100kΩ Allowable Shift Level of Reference Voltage 0.8V to 1.2V Allowable Range of Output Voltage 2.4V to 3.6V Allowable Range of Output Current 24µA to 144µA Maximum Response Time < 0.9ms Maximum Percentage of Error < 2%

Start-Up Time < 2ms

5.4.2 Transient Responses of the Practical Charge Pump Regulator

A simple implementation of the practical compensated charge pump regulator in transistor level is shown in Fig. 5.27. The circuit is simulated in a TSMC mix-mode 0.35 µm CMOS process technology. All design parameters of the practical circuit are in complete accord with those of the modeling design example mentioned above. Table 5.11 shows the simulated average output voltage (Vo,avg) and the corresponding percentage error of the practical regulator in the steady state with different resistors and different reference voltages. The results of the average output voltage are almost identical as those in the modeling design example, and all percentage errors are less than 2 % when Vref is of 0.8 V to 1.1 V. The output ripple is lower than 0.2 V with this frequency regulation method.

Fig. 5.27 Schematic diagram of a simple compensated charge pump regulator.

Table 5.11 Simulation results of average output voltage and the corresponding percentage error in the steady state with different resistors and different reference voltages.

Reference Voltage RL = 25 kΩ RL = 50 kΩ RL = 100 kΩ

Vo,avg 2.387 V 2.423 V 2.442 V

Vref = 0.8 V

error 0.542 % 0.958 % 1.750 %

V_o,avg 2.676 V 2.711 V 2.736 V

Vref = 0.9 V

error 0.889 % 0.407 % 1.333 %

Vo,avg 2.953 V 2.989 V 3.031 V

V_ref = 1.0 V

error 1.567 % 0.367 % 1.033 %

V_o,avg 3.248 V 3.283 V 3.322 V

Vref = 1.1 V

error 1.576 % 0.515 % 0.667 %

Vo,avg 3.489 V 3.527 V 3.563 V

V_ref = 1.2 V

error 3.08 % 2.028 % 1.028 %

Fig. 5.28(a) and (b) show the output waveforms when RL is changed instantly from 50 kΩ to 100 kΩ and when RL is changed instantly from 50 kΩ to 25 kΩ, respectively, with Vref = 1V.

The pump clock frequency automatically decreases when the resistive load becomes lighter.

Compared with Fig. 5.25, the results obtained agree approximately with those expected. In addition, the effects of changing the reference voltage as a step input are also tested. Fig. 5.29 (a) and (b) show the output waveforms corresponding to Vref changed from 1 V to 1.2 V and changed from 1 V to 0.8 V, respectively, with the standard case of RL = 50 kΩ. The simulation results agree with those obtained in Fig. 5.26. In fact, other simulation tests of the practical regulator design under different conditions are also made, and the results confirm those of the modeling regulator design described in section 5.4.1. Therefore, the characteristics of this practical regulator design would correspond to the transient-response specifications given in Table 5.10.

(a)

(b)

Fig. 5.28 Transient output response of the practical regulator with a resistive load variation at Vref = 1V. (a) RL is changed from 50 kΩ to 100 kΩ. (b) RL is changed from 50 kΩ to 25 kΩ.

(a)

(b)

Fig. 5.29 Transient output response of the practical regulator with a reference voltage variation at RL = 50 kΩ. (a) Vref is changed from 1 V to 1.2 V. (b) Vref is changed from 1 V to 0.8 V.

5.5 Summary

Based on the presented design procedure, a charge pump regulator with a frequency compensation scheme can be implemented and the characteristics can be designed though manual and/or computer analysis of the equivalent model. This analytical model helps to plan a charge pump regulator and its design tradeoffs. The regulator provides a negative feedback to the pump, insuring that the pump output will be constant, regardless of process, environment and loading conditions. Short disturbances such as resistive load variation or impulse inputs such as reference voltage shift might alter the output voltage temporarily, but the regulator will return to the desired operating point.

From the design example, the proposed design procedure is verified by comparing the simulation results of the practical regulator and analytical data from the modeling design. The

two sets of results are found to be practically identical. Thus, the accuracy of the modeling design has been demonstrated. Performance data are summarized in Table 5.12. It should be noted that the allowable discrepancy in the two sets reflects a slight error in the idealization of the model.

In addition, this charge pump regulator scheme can be built with discrete components, or be integrated on an IC chip. In the first case, a high output voltage and large output power and can be obtained by using power MOSFETs and large discrete capacitors. In the second case, smaller power and output voltage can be delivered by small capacitors operating at higher frequency.

Table 5.12 Performance summary of the regulator example.

Min. Typ. Max.

Supply Voltage 1.5V

Resistive Load 25kΩ 50kΩ 100kΩ

Reference Voltage 0.8V 1.0V 1.2V

Output Voltage 2.4V 3.0V 3.6V

Output Current 24µA 60µA 144µA Output Ripple 0.15V 0.2V 0.25V

Response Time < 0.9ms

Error Percentage < 2%

Start-Up Time < 2ms

Chapter 6

Conclusions and Suggestions

6.1 Conlusions

Nowadays, the perspective is changing. As the power supply scales down, other critical circuits whose performances are strongly dependent on core power supply levels and variations will require a dedicated and stabilized supply voltage, higher or lower than V_DD. High voltage generator is therefore one of the key challenges of designers. In this thesis, the discussions are focused on charge pump designs for low voltage applications.

Conventional CPCs have deficiencies such as a large cascade stage number for a high pump output voltage, and the saturated limitation of the output voltage. Thus, the output voltage cannot be maintained as a linear function of the number of stages and the pumping efficiency will be degraded as the number of stages increase further. Several modifications have been presented and discussed in chapter 2.

In chapter 3, in order to overcome above problems, the pumping gain increase circuits are proposed to solve the voltage drop across the MOSFET charge transfer switches in the inner stages and the output stage caused by the threshold voltage increase problem. Thus, the output voltage increases more linearly versus the pumping stage number. From the simulation results, the PGI-3 circuit exhibits the best charge pumping performance among these three different PGI circuits, and the pumping gain of PGI-3 is very close to the ideal value without the saturation problem. The output voltage of PGI-3 can easily exceed 10 V with a 1.5 V supply

when six pumping stages are used.

In addition, an exponential-gain structure with high voltage transfer efficiency is also presented in chapter 3 as a further application of the PGI circuit. It can pump output voltage exponentially in fewer voltage pump stages from a low power supply without output voltage saturated limitation. The simulation results have shown that the exponential-folds pump structure can be applied to produce any structure with nⁱ architecture, such as that one can use a 3×3 circuit to generate a boosted output above 12V from a 1.5V supply under a 0.35 µm process. A 2×2 CPC is demonstrated using this technique from a 1.5 V supply voltage. It is conceivable that this charge pump styled voltage generator can be well suited to many types of portable equipment that require a high voltage from a low voltage source such as one battery cell.

In chapter 4, analysis and modeling technique of on-chip charge pumps with a resistive load based on pump gain increase circuits have been proposed. The equations of the model, which are useful for a pencil and paper design, also have been deduced for planning the circuit to achieve good enough performance with an acceptable accuracy tolerance in the steady state. Thus, the characteristics of PGI circuits can be approximately predicted and the circuit parameters can be determined in satisfying the requirement. In addition, an optimized design method for PGI circuits with a resistive load is developed in terms of the total number of gain stages in the design and the ratio between pump capacitors.

For 1.5 V supply voltage operation, reliability and accuracy are demonstrated by comparisons between SPICE simulations of the PGI circuit and the result of the equivalent model. The model also has been validated by means of measurements taken from a test chip and all the relative errors of measurements are less than 5 %. Finally, although the derivation of the model was based on PGI circuits, it is shown that the same design strategy can also be applied to any improved charge pump design which is able to eliminate the voltage drop within the inner stages and the output stage as an ideal case.

In chapter 5, the proposed equivalent model can be applied to design a charge pump regulator which is independent of the current drawn by load variations. By using this equivalent model, characterization of regulator can be performed in mathematical analysis with a pencil-and-paper manner. The presented regulator adopts the automatic pumping frequency scheme including a voltage-controlled oscillator, a charge pump circuit, an error detector, and a compensator. This control scheme provides negative feedback to the pump operation, insuring that the pump clock frequency would be changed automatically for generating a desired output voltage regardless of load current variations.

A design example of the charge pump regulator at the range of regulated output voltage from 2.4 V to 3.6 V across different resistive loads is used to illustrate the design procedure based on the equivalent model. In the case of regulator design, simulation can be carried out interactively during each design step to immediately check the consequence of a design decision, and the following procedure could be applied to plan the overall design:

1. Design the circuit parameters of the pumping gain increase circuit to comply with the required specifications through analyzing the model.

2. Design the voltage-controlled oscillator to agree with the required center frequency and the operating range, which can be determined by the information of output voltage variations according with the pump frequency fluctuations under different loading conditions.

3. Combine the voltage-controlled oscillator with the equivalent model to form the un-regulated charge pump converter. Its low-frequency gain and the dominant pole can be obtained by the AC small-signal simulation. This information is useful for characteri-zation of the open-loop and close-loop system though manual and/or computer analysis.

4. Design the feedback loop of the converter to meet the static and dynamic requirements.

To ensure stability of the regulator, it is necessary to introduce the compensator design.

Check the compatibility of the chosen compensator to the regulator by frequency

response simulations.

5. If closed loop instability is expected, damp the feedback or redesign the compensator to meet the basic stability criteria.

6. Check the transient response to meet specifications. If the regulator does not meet specifications, repeat step (5) or trim the loop gain to improve performance.

From the design example, the accuracy of the modeling design has been demonstrated by comparing the simulation results between the modeling and the practical regulator.

Consequently, based on the presented design procedure, a charge pump regulator can be implemented and the characteristics can be planned by analyzing the proposed equivalent model. The primary advantage of the modeling approach presented here is the ease by which the regulator system can be analyzed. This permits the development of charge pump regulator designs.

6.2 Suggestions for Future Works

The following issues raised in the course of this study appear to merit further investigation.

The traditional electrostatic discharge (ESD) protection circuits are not suitable for these applications. The more robust ESD protection circuits are required in low-voltage processes and must be developed.

Several clock signals with high voltage amplitude are generated in charge pump circuits for controlling the transfer switches, so that the cross coupling effect due to layout drawing occurs in the course of the clock signal transmission. The shielding work is required and must be discussed.

The gate-drain and the gate-source voltage of all devices in the proposed circuits might be large, so the proposed circuit will suffer the gate-oxide reliable problem. Especially the

operation frequency becomes higher in the advanced ICs, not only the DC overstress on the gate oxide but also the AC overstress must be considered in the high-voltage circuits realized with low-voltage devices in the future IC design.

The presented regulator can be considered as a stable overdamped case since it does not yield any oscillations and overshoot in transient responses. However, an overdamped system is always sluggish in responding to any inputs. From the control theory, it is desirable to improve the damping ratio of the system between 0.4 and 0.8 for sufficiently fast and damped transient responses.

In actual applications, since leakage currents discharge charge pump output and internal nodes, a standby scheme is necessary to charge pump operations for minimizing overall chip power consumption. In addition, when the transfer switch operates from standby to the active mode, the pumping output voltage cannot be provided with the required accuracy very rapidly due to the long setup transient of the pump circuit especially with a heavy load. To avoid the ensuing unacceptable penalty in the transient time when entering the pump mode from the standby condition, an effective high voltage standby management is necessary.

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