Several modified charge pump circuits based on the Dickson structure were reported to enhance the pumping efficiency [1], [6], [23]-[36]. Based on process techniques, several attempts have been made to implement fully isolated p-n junction diodes in the Dickson charge pump circuit shown in Fig. 2.1 [1], [26]-[29]. Besides, in the case of using MOS-
diodes as transfer devices, some processes make use of ion implantations to adjust the threshold voltage of the transistor to the desired value and to improve the punch-through feature of transistors.
2.3.1 Normal Transfer Device
Traditionally, a p+/n-well diode with the grounded p-substrate as shown in Fig. 2.5 is a kind of p-n junction diodes in the standard CMOS process; nevertheless, an undesired parasitic p-n junction exists between the n-well and the grounded p-type substrate. If the voltage on the cathode of the p+/n-well diode is larger than the junction breakdown voltage between the n-well and the grounded p-substrate, the charge on the cathode will leak to ground through this parasitic p-n junction. Besides, it can also be found that the p+/n-well diode exhibits a vertical parasitic bipolar transistor, which is in part responsible for leakage currents.
Fig. 2.5 Cross-section of an p+/n-well diode created on an n-well using p+ and n+ diffusions with the grounded p-substrate.
A diode-connected NMOS transistor, whose gate and drain are connected, with the grounded p-substrate is another kind of p-n junction diodes in the standard CMOS process as shown in Fig. 2.6(a). Similarly, an undesired p-n junction parasitizes between the n+ region (source/drain) and the grounded p-type substrate. If the voltage on the cathode or anode of the transistor is larger than the junction breakdown voltage between the n+ region and the grounded p-type substrate, the charge will also leak to ground through this parasitic junction.
It is also found in this structure that the lateral parasitic bipolar transistor would result in leakage currents.
(a) (b)
Fig. 2.6 Cross-section of an diode-connected NMOS transistor with the grounded p-substrate. (a) Standard NMOS transistor. (b) High voltage NMOS transistor.
Another high breakdown voltage structure of an NMOS transistor is that the source and drain regions are surrounded by separate n-wells shown in Fig. 2.6(b). The n-well is lower doped than conventional n-diffusions thus allowing the possibility of a higher breakdown voltage. Using this power NMOS to substitute for a standard NMOS in diode-connected style, it can be seen that higher breakdown voltages of the power NMOS will reduce the limitation from undesired junctions. However, the layout is atypical in that the active layer was added beneath the gate in order to achieve thin oxide in the gate to n-well overlap region.
Consequently, while above normal transfer devices are used in the Dickson charge pump circuit, the maximum output voltage and the pumping efficiency will be limited by the breakdown voltage of the undesired junction. In addition, parasitic devices are in part responsible for leakage currents.
2.3.2 Utilizing Body Diode as the Transfer Device
The implementation of silicon-on-insulator (SOI) MOSFET body diodes in place of typical transfer devices reduces the voltage drop across each stage and increases the voltage effi-ciency of the charge pump [27]. In an SOI process, each MOSFET body is isolated from
neighboring transistors due to the buried oxide (BOX) layer. The cross section of an n-channel SOI transistor is shown in Fig. 2.7, and the two p-n junctions of this structure form a back-to-back diode configuration as indicated in the drawing.
Fig. 2.7 Cross-section of an SOI n-channel device for body diode connection.
For body diode implementation, the floating-body of the n-channel is connected to the drain, thus shorting the junction from the p-type body to the n-type drain. Hence, only one diode exists between the gate-drain-body connection and the source. In this configuration, the gate-drain-body connection will serve as the anode and the source as the cathode. Fig. 2.8 shows the two-dimensional structure of an SOI NMOS body-diode under gate-drain-body connection. The vertical white line represents the p-n junction of the body diode, where the right side is the anode or p-type region of the NMOS structure and the left side is the cathode or n-type source region.
The build-in voltage across this silicon body diode is approximately 0.4 V. Comparing with the transfer device realized by transistors in the diode-connected style, using body diodes can prevent the augmented threshold voltage problem as the pump stage number increases.
Furthermore, since the device is isolated to others by the insulation layer in the SOI CMOS process, charge pump circuits realized by the body diode can pump the output voltage higher without the limitation of parasitic p-n junctions, such as the breakdown voltage of undesired
junctions or leakage currents. However, the voltage pumping gain per stage is still reduced by the build-in voltage of the body diode, and the SOI CMOS process is more expensive than the common bulk CMOS process.
Fig. 2.8 2-D structure of an SOI NMOS body-diode [27].
2.3.3 Utilizing Polysilicon Diode as the Transfer Device
In the past, it is difficult to implement fully isolated p-n-junction diodes in the common silicon substrate. In the recent sub-quarter-micron standard CMOS process with shallow trench isolation (STI) [37], the polysilicon diode, which is fully isolated from the silicon substrate, can be implemented and applied in the charge pump circuit [28].
As shown in Fig. 2.9, the polysilicon diode can be realized on the polysilicon layer in the recent STI process which has separated doping impurities for PMOS and NMOS gates. The STI layer is located above the silicon substrate. The intrinsic polysilicon layer is deposited on the STI layer, and then the p-type and n-type impurities are doped into the intrinsic polysilicon layer to form the PMOS gate and the NMOS gate, respectively. An extra un-doped (intrinsic) polysilicon region (i) can be inserted between the p-type and n-type doped polysilicon regions. The length Lc of the un-doped region can be used to adjust the I–V
characteristic of the polysilicon diode.
Fig. 2.9 Schematic cross section of the polysilicon diode.
Because the polysilicon diode is implemented on the STI layer, it is isolated from the silicon substrate. Charges on the anode and the cathode of the polysilicon diode would not leak to the silicon substrate. In addition, the parasitic capacitance of the polysilicon diode formed on the STI layer has been studied in [38], which is smaller than those of traditional p+/n-well junction diodes and MOS diodes. Therefore, the polysilicon diode can be applied to the charge pump circuit without the limitation of parasitic junctions for achieving better pumping efficiency.
2.3.4 Utilizing Triple-Well Technique
Triple-well technology has become popular for charge pump circuit fabrication as it allows easier handling of the negative voltages necessary when the negative-gate erase technology is adopted. With this kind of technology shown in Fig. 2.10, p-well/n+ junction diodes can be used with no risk of charge injection into the substrate, since the p-well region is isolated from the p-substrate by a reverse-biased n-well. In addition, when the triple-well process is used, the gate-drain connection for a MOS diode, which implements a charge transfer device, can also be applied with isolation. Therefore, based on the triple-well technology, p-well/n+
junction diodes or MOS diodes applied to the charge pump circuit would reduce the leakage current from parasitic junctions.
However, if the triple-well p-well/n+ junction diode is used, the pumping voltage per stage is still reduced by the build-in voltage. If the triple-well MOS diode is applied, the Vt
augmentation problem still exists and the pumping efficiency of the succeeding stage is still less than that of the forestage.
Fig. 2.10 Schematic cross section of the NMOS transfer device in triple-well process.