Architecture

Since most CPC’s have a linear growing structure and voltage gain losses, many stages will be needed to obtain high output voltages. Moreover, due to Vt augmentation problem, they will not achieve higher output voltages. Thus, an exponential-gain pump structure is proposed to solve the voltage saturation by making the clock voltage grows exponentially along with the number of stages cascaded. Compared with the linear-gain structure shown in Fig. 3.13(a), the exponential-gain pump structure, shown in Fig. 3.13(b), adopts less stage number to support the same output voltage.

(a)

(b)

Fig. 3.13 A conceptual block diagram of eight-fold voltage gain by using (a) a linear growing structure in 7-stage case and (b) an exponential-gain pump structure in 3-stage case.

An n-times voltage multiplier is the fundamental cell of this structure. The output of this fundamental cell is connected as the power supply to the next one. With i cascaded cells, an

exponential-gain pump structure will be formed to provide the total voltage gain of nⁱ. In Fig.

3.13(b), the system can be considered as a 2³ exponential-gain pump structure formed by three cascaded voltage doublers. It should be noted that with this structure the output voltage will be confined by the fabrication process. To obtain a high output voltage which exceeds the breakdown voltage of the low voltage chip, the cascaded cells need to be placed in a chip or in discrete chips fabricated by the process which can provide a breakdown voltage higher than the operating voltage.

In Fig. 3.14, an exponential-gain example of a 2×2 charge pump circuit denoted by 2×2 CPC is proposed. The first stage of a 2× PGI-1 circuit, named Cell-1, is used to provide the supply voltage (Vo1) of the next 2× PGI-1 circuit. If more cells are cascaded, then the voltage of whole charge pump circuit will grow exponentially. From (3.12), since the growth of clock voltage is always greater than the growth of Vt in this structure, the Vt problem can be suppressed very well.

Fig. 3.14 The block diagram of a 2×2 exponential-gain pump structure.

Other 2× cells based on PGI-2 and PGI-3 circuits have also been used to realize a 2×2 CPC.

The advantage of this new structure can be viewed in several ways: fewer stages, lower power dissipation from switching, and high flexibility. Since the complexity of the circuit and the pumping stage number in each cell has been reduced, the parasitic effect has also been

reduced and the output saturation problem will not occur, even though PGI-2 or NCP2 are used as the fundamental cell. The number of switches is decreased substantially and the power loss from switching is also reduced. In addition, a higher pumping gain can be obtained more flexibly by appropriately adjusting the number of CPC stages in each cell or the number of cascaded cells. Thus this structure is not only suited for high pumping gain, especially in high output voltage and low supply voltage applications, but also simplifies the whole circuit configuration.

3.3.2 Simulation and Measurement Results

Fig. 3.15 shows the transient simulation results of the three-stage PGI-1, PGI-2, PGI-3, and the proposed exponential-gain 2×2 CPC based on the PGI-1 as the fundamental cell. All of these circuits are designed for a 4× ideal pumping gain in the condition of light load and simulated with the same technology. The geometric size of each design is almost identical in all devices without optimal sizing. The simulation results show that the output voltage of the 2×2 CPC is a little smaller than those of the PGI-1 and PGI-3, and that can be ascribed to the extra power consumption from the internal comparator and buffer of the exponential-gain pump structure.

Fig. 3.15 Simulated transient output waveforms of 2×2 CPC and various 3-stage PGI circuits with Vin = Vclk = 1.5 V and Iout = 10 µA.

The simulated output voltages versus expected gain of PGI-1, PGI-3, and exponential-gain CPC are summarized in Fig.3.16 and Table 3.1. Ideally, an (N-1)-stage linear CPC, such as PGI-1 and PGI-3, can generate an output voltage closed to N-fold of the supply voltage. In the case of the exponential-gain structure, the output voltage is close to the ideal value without any saturation problem in the present testing range and easily exceeds 10 V when using a 3×3 CPC with a 1.5 V supply. Table 3.1 also shows that the exponential-gain structure has high flexibility to generate a desired output voltage.

Fig. 3.16 Simulated output voltage versus expected gain of exponential-gain structure, PGI-1, and PGI-3 with Vin = Vclk = 1.5 V and Iout = 10 µA.

Table 3.1 Comparison of output voltages generated by PGI-1 and exponential-gain structure over several gain configurations.

Ideal Folds

A 2×2 CPC using PGI-1, PGI-2, and PGI-3 for the fundamental cell has been fabricated with a standard 0.35-µm CMOS technology. Fig. 3.17 summarizes the measured output voltage versus various supply voltages, 1.3 V to 2.2 V, and a 10 µA output load current. The measured data show that the output voltages of 2×2 CPC’s formed by PGI-2 or PGI-3 are lower than those formed by PGI-1. The main reason for this effect is that PGI-2 and PGI-3 use PMOS switches deficient in the driving abilities of charge transfer devices. The measured results also show that the output voltage of the exponential-gain CPC using PGI-1 has a tendency to saturate when the supply voltage exceeds 2 V. This is due to the breakdown voltage limitation of the process having been reached in the PGI-1 circuit of Cell-2.

Fig. 3.17 Measured output voltages of 2×2 CPC using PGI-1, PGI-2 and PGI-3 under different supply voltages.

3.4 Summary

The conventional charge pump circuit always suffers from the problem of increased drain-source voltage drop Vds across each charge transfer MOS switch, where Vds is affected by the threshold voltage affected by the body effect. Thus, the output voltage cannot be maintained as a linear function of the number of stages and the pumping efficiency will be degraded as the stage number increases further. Novel MOS charge pumps utilizing an exponential-gain structure and pumping gain increase circuits with high voltage transfer efficiency to generate boosted output voltages have been described to overcome key problems in CPC designs.

First, three different PGI circuits are proposed to reduce the voltage drop across the output stage and inner charge transfer MOS switches. The PGI circuits allow the output voltage to increase linearly as the number of pumping stages increases. However, in PGI-1 and PGI-2, the threshold voltage increase problem still exists and limits the output voltage, as the stage number gets too large. In PGI-3, there is no saturation limit, since |Vgs| of each CTS can always be larger than |Vtp|. Therefore, the output voltage is close to the ideal level and the charge transfer efficiency can be enhanced. The main results of the comparison with these three PGI circuits are provided in Table 3.2.

Table 3.2 Comparison with the three different PGI circuits.

pumping

The second design is an exponential-gain pump structure that can pump the output voltage exponentially from a low power supply without an output saturation effect. This structure can be applied to produce any pumping gain with its nⁱ architecture. For example, a 2×2 (2²) CPC

can be used to generate a boosted output of 6 V with a 1.5 V supply voltage. As shown in simulation and measurement results, the proposed designs are able to generate high voltages efficiently from a power supply below 2 V. A three-stage PGI-3 circuit or a 2×2 CPC can generate a boosted output close to the ideal value of 6 V from a 1.5 V supply.

Thus, it is conceivable that PGI circuits and the exponential-folds structure can be applied to generate high output voltages more effectively from a low voltage source such as using a battery cell.

Chapter 4

Analysis and Modeling of On-Chip Pumping Gain Increase Circuits with a Resistive Load

4.1 Introduction

In recent years, many efforts have been made in the analysis and optimization of the Dickson structure in order to support a convenient and rapid design scheme [23]-[25], [40], [41]. Similarly, in this chapter, a thorough analysis and a complete average model of the pumping gain increase (PGI) circuit, which is a type of improved charge pump circuits, with a resistive load have been presented. Based on this simple analytical model, the characteristics of PGI circuits can be approximately predicted and several handy equations can also be found for planning the desired circuit to achieve good enough performance with an acceptable accuracy tolerance in the steady state.

In section 4.2, a general equivalent model based on PGI circuits is described. Analyses based on the charge balance and average conceptions are presented. By using this simple analytical model, characterization of PGI circuits can be performed in a pencil-and-paper manner and the output behavior can be approximately determined. An optimization design method for minimizing the die area of an N-stage PGI circuit in terms of the total number of pump stages and the pump capacitor ratio is also presented. This design strategy can also be

applied to other improved CPC designs that have no voltage drop within the inner stages and the output stage. In section 4.3, simulation results are presented to verify this equivalent model for designing PGI circuits. Presented in Section 4.4, experimental results measured from a test chip that was fabricated with a TSMC 0.35-µm mixed-mode technology demonstrate the validity of the proposed model. Conclusions are given in Section 4.5.