PGI-1 Circuit

The pumping gain increase circuit develops from the NCP2 circuit which utilizes dynamic CTS’s to assign the gate control input of each transfer switch to the higher voltage level provided by the next pump stage. However, with the increasing pump voltage at the source terminal of each charge transfer switch, the threshold voltage Vt still unavoidably grows along with the increased source-body voltage (Vsb). In the last CTS, there is no succeeding stage to generate any higher voltage level. When the pump stage number increases to a value such that the gate control voltage (Vgs) of the last CTS cannot exceed the increased Vt, the limited gate control voltage would cause undesired operations in last few stages and the pumping output voltage will arrive at the saturation level. Although CTS’s in inner stages have high transfer efficiency, but ones in last few stages would have low transfer efficiency. In addition, NCP2 uses an NMOS-diode in the output stage to prevent reverse charge injection from the output node, so that a large voltage will be dropped across the diode due to the augmented threshold voltage problem.

Instead of using the diode-configured MOS switch at the output stage in NCP2, a pumping gain increase circuit denoted by PGI-1 is proposed. Fig. 3.1 shows a charge pump circuit built by a three-stage NCP2 circuit with a PGI-1 circuit at the back. The objective is to increase the voltage level of the switch control signal in the last pump stage and to eliminate the voltage drop across the output stage. The main idea is similar to the circuit shown in Fig. 2.18 introducing the extra gate bias circuit to the main charge pumps. In PGI-1 circuit, only a small auxiliary CTS is added to provide a high voltage level, which is larger than the increased threshold voltage, to drive the last CTS and the output switch, so that all pump stages including of the output one would have perfect pumping performance.

Fig. 3.1 A three-stage NCP2 using PGI-1 as its output stage.

The operation of the PGI-1 circuit is explained as follows. In Fig. 3.1, clk and clk are out-of-phase and have the same voltage amplitude Vclk. The MOS diode (MDx) is used to establish initial voltages. When clk is low and clk is high, the voltage V2 and V4 of nodes 2 and 4 are raised to higher potential levels. In the ideal case, the gate-source voltage of MP1 and MP3 can be obtained as

gs,MP1 gs,MP3 2 clk

V =V = V (3.1)

If 2V_clk >V_tp0 (3.2)

where Vtp0 is the threshold voltage of PMOS transistor for Vsb = 0, then MP1 and MP3 would be turned on, causing the gate-source voltage of MS1 and MS3 as

gs,MS1 gs,MS3 2 clk

V =V = V (3.3)

Assuming that

clk tn,MS3 tn,MS1

2V >V >V (3.4)

the switches MS1 and MS3 will be turned on completely by the raising voltage V2 and V4, respectively. In this period, MN1 and MN3 are always OFF since the gate-source voltages are

both zero. Thus, the pump capacitors C1 and C3 will be charged through MS1 and MS3, causing the voltage V1 and V3 of nodes 1 and 3 being pulled up to VDD and (VDD+2Vclk), respectively. Simultaneously, Cc is further charged through MDC.

On the other hand, since V2 and V4 are raised to higher potential levels, the gate-source voltage of MN2 and MNO can be obtained as

gs,MN2 gs,MNO 2 clk

V =V = V (3.5)

Assuming that

clk tn,MNO tn,MN2

2V >V >V (3.6)

then MN2 and MNO would be turned on, causing MS2, MSA, and MSO being turned off by the lower voltage V1 and V3 to prevent reverse charge injection.

Similarly, when clk is high and clk is low, the voltages V1, V3 and V5 are raised to higher potential levels. The high voltage V3 leads the preceding switch MS2 to be turned on to charge C2. Simultaneously, MSO and MSA are turned on, since V4 is low and V5 is high. Thus, Ca and Co are charged through MDA/MSA and MDO/MSO, respectively. If the control voltage level of MSO is high enough to overcome the augmented Vtn,MSO, MSO can be turned on and the pump efficiency of the output stage can be kept as high as that of the forestages.

The choice between an NMOS diode and a PMOS diode for MDC is an important design issue of PGI-1. Although PGI-1 can eliminate the Vds drop in the output stage, the Vtn increase still exists and affects the internal charge transfer devices, especially when MDC is an NMOS diode. For the case of an NMOS diode based MDC, the pumping voltage in the circuit can be expressed as follows:

(

)

Cc Ca

V  V +V −V (3.8)

where Ca > Cc and VCc are the voltages across Cc.

From (3.7), a complete conduction of MSA is needed to obtain higher VCa which is established by (VC3+Vclk). From (3.8), the corresponding gate control voltage of MS3 and MSA for conduction is provided by (VCa+Vclk) and (VCc+Vclk), respectively, where VCc is established by [(VCa+Vclk) – Vds,MDC]. To turn on MSO and MSA and to give perfect pumping efficiency in the output stage, Vgs,MSO and Vgs,MSA must be high enough to conquer their threshold voltages. Thus, the lower-bound condition for turning on MSO and MSA must be satisfied: and MSA will have the same value. Substituting (3.8) into (3.9), the lower-bound condition for turning on MSO can be obtained as

gs,MSO 2 clk ds,MDC tn,MSO

V  V −V >V (3.10)

In (3.10), the threshold voltage depends on the body effect and can be obtained by

( )

th th0 γ 2 _{f sb} 2 _f

V =V + φ +V − φ (3.11)

where Vth0 is the threshold voltage with Vsb =0. The Fermi level φ_f and the parameter γ are constant values if the process characteristics are fixed. From (3.11), it can be seen that the increasing Vsb,MSO results in increasing the value of Vtn,MSO. Similarly, if MDC is an NMOS diode, a large Vds,MDC will occur due to a large Vsb,MDC. From (3.10), since the only constant is Vclk, the formula of the lower-bound condition for turning on MSO can be changed as

clk tn,MSO ds,MDC

2V >V +V (3.12)

When the sum of augmented Vtn,MSO and Vds,MDC is larger than 2Vclk, MSO and MSA will not turn on and Vout will start to saturate.

With the aid of (3.11) and (3.12), the approximate value of the output saturation voltage can be graphically determined from Fig. 3.2. Line-1 is the threshold voltage of MSO (Vtn,MSO) with respect to various Vout. In the proposed circuit, all the bodies of NMOS transistors are connected to ground. Since the source of MSO is connected to the output terminal in PGI-1, Vout is equivalent to Vsb,MSO. Thus, Vtn,MSO can be obtained by substituting Vout to (3.11) and that produces Line-1. When MDC is an NMOS diode, Vgs,MSO can be calculated from (3.10) once Vds,MDC is known. However, Vds,MDC should be determined by its subthreshold voltage, which is smaller than Vtn,MDC. To obtain Vds,MDC, SPICE simulation results were used to sketch Line-2. Line-3, which indicates Vgs,MSO, was obtained by calculating (3.10) with Vclk value and Line-2. Thus, the intersection of Line-1 and Line-3 gives the critical value of Vgs,MSO = Vtn,MSO. The intersection at point 1 shows that the saturation point of Vout is about 4 V while Vclk = 1.5 V. Thus, if more than two pump stages are used in PGI-1 circuit with MDC of NMOS diode and VDD = Vclk = 1.5 V, Vout will start to saturate around 4 V.

An alternative design employed to solve the saturation problem uses a P-MOSFET, based on an N-well/P-substrate, for the MDC in the modified PGI-1. The body of the PMOS is connected to its output side so that the MDC operates as a forward-biased PN junction diode in the charging periods of Cc. This PMOS diode can be easily implemented with a standard CMOS process. Base on the PMOS-diode MDC, the simulation result shows that the Vds,MDC

voltage drop is fixed to a small value about 0.5 V and the PMOS-diode MDC no longer has the augmented Vt problem. Thus, the saturation voltage of Vout can be increased further according to (3.10), which denotes that Vds,MDC is about 0.5 V. However, the MSO switch still affects the saturation effect. From the intersection at point 2 in Fig. 3.2, the saturated output voltage has been increased to about 8.8 V where both VDD and Vclk are 1.5 V.

Fig. 3.2 The graphical solution for obtaining the output saturation voltage in PGI-1 circuit, shown in Fig. 3.1, under NMOS-diode MDC and PMOS-diode MDC where VDD

and Vclk are 1.5 V and all the voltages are taken when clk is high.