CHAPTER 2 OVERVIEW ON POWER MOSFETs FOR
3.3 Summary
In 0.25μm 18V BCD process, to increase the N_C spacing of drain side in LD-NMOS can improve the holding voltage, It2 value, HBM and MM ESD levels. The larger N_C spacing can also improve the It2 value in both NFOD and NSCR devices. Moreover, with increasing the polygate length and S spacing in LD-NMOS, NSCR and NFOD, respectively, the trigger voltage is increased substantially. In LD-PMOS, no matter how to modify the layout parameters, the ESD robustness is not improved. So, the LD-PMOS is not a good ESD protection device. In dual-direction SCR, a holding voltage higher than the operation voltage can be obtained by designing proper longitude spacing. The It2 value, HBM and MM ESD levels are higher than the standard ESD specification.
Table 3.1
Various ESD Characteristics of LD-NMOS in different device total width (W).
Table 3.2
Various ESD Characteristics of LD-NMOS in different OD region beyond N+ region of drain side (D_O).
Table 3.3
Various ESD Characteristics of LD-NMOS in different P+ edge to polygate spacing of source side (P_P).
Table 3.4
Various ESD Characteristics of LD-NMOS in different HV NDDD spacing (H_N) and N+
edge to contact spacing (N_C) of drain side.
(a)
(b)
Table 3.5
Various ESD Characteristics of LD-PMOS in different device total width (W).
Table 3.6
Various ESD Characteristics of LD-PMOS in different HV PDDD spacing of drain side (H_P).
Table 3.7
Various ESD Characteristics of LD-PMOS in different P+ edge to contact spacing of drain side (P_C).
Table 3.8
Various ESD Characteristics of LD-PMOS in different N+ edge to polygate spacing of source side (N_P).
Fig. 3.1 The HV BJT structure with controllable trigger and holding voltage.
(a)
(b)
Fig. 3.2 The TLP I-V curves of HV BJT structure with different (a) “t” spacing, (b) “d”
spacing.
(a)
(b)
Fig. 3.3 The cross-sectional views of (a) HV NMOS with N-drift implant and (b) HV NSCR with N-drift implant.
Fig. 3.4 The cross-sectional view of bipolar-triggered SCR (B-SCR).
Fig. 3.5 The TLP I-V curves of bipolar-triggered SCR (B-SCR) with different P+ spacing.
(a)
(b)
Fig. 3.6 (a) The cross-sectional view of LD-NMOS and the modified parameters, (b) The layout view of LD-NMOS and the modified parameters.
1E-7 1E-6 1E-5
Fig. 3.7 (a) The TLP I-V curves of LD-NMOS with different total width, (b) The diagram of the holding voltage and It2 value versus the total width.
1E-7 1E-6 1E-5
Fig. 3.8 (a) The TLP I-V curves of LD-NMOS with different D_O spacing, (b) The diagram of the holding voltage and It2 value versus the D_O spacing.
1E-7 1E-6 1E-5
Fig. 3.9 (a) The TLP I-V curves of LD-NMOS with different P_P spacing, (b) The diagram of the holding voltage and It2 value versus the P_P spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Fig. 3.10 (a) The TLP I-V curves of LD-NMOS with different N_C spacing, (b) The diagram of the holding voltage and It2 value versus the N_C spacing.
1E-7 1E-6 1E-5
Comparing on different NDDD spacing with N_C=1μm TLP of NDDD=4μm
Comparing on different NDDD spacing with N_C=1μm Holding Voltage
It2
(b)
Fig. 3.11 (a) The TLP I-V curves of LD-NMOS with different H_N spacing on N_C = 1μm, (b) The diagram of the holding voltage and It2 value versus the H_N spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Comparing on different NDDD spacing with N_C=2μm
TLP of NDDD=9μm
Comparing on different NDDD spacing with N_C=2μm Holding Voltage
Fig. 3.12 (a) The TLP I-V curves of LD-NMOS with different H_N spacing on N_C = 2μm, (b) The diagram of the holding voltage and It2 value versus the H_N spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Comparing on different NDDD spacing with N_C=3μm
TLP of NDDD=9μm
Comparing on different NDDD spacing with N_C=3μm Holding Voltage
Fig. 3.13 (a) The TLP I-V curves of LD-NMOS with different H_N spacing on N_C = 3μm, (b) The diagram of the holding voltage and It2 value versus the H_N spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Comparing on different NDDD spacing with N_C=4μm
TLP of NDDD=9μm
13.0 Comparing on different NDDD spacing with N_C=4μm Holding Voltage
Fig. 3.14 (a) The TLP I-V curves of LD-NMOS with different H_N spacing on N_C = 4μm, (b) The diagram of the holding voltage and It2 value versus the H_N spacing.
Fig. 3.15 The cross-sectional view of the LD-NMOS with separation source and bulk
Spacing from Source to Bulk=0μm Leakage of W=100μm
Spacing from Source to Bulk=2μm Leakage of W=100μm
Fig. 3.16 LD-NMOS : (a) The TLP I-V curves of different total width with S_B spacing=0μm, (b) The TLP I-V curves of different total width with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different total width.
1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35
0.5 1.0 1.5
TLP of Channel Length=0.35μm TLP of Channel Length=0.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Spacing from Source to Bulk=0μm Leakage of Channel Length=0.35μm Leakage of Channel Length=0.5μm
1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35
0.5 1.0 1.5
TLP of Channel Length=0.35μm TLP of Channel Length=0.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Spacing from Source to Bulk=2μm Leakage of Channel Length=0.35μm Leakage of Channel Length=0.5μm
(a) (b)
Fig. 3.17 LD-NMOS : (a) The TLP I-V curves of different channel length with S_B spacing=0μm, (b) The TLP I-V curves of different channel length with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different channel length.
1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35
0.5 1.0 1.5
TLP of Polygate Length=1μm TLP of Polygate Length=1.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Spacing from Source to Bulk=0μm Leakage of Polygate Length=1μm Leakage of Polygate Length=1.5μm
1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35
0.5 1.0 1.5
TLP of Polygate Length=1μm TLP of Polygate Length=1.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Spacing from Source to Bulk=2μm Leakage of Polygate Length=1μm Leakage of Polygate Length=1.5μm
(a) (b)
Fig. 3.18 LD-NMOS : (a) The TLP I-V curves of different polygate length with S_B spacing=0μm, (b) The TLP I-V curves of different polygate length with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different polygate length.
(a)
(b)
Fig. 3.19 (a) The cross-sectional view of LD-PMOS and the modified parameters, (b) The layout view of LD-PMOS and the modified parameters.
1E-7 1E-6 1E-5 of the holding voltage and It2 value versus the total width.
1E-7 1E-6 1E-5
Fig. 3.21 (a) The TLP I-V curves of LD-PMOS with different H_P spacing, (b) The diagram of the holding voltage and It2 value versus the H_P spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Fig. 3.22 (a) The TLP I-V curves of LD-PMOS with different P_C spacing, (b) The diagram of the holding voltage and It2 value versus the P_C spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Fig. 3.23 (a) The TLP I-V curves of LD-PMOS with different N_P spacing, (b) The diagram of the holding voltage and It2 value versus the N_P spacing.
Fig. 3.24 The cross-sectional view of NFOD and the modified parameters.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=0μm TLP of W=100μm
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=2μm Leakage of W=100μm
Fig. 3.25 NFOD : (a) The TLP I-V curves of different total width with S_B spacing=0μm, (b) The TLP I-V curves of different total width with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different total width.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Spacing from Source to Bulk=0μm TLP of S=1μm
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35 40
Spacing from Source to Bulk=2μm TLP of S=1μm
Fig. 3.26 NFOD : (a) The TLP I-V curves of different S spacing with S_B spacing=0μm, (b) The TLP I-V curves of different S spacing with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different S spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Spacing from Source to Bulk=0μm TLP of N_C=2μm
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=2μm TLP of N_C=2μm spacing=0μm, (b) The TLP I-V curves of different N_C spacing with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different N_C spacing.
Fig. 3.28 (a) The cross-sectional view of dual-direction SCR type I and the modified parameters, (b) The layout diagram of dual-direction SCR type I.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35 40 45 50
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35 40 45 50 curves of different C spacing with ESD zap at node 1, (b) The TLP I-V curves of different C spacing with ESD zap at node 2, (c) The HBM and MM levels versus C spacing with ESD zap at node 1, (d) The HBM and MM levels versus C spacing with ESD zap at node 2.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35 40 45 50 curves of different C spacing with ESD zap at node 1, (b) The TLP I-V curves of different C spacing with ESD zap at node 2, (c) The HBM and MM levels versus C spacing with ESD zap at node 1, (d) The HBM and MM levels versus C spacing with ESD zap at node 2.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35 40 45 50 curves of different S spacing with ESD zap at node 1, (b) The TLP I-V curves of different S spacing with ESD zap at node 2, (c) The HBM and MM levels versus S spacing with ESD zap at node 1, (d) The HBM and MM levels versus S spacing with ESD zap at node 2.
Fig. 3.32 The cross-sectional view of dual-direction SCR type II and the modified parameter.
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0 5 10 15 20 25 30 35 40 45
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35 40 45
Fig. 3.33 Dual-direction SCR type II : (a) The TLP I-V curves of different S spacing with ESD zap at node 1, (b) The TLP I-V curves of different S spacing with ESD zap at node 2, (c) The HBM and MM levels versus S spacing with ESD zap at node 1, (d) The HBM and MM levels versus S spacing with ESD zap at node 2.
Fig. 3.34 The cross-sectional view of dual-direction SCR type III and the modified parameter.
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0 5 10 15 20 25 30 35 40 45
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30 35 40 45
Fig. 3.35 Dual-direction SCR type III : (a) The TLP I-V curves of different S spacing with ESD zap at node 1, (b) The TLP I-V curves of different S spacing with ESD zap at node 2, (c) The HBM and MM levels versus S spacing with ESD zap at node 1, (d) The HBM and MM levels versus S spacing with ESD zap at node 2.
Fig. 3.36 The cross-sectional view of NSCR and the modified parameters.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=0μm TLP of W=100μm
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=2μm Leakage of W=100μm
Fig. 3.37 NSCR : (a) The TLP I-V curves of different total width with S_B spacing=0μm, (b) The TLP I-V curves of different total width with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different total width.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Spacing from Source to Bulk=0μm TLP of N_C=2μm
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=2μm TLP of N_C=2μm spacing=0μm, (b) The TLP I-V curves of different N_C spacing with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different N_C spacing.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Spacing from Source to Bulk=0μm TLP of Polygate Length=1μm TLP of Polygate Length=1.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Leakage of Polygate Length=1μm Leakage of Polygate Length=1.5μm
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=2μm TLP of Polygate Length=1μm TLP of Polygate Length=1.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Leakage of Polygate Length=1μm Leakage of Polygate Length=1.5μm
(a) (b)
Fig. 3.39 NSCR : (a) The TLP I-V curves of different polygate length with S_B spacing=0μm, (b) The TLP I-V curves of different polygate length with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different polygate length.
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
Spacing from Source to Bulk=0μm TLP of Channel Length=0.35μm TLP of Channel Length=0.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Leakage of Channel Length=0.35μm Leakage of Channel Length=0.5μm
1E-10 1E-9 1E-8 1E-7 1E-6 1E-5
0 5 10 15 20 25 30
Spacing from Source to Bulk=2μm TLP of Channel Length=0.35μm TLP of Channel Length=0.5μm
Leakage (A)
Itlp (A)
Vtlp (V)
Leakage of Channel Length=0.35μm Leakage of Channel Length=0.5μm
(a) (b)
Fig. 3.40 NSCR : (a) The TLP I-V curves of different channel length with S_B spacing=0μm, (b) The TLP I-V curves of different channel length with S_B spacing=2μm, (c) The It2 value versus S_B spacing on different channel length.
CHAPTER 4
PROCESS MODIFICATION FOR
HIGH-VOLTAGE ESD PROTECTION DESIGN
4.1 The ESD Failure Mechanism of LD-NMOS
According to the chapter 2.2, the turn-on of the BJT and the avalanche breakdown of the N/N+ junction of the LD-NMOS result in the double snapback characteristic. During each snapback period, the voltage of the device will be decreased and the current of the device will be increased substantially. This phenomenon can cause current crowding in the drain area and raise the temperature to the silicon melting point to fuse the drain contact. So, the ESD failure mechanism of the LD-NMOS is due to the double snapback characteristic. If the snapback characteristic can be delayed or be diminished, the device can have longer and large ESD current can be discharged [41]. The turn-on of the BJT can be delayed or diminished by changing the base resistance. The avalanche breakdown of the N/N+ junction can be delayed and diminished by controlling the electric field peak not to approach the N/N+ junction. This chapter will introduce some reported HV devices with additional process layer to have better ESD performance that have been reported and discuss the ESD performance of the small device (total width < 5k μm), the large device (total width > 5k μm) with the PSB (P type Sub Body) layer in a 0.25μm 18V BCD process.
4.2 The High-Voltage BJT with ESD Implantation
The gate-grounded NMOS transistor (GGNMOS), diode strings and SCR with trigger circuit are used in traditional ESD protection. If there are only low-voltage devices available, the high-voltage and high-current characteristics of the lateral bipolar device can be adjusted by changing ESD implant dose and layout modification. The BJT does not require gate oxide and therefore does not need to follow gate oxide constraints. Fig. 4.1(a) shows the lateral bipolar device, the three terminals are separated by STI, the “ac” denotes the collector-to-STI
distance and the “dESD” denotes the ESD mask-to-STI distance [42]. During the ESD stresses on the collector, the device breaks down at the N+/P well junction where the ESD implant is located. Then, the bipolar will turn on and go into snapback state. In TCAD simulation, a hot spot develops at S2 location, which finally causes the device damage and the current path will change from S1 path to S2 path during high currents condition.
The breakdown voltage can be modified by tuning the concentration of the ESD implantation. With the increasing of the ESD implant boron dosage, the trigger voltage can be decreased and the holding voltage can be increased by increasing both the ac and dESD spacing.
Moreover, the turn-on resistance can be decreased by decreasing the “ac-dESD spacing” with fixed ac due to the entering electrons still flow through the high-ohmic diffusion to reach the collector contact, as shown in Fig. 4.1(b) [42]. The parasitic resistance of current path S2 is smaller than S1 due to the deeper current path. In the formula of resistance (R=ρL/A), bigger cross-sectional area causes the smaller resistance.
4.3 The Methods to Enhance ESD Performance in LD-NMOS
The ESD performance in typical LD-NMOS is very awful. Therefore, various LD-NMOS structures have been reported to improve the current capability without changing the breakdown voltage. The failure mechanism of LD-NMOS is attributed to current crowding by the snapback characteristic of parasitic BJT turn-on and the avalanche breakdown characteristic of the N/N+ junction as described in chapter 4.1. So, reduce the strong snapback effect of turned-on BJT or keep the parasitic BJT off are the methods to enhance the ESD performance of LD-NMOS, as described below.
4.3.1 No Turn-On Parasitic BJT by Drain and Gate Clamp Technique
The only practical method to allow the LD-NMOS conduct higher current without parasitic BJT turning on is to use various gate and drain clamp circuits [24]. Through this method, the channel heating effects can be minimum and the ESD level can be optimized by the more uniform turn-on of the LD-NMOS.
If the gate bias gets higher, the driving current will be saturated by the mobility degradation of the channel heating. For power devices, the effective thermal impedance is proportional to pulse width. The pulse width range of non-ESD condition is from tens of μs
to a few ms, whereas the ESD pulse duration is about 100ns. Therefore, the effective thermal impedance for ESD pulse is a fraction of the thermal impedance under normal operating conditions and the channel heating effect can be minimized to gain higher secondary breakdown current (It2). Fig. 4.2(a) compares the I-V measurement of LD-NMOS under ESD pulse and under normal operation. It can be observed that under ESD stress, the only limiting effects are the vertical and lateral fields [24].
To add the zener diodes to clamp drain voltage and gate voltage, respectively, as shown in Fig. 4.2(b) [24]. These clamp circuits are used to prevent the device entering bipolar breakdown. When the transient voltage at the pad exceeds the drain zener clamp voltage, the sufficient gate bias voltage will trigger the LDMOS. When more current flows into the device, the gate potential rises and the LD-NMOS starts to conduct. If a larger gate clamp is used, the It2 value and the HBM level of the LD-NMOS can be increased, but the gate oxide reliability is another important issue needed to concern. The It2 value is determined by the gate zener clamp breakdown voltage or the leakage current of the LD-NMOS.
On the other hand, the drain clamp can increase the power dissipation, so the smaller drain clamp can enhance ESD performance. For larger device total width with multiple fingers, the device can be turned on more uniformly by adding the resistor between the gate and source terminal, then the ESD level can also be enhanced. In summary, the optimized ESD performance of the LD-NMOS can be obtained by using the adequate gate clamp, smaller drain clamp with satisfied operating voltage range, larger device total width to discharge ESD currents and the added resistor between the gate and source sides to enhance the uniform turn-on characteristic..
4.3.2 No-Snapback Characteristic by Adaptive Layer Technique
Because the snapback mechanism is caused by the positive feedback between the parasitic BJT turn-on in the source side and the avalanche breakdown of the N/N+ junction in the drain side. The no-snapback LD-NMOS can be implemented by adding the adaptive layer beneath the drain and source side, respectively. Fig. 4.3(a) shows the added adaptive layer in the LD-NMOS to suppress the snapback effect [43]-[44].
During ESD stress condition and after the BJT turns on, the drain N/N+ junction is reverse biased by the voltage (V = Rd x Id), where the Rd denotes the drain resistance and the Id denotes the drain current. In order to prevent the snapback effect happening, it is necessary to reduce the V below the N/N+ junction avalanche breakdown voltage. The method is to
reduce the Rd by inserting a N-type high doping concentration drain adaptive layer beneath the N+ diffusion. Through this method, the more Id is needed to cause junction breakdown.
Therefore the trigger current of N/N+ junction should be increased. Fig. 4.3(b) shows the device with different N-type doping concentration adaptive layer, the bend 1 is the turn-on point of the BJT and the bend 2 is the drain avalanche point [43]-[44]. With increasing the doping concentration, the bend 2 moves upward and the snapback effect can be reduced effectively.
On the other hand, to avoid the BJT in the source side turn-on is another issue. The BJT can be turned on easily by increasing base resistance. So, to reduce the base resistance can prevent the BJT turning on. The added adaptive layer in the source side is a P-type high doping concentration layer, it can reduce the base resistance substantially. Through this method, the more current is needed to turn on the BJT. With increasing the doping concentration of the body adaptive layer, the base resistance can be reduced and the bend 1 moves to higher current, as shown in Fig. 4.3(c) [43]-[44]. In addition, curve A of Fig. 4.3(c) shows the base resistance is converged.
The adaptive layer in both sides can suppress the snapback effect by adjusting on/off condition of the BJT turns in the source side and N/N+ junction avalanche breakdown in the drain side. Therefore, the failure mechanisms can be avoided and the ESD performance of LD-NMOS can be enhanced.
4.4 Experimental Results and Failure Analysis
The additional layer in this experiment is similar to the adaptive layer as above. This layer is named PSB (P type Sub Body) layer and it is also a high doping P type layer. The original concept to design this layer is to decrease the base resistance of the parasitic BJT and increase the holding voltage after snapback condition. On the other hand, to decrease the base resistance of the parasitic BJT can also enhance the turn-on uniformity. By appropriate modifying the doping concentration, the snapback characteristic of the parasitic BJT can be avoided in 0.25μm 18V BCD process. There are small device (total width < 5k μm) and large device (total width > 5k μm) with and without the PSB layer had been experimented and discussed the influence on ESD performance. In addition, the failure analysis is presented in large device (total width = 20k and 80k μm) with the guardring floating and grounded.
4.4.1 The Small Device with and without PSB Layer
To investigate the influence on ESD performance, the small device (total width = 200μm and one finger width = 50μm) with and without the PSB layer had been experimented, as shown in Fig. 4.4. The N+ edge to contact spacing of the drain side is fixed at 10μm to enhance the ESD performance and to avoid the device destroying so early. The modified parameters are the source to bulk spacing of the source side named S_B and the channel length.
Table 4.1 shows the various ESD data when the small LD-NMOS device without the PSB layer. To find out the ESD performance of device without the PSB layer, with increasing the channel length from 15μm to 30μm, the holding voltage can be increased from 22V to 26V. With increasing the channel length from 15μm to 30μm and S_B spacing from 0 to
Table 4.1 shows the various ESD data when the small LD-NMOS device without the PSB layer. To find out the ESD performance of device without the PSB layer, with increasing the channel length from 15μm to 30μm, the holding voltage can be increased from 22V to 26V. With increasing the channel length from 15μm to 30μm and S_B spacing from 0 to