The Small Device with and without PSB Layer

CHAPTER 4 PROCESS MODIFICATION FOR HIGH-VOLTAGE

4.4 Experimental Results and Failure Analysis

4.4.1 The Small Device with and without PSB Layer

To investigate the influence on ESD performance, the small device (total width = 200μm and one finger width = 50μm) with and without the PSB layer had been experimented, as shown in Fig. 4.4. The N+ edge to contact spacing of the drain side is fixed at 10μm to enhance the ESD performance and to avoid the device destroying so early. The modified parameters are the source to bulk spacing of the source side named S_B and the channel length.

Table 4.1 shows the various ESD data when the small LD-NMOS device without the PSB layer. To find out the ESD performance of device without the PSB layer, with increasing the channel length from 15μm to 30μm, the holding voltage can be increased from 22V to 26V. With increasing the channel length from 15μm to 30μm and S_B spacing from 0 to 10μm, the trigger voltage will be increased a little, the holding voltage and the It2 value will be increased about 3V and 2A when the S_B spacing is 0μm, respectively, as shown in Figs.

4.5(a) and 4.5(b). Therefore, the large channel length can enhance the holding voltage and It2 value substantially.

Table 4.2 shows the various ESD data when the small LD-NMOS device with the PSB layer. To find out the ESD performance of device with the PSB layer, with increasing the channel length from 15μm to 30μm, the holding voltage can be increased from 23V to 27V.

With increasing the channel length from 15μm to 30μm and S_B spacing from 0 to 10μm, the trigger voltage and the holding voltage can be increased from 35V to 43V and 27V to 35V when the S_B spacing is 0μm, respectively, as shown in Figs. 4.6(a) and 4.6(b). The It2 can be also increased by the increasing channel length.

Comparing with the Table 4.1 and 4.2, the PSB layer can enhance the trigger voltage and holding voltage substantially when the S_B spacing is 0μm, but the It2 value may be decreased a little due to the larger holding voltage

4.4.2 The Large Device with and without PSB Layer

The large device of LD-NMOS had been fabricated by minimum design rule and had been designed as ESD protection device and output current driver, simultaneously. The cross-sectional and layout diagram of large device with the PSB layer and guardring are shown in Figs. 4.7(a) and 4.7(b). Figs. 4.8(a) and 4.8(b) show the TLP I-V curve of large device (total width = 5k, 20k and 80k μm and guardring floating) without and with PSB layer,

respectively. Figs. 4.9(a) and 4.9(b) show the TLP I-V curve of large device (total width = 5k, 20k and 80k μm and guardring grounded) without and with PSB layer, respectively. The It2 value and the turn-on uniformity can be further increased by the PSB layer substantially.

Comparing the leakage current of Fig. 4.8(a) and Fig. 4.8(b), the device with the PSB layer can decrease the leakage current. Therefore, by adding the PSB layer, the LD-NMOS with no snapback characteristic can be implemented successfully.

4.4.3 The Failure Analysis of Large Device

Figs. 4.10(a) and 4.10(b) show the SEM images of the large LD-NMOS device with PSB layer (total width = 80K) with guardring floating and with guardring grounded, respectively. The failure locates at center finger while the guarding is floating and the failure locates at corner while the guarding is grounded. Figs. 4.11(a) and 4.11(b) show the SEM images of the large LD-NMOS device with PSB layer (total width = 20k) with guardring floating and with guardring grounded, respectively. The failure location of the device total width = 20k is similar to the device total width = 80k. Therefore, the guardring grounded type will conduct the ESD current to the corner and damage the corner fingers. The guardring floating type can have better ESD performance than the guardring grounded type..

4.5 Summary

The failure mechanism of LD-NMOS is the snapback characteristic. To suppress the parasitic BJT turn-on of source side and the N/N+ junction avalanche breakdown of drain side can both improve the turn-on uniformity and ESD performance. The PSB layer can increase the trigger voltage and holding voltage in small LD-NMOS device, but decrease the It2 value a little while the source and bulk regions are butted. Moreover, The PSB layer can increase the It2 value in large LD-NMOS device substantially and improve the leakage current while the guardring is floating.

Table 4.1

The ESD characteristics of the small LD-NMOS device without the PSB layer.

Table 4.2

The ESD characteristics of the small LD-NMOS device with the PSB layer.

(a) (b)

Fig. 4.1 (a) The cross-sectional of lateral NPN device with ESD implant, (b) Measured I-V curve for different dESD but fixed ac, with increasing the ac-dESD spacing, the current will flow through the collector diffusion and the resistance will increased.

The ac-dESD spacing is curve A > curve B > curve C.

(a) (b)

Fig. 4.2 (a) The I-V curve of normal operation and ESD stress by curve tracer, (b) The drain and gate clamp structure with a gate-grounded resistor.

(a)

(b) (c)

Fig. 4.3 (a) The adaptive layer structure of LD-MOS on both drain and source sides, (b) The influence on snapback effect by drain adaptive layer, (c) The influence on snapback effect by body adaptive layer.

Fig. 4.4 The cross-sectional view of small LD-MOS device with the PSB layer.

1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5

0 5 10 15 20 25 30 35 40 45

Fig. 4.5 (a) The TLP I-V curves of different S_B spacing in small LD-NMOS device without PSB layer (channel length = 15μm), (b) The TLP I-V curves of different S_B spacing in small LD-NMOS device without PSB layer (channel length = 30μm).

1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5

0 5 10 15 20 25 30 35 40 45

Fig. 4.6 (a) The TLP I-V curves of different S_B spacing in small LD-NMOS device with PSB layer (channel length = 15μm), (b) The TLP I-V curves of different S_B spacing in small LD-NMOS device with PSB layer (channel length = 30μm).

(a)

(b)

Fig. 4.7 (a) The cross-sectional view of large LD-MOS device with the PSB layer and guarding, (b) The layout diagram of the large device.

1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5

5 10 15 20 25 30 35 40 45 50

Fig. 4.8 (a) The TLP I-V curves of large LD-NMOS device without PSB layer and guardring floating, (b) The TLP I-V curves of large LD-NMOS device with PSB layer and guardring floating.

1E-11 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5

5 10 15 20 25 30 35 40 45 50

Fig. 4.9 (a) The TLP I-V curves of large LD-NMOS device without PSB layer and guardring grounded, (b) The TLP I-V curves of large LD-NMOS device with PSB layer and guardring grounded.

(a)

(b)

Fig. 4.10 (a) The SEM image of large LD-NMOS device (total width = 80k μm) with PSB layer and guarding floating, (b) The SEM image of large LD-NMOS device (total width = 80k μm) with PSB layer and guarding grounded.

(a)

(b)

Fig. 4.11 (a) The SEM image of large LD-NMOS device (total width = 20k μm) with PSB layer and guarding floating, (b) The SEM image of large LD-NMOS device (total width = 20k μm) with PSB layer and guarding grounded.

CHAPTER 5 CONCLUSIONS AND FUTURE WORKS

5.1 Main Results of This Thesis

In this thesis, the various ESD protection devices have been developed for BCD process with high ESD robustness. Each of the ESD protection devices has been successfully verified in the testchips.

In chapter 2, the turn-on mechanism and double-snapback characteristic of HV LD-NMOS and HV NMOS has been discussed. The turn-on mechanism of LD-NMOS is composed of the turn-on parasitic BJT and the N/N+ junction avalanche breakdown. After the BJT turns on, the electric field peak will move toward the drain side and cause the N/N+

junction breakdown. The feedback between the BJT and N/N+ junction will improve the snapback characteristic. The double-snapback characteristic of the HV NMOS depends on the device structure. If the current path won’t change after the device go into first snapback, the device will not have the second snapback chance.

In chapter 3, there are several splits on HV LD-NMOS, HV LD-PMOS, HV NFOD, HV NSCR and HV dual-direction SCR. The dominant factor to improve the ESD performance of LD-NMOS, NFOD and NSCR is the N+ edge to contact spacing of the drain side.

Unfortunately, the ESD performance of the LD-PMOS in several testkeys is very insufficient to pass the standard ESD specification. In dual-direction SCR, the holding voltage can be modified to over than the operation voltage and to avoid the latchup effect. The It2 value, HBM and MM level of the dual-direction SCR are about 4A, 6KV and 300V, respectively.

In chapter 4, the PSB layer is added to small device and large device of LD-NMOS to investigate the ESD performance. The holding and trigger voltage of small LD-NMOS device can be increased by the PSB layer substantially while the source and bulk regions are butted.

The PSB layer can decrease the base resistance of the parasitic BJT and improve the turn-on uniformity of the large LD-NMOS device with the minimum rule. Therefore, the It2 value of the large LD-NMOS device with the PSB layer can be increased.

5.2 Future Works

The trigger voltage of the dual-direction SCR is relative high to protect the internal circuit. The extra trigger element is added to reduce the trigger voltage, as shown in Fig. 5.1 [45]. By using the spacing between the HV N Wells, the additional layout area is not needed.

Through this trigger method, the dual-direction SCR will have the same trigger voltage on both sides.

The difference holding voltage of TLP and 370A has been found in dual-direction SCR.

Even though the holding voltage of TLP is more than the operation voltage, the holding voltage measured by 370A will be only 2V, as shown in Figs 5.2 and 5.3(a) ~ 5.3(d). To investigate the reason and try to improve the holding voltage in DC domain is the next research topic. In addition, the holding voltage and trigger voltage of DC I-V curve in LD-NMOS are also different from TLP I-V curve, as shown in Figs 5.4(a) ~ 5.4(b), but the holding voltage and trigger voltage of DC I-V curve in LD-PMOS are the same as TLP I-V curve, as shown in Figs 5.4(c) ~ 5.4(d).

Fig. 5.1 The added trigger element to trigger the dual-direction SCR on both sides.

Fig. 5.2 The dual-direction SCR measured by TLP and 370A.

1E-10 1E-9 1E-8 1E-7 1E-6 1E-5

0 5 10 15 20 25 30 35 40 45 50 GND, (b) The TLP I-V curve of dual-direction SCR with node 2 pulse in and node 1 GND, (c) The DC I-V curve of dual-direction SCR with node 1 pulse in and node 2 GND, (d) The DC I-V curve of dual-direction SCR with node 2 pulse in and node 1 GND.

1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 I-V curve of LD-NMOS with N_C=4μm, H_N=18 μm, (c) The TLP I-V curve of LD-PMOS with W=400μm, (d) The DC I-V curve of LD-PMOS with W=400μm.

REFERENCES

[1] ESD Association Standard Test Method ESD STM5.1-2001, for Electrostatic Discharge Sensitivity Testing – Human Body Model (HBM) – Component Level, 2001.

[2] C. Duvvury, R. Rountree, and O. Adams, “Internal chip ESD phenomena beyond the protection circuit,” IEEE Trans. on Electron Devices, vol. 35, no. 12, pp. 2133–2139, Dec. 1988.

[3] V. Puvvada and C. Duvvury, “A simulation study of HBM failure in an internal clock buffer and the design issue for efficient power pin protection strategy,” in Proc.

EOS/ESD Symp., 1998, pp. 104–110.

[4] A. Amerasekera and C. Duvvury, ESD in Silicon Integrated Circuits, 2^nd Edition, John Wiley & Sons, Ltd., England, 2002.

[5] S. Voldman, ESD Physics and Devices, John Wiley & Sons, Ltd., England, 2004.

[6] M.-D. Ker, “Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI,” IEEE Trans. Electron Devices, vol. 46, no. 1, pp. 173–183, Jan. 1999.

[7] W. Morris, “Latchup in CMOS,” in Proc. IEEE Int. Reliability Physics Symp., 2003, pp. 76–84.

[8] M.-D. Ker and W.-Y. Lo, “Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology,” IEEE Trans.

Semicond. Manufact., vol. 16, no. 2 pp. 319–334, May 2003.

[9] S.-F. Hsu, M.-D. Ker, G.-L. Lin and Y.-N. Jou, “Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process,” in Proc. IEEE Int. Reliability Physics Symp., 2006, pp. 140–144.

[10] T. J. Maloney and N. Khurana, “Transmission line pulsing techniques for circuit modeling of ESD phenomena,” in Proc. EOS/ESD Symp., 1985, pp. 49–54.

[11] J.E. Barth, K. Verhaege, L. G. Henry and J. Richner, “ TLP calibration, correlation, standards, and new techniques,” IEEE Trans. Electronics Packaging manufact., vol.

24, no. 2, pp. 99–108, Apr. 2001.

[12] M.-D. Ker and K.-H. Lin, “The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs,” IEEE J. Solid-State Circuits, vol. 40, no. 8, pp. 1751–1759, Aug.

2005.

[13] M.-D. Ker and S.-H. Chen, “ Implementation of initial-on ESD protection design with PMOS-triggered SCR devices in deep-submicron CMOS technology,” IEEE J.

Solid-State Circuits, vol. 42, no. 5, pp. 1158–1168, May 2007.

[14] A. Wang and C.-H. Tsay, “ An on-chip ESD protection circuit with low trigger voltage in BiCMOS technology,” IEEE J. Solid-State Circuits, vol. 36, no. 1, pp. 40–45, Jan.

2001.

[15] M.-D. Ker, C.-Y. Wu, T. Cheng, M. Wu, and T.-L. Yu, “On-chip ESD protection using capacitor-couple technique in 0.5-mm 3-V CMOS technology,” in Proc. IEEE Int.

ASIC Conference and Exhibit, pp. 135–138, Sep. 1995.

[16] T.-Y. Chen and M.-D. Ker, “Investigation of the gate-driven effect and substrate-triggered effect on ESD robustness of CMOS devices,” IEEE Trans. Devices and Materials Reliability, vol. 1, no. 4, pp. 190–203, Dec. 2002.

[17] M.-D. Ker and K.-C. Hsu, “SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes,” IEEE Trans.

Devices and Materials Reliability, vol. 3, no. 3, pp. 58–68, Sep. 2003.

[18] M.-D. Ker and K.-C. Hsu, “Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-µm CMOS integrated circuits,” in Proc. IEEE Int. Reliability Physics Symp., pp. 381–386, Apr. 2004.

[19] K.-C. Hsu and M.-D. Ker, “Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-blocking mask,” in Proc. IEEE Int. Symposium on Quality Electronic Design, pp. 503–506, Mar.

2006.

[20] M.-D. Ker, J.-H. Chen and K.-C. Hsu, “Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices,” in Proc. IEEE Int.

Symposium on VLSI Technology, Systems, and Applications, pp. 17–18, Apr. 2005.

[21] M. P. J. Mergens, M. T. Mayerhofer, J. A. Willemen, M. Stecher, “ESD protection considerations in advanced high-voltage technologies for automotive,” in Proc.

EOS/ESD Symp., 2006, pp. 69–76.

[22] H. Ballan and M. Declercq, High Voltage Devices and Circuits in Standard CMOS Technologies, Kluwer Academic, 1998.

[23] M. P. J. Mergens, W. Wilkening, S. Mettler, H. Wolf, A. Stricker, and W. Fichtner,

“Analysis of lateral DMOS power devices under ESD stress conditions,” IEEE Trans.

Electron Devices, vol. 47, no. 11, pp. 2128–2137, Nov. 2000.

[24] C. Duvvury, F. Carvajal, C. Jones, and D. Briggs, “Lateral DMOS design for ESD

robustness,” in IEDM Tech. Dig., 1997, pp. 375–378.

[25] P. Moens, K. Reynders, S. Bychikhin, D. Pogany and M. Zubeidat, “Optimization of integrated vertical DMOS transistors for ESD robustness,” Proceedings of Int.

Symposium on Power Semiconductor Devices and ICs, pp. 221–224, 2004.

[26] A. W. Ludikhuize, “A review of RESURF technology,” ISPSD, pp. 11–18, 2000.

[27] V. Parthasarathy, V. Khemka, R. Zhu, J. Whitfield, A. Bose, and R. Ida, “A double RESURF LDMOS with drain profile engineering for improved ESD robustness,”

IEEE Electron Device Lett., vol. 23, no. 4, pp. 212–214, Apr. 2002.

[28] A. W. Ludikhuize, “Kirk effect limitations in high-voltage ICs,” Proceedings on Int.

Symposium on Power Semiconductor Devices and ICs, pp. 249–252, May 1994.

[29] U. Glaser, J. Schneider, M. Streibl, K. Esmark, S. Druen, H. Gossner, W. Fichtner,

“Base pushout driven snapback in parasitic bipolar devices between different power domains,” IRPS, pp. 387–392, 2004.

[30] M.-D. Ker and K.-H. Lin, “Double snapback characteristics in high voltage nMOFETs and the impact to on-chip ESD protection design,” IEEE Electron Device Lett., vol. 25, no. 9, pp. 640–642, Sep. 2004.

[31] V. A. Vashchenko, A. Concannon, M. ter Beek and P. Hopper, “High performance SCRs for on-chip ESD protection in high voltage BCD processes,” ISPSD, pp.

261–264, 2003.

[32] T. Dyer, J. McGinty, A. Strachan and C. Bulucea, “Monolithic integration of trench vertical DMOS (VDMOS) power transistors into a BCD process,” Proceedings of Int.

Symposium on Power Semiconductor Devices and ICs, pp. 1–4, 2005.

[33] B. H. Krabbenborg, J. A. Van der Pol, “Robustness of LDMOS power transistors in SOI-BCD processes and derivation of design rules using thermal simulation,”

Proceedings of Int. Symposium on Power Semiconductor Devices and ICs, pp.

157–160, 2001.

[34] P. Wessels, M. Swanenberg, “Advanced 100V, 0.13 gm BCD process for next generation automotive applications,” Proceedings of Int. Symposium on Power Semiconductor Devices and ICs, pp. 1–4, 2006.

[35] M. Blaho, L. Zullino, H. Wolf, R. Stella, A. Andreini, H. A. Gieser, D. Pogany and E.

Gornik, “Internal behavior of BCD ESD protection devices under TLP and very-fast TLP stress,” IEEE Trans. Devices and Materials Reliability, vol. 4, no. 3, pp. 535–541, Sep. 2004.

[36] V. D. Heyn, G. Groeseneken, B. Keppens, M. Natarajan, L. Vacaresse and G. Gallopyn,

“Design and analysis of new protection structures for smart power technology with controlled trigger and holding voltage,” IEEE Int. Reliability Physics Symp., 2001, pp.

253–257.

[37] W.-J. Chang, M.-D. Ker, T.-H. Lai, T.-H. Tang, and K.-C. Su, “ESD robustness of 40-V CMOS devices with/without drift implant,” in Final Report of IEEE Integrated Reliability Workshop, 2006, pp. 167–170.

[38] W.-J. Chang and M.-D. Ker, “The impact of drift implant and layout parameters on ESD robustness for on-chip ESD protection devices in 40-V CMOS technology,”

IEEE Trans. Device Mater. Reliab., in press, 2007.

[39] V. A. Vashchenko, A. Concannon, M. ter Beek and P. Hopper, “Stacked BSCR ESD protection for 250V tolerant circuits,” Proceedings of Int. Symposium on Power Semiconductor Devices and ICs, pp. 225–228, 2004.

[40] J.-H. Lee, J.-R. Shih, C.-S, Tang, K.-C. Liu, Y.-H. Wu, R.-Y. Shiue, T.-C. Ong, Y.-K.

Peng, and J.-T. Yue, “Novel ESD protection structure with embedded SCR LDMOS for smart power technology,” in Proc. IEEE Int. Reliability Physics Symp., 2002, pp.

156–161.

[41] M.-D. Ker, J.-J. Peng, and H.-C. Jiang, “Failure anlaysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution,” IPFA, pp. 84–89, 2002.

[42] J. Schneider, M. Wendel and K. Esmark, “ Tunable bipolar transistor for ESD protection of HV CMOS technology,” in Proc. EOS/ESD Symp., 2006, pp. 214–221.

[43] K. Kawamoto, S. Takahashi, S. Fujino and I. Shirakawa, “ A no-snapback LDMOSFET with automotive ESD endurance,” IEEE Electron Devices , vol. 49, no.

11, pp. 2047–2053, Nov. 2002.

[44] K. Kawamoto and S. Takahashi, “An advanced no-snapback LDMOSFET with optimized breakdown characteristics of drain n-n+ diodes,” IEEE Electron Devices , vol. 51, no. 9, pp. 1432–1440, Sep. 2004.

[45] M.-D. Ker and K.-C. Hsu, “Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits,” IEEE Trans. Devices and Materials Reliability, vol. 5, no. 2, pp. 235–249, Jun. 2005.

VITA

姓名：黃曄仁 (Yeh-Jen Huang) 性別：男

出生日期：民國 69 年 10 月 25 日出生地：台北市

住址：台北市大安區大學里 6 鄰溫州街 48 巷 14 號 3 樓學歷：

台北市私立延平中學 (84 年 9 月 - 87 年 6 月) 長庚大學電機工程學系畢業 (88 年 9 月 - 92 年 6 月) 國立交通大學電機學院微電子奈米產業研發碩士班

(95 年 2 月入學)

論文名稱：高壓製程之靜電放電防護元件設計

High-Voltage ESD Protection Devices Design in BCD Process

在文檔中高壓製程之靜電放電防護元件設計 (頁 103-124)