The High-Voltage ESD Protection Devices

There are several high-voltage ESD protection devices that have been developed in different two processes. In the high-voltage (HV) process, a low doping layer is added in the drain and source sides named DDD-structure to increase the breakdown voltage. The ESD robustness of the asymmetric structure is better than symmetric structure in the HV process as described in chapter 1. The asymmetric structure means the DDD layer is added in the drain side. In the Bipolar-CMOS-DMOS (BCD) process [31]-[35], there are BJT, CMOS and DMOS to use in the high-voltage operation. In addition, the diode with high reverse breakdown voltage and high-voltage SCR are also available in these two processes.

3.1.1 The High-Voltage Bipolar Junction Transistor with Controllable Trigger and Holding Voltage

To provide effective whole-chip ESD protection, on-chip ESD protection devices are added in different parts of ICs. The required ESD specification of breakdown voltage, trigger

voltage and holding voltage in each part are different. So, this requires devices with high electrical flexibility to meet the different ESD specifications.

In the BCD process, the high-voltage bipolar junction transistor (HV BJT) with controllable trigger and holding voltage has been developed by well-adjusted layout parameter, as shown in Fig. 3.1 [36]. The holding voltage can be controlled by changing the

“d” spacing (the clearance between P Body edge and N+ emitter); the trigger voltage can be controlled by changing the “t” spacing (the distance between P Body and N Well), respectively.

In order to understand the physical mechanism of the influence on changing each layout parameter, to investigate the current flow, electrical field and the impact ionization in the device is necessary. Due to the junction breakdown is happened at P Body/N- junction, with the increasing of the “t” spacing, the breakdown and the trigger voltage can be both increased as shown in Fig. 3.2(a) [36].

Moreover, there are two current paths can trigger the HV BJT device, a lateral one and a vertical one via the N+ Buried Layer (NBL). To find out the effect on different “d” spacing, the TLP I-V curve shows the current path can be changed from lateral bipolar path to vertical bipolar path, as shown in Fig. 3.2(b) [36]. If the applied voltage exceeds the breakdown voltage of P Body/N- junction in small “d” spacing, the device enters the first snapback state and the impact ionization happens on the surface of P Body/N- junction. When the current further increases, the Kirk effect happens and push the maximum electric field peak from the P Body/N- junction to the collector N Well/N+ junction. In this higher doped region (N Well/N+), due to the higher multiplication rate, a lower electric field can reach the same avalanche current to bring the device into second snapback state resulting in the low holding voltage.

With the larger “d” spacing, the device behavior is completely different due to the carrier recombination of the electron. The larger base width can let more electron current be recombined by the base hole current. Therefore, the bipolar current gain (β) degrades with increasing the base width. By the decreased current gain of the lateral NPN BJT, the lateral NPN will be turned off. The NBL is a high doping N-type layer, which constructs a low impedance current path to shunt the ESD current through the vertical NPN BJT. The impact ionization and the base-widening effect will reach the NBL layer, and then the second snapback occurs. Due to the doping profile of NBL is lower than the N+/N Well region, the multiplication rate is also lower than the N Well/N+ region and the holding voltage may be much higher than the lateral NPN.

In summary, by tuning the “t” spacing, the breakdown and trigger voltage can be increased; by tuning the “d” spacing, the turn-on type of the bipolar junction transistor and the holding voltage can be selected.

3.1.2 The High-Voltage NMOS with Embedded SCR Structure (NSCR) The HV NMOS has poor ESD robustness compared to LV NMOS. To increase the ESD robustness, the conventional method is to use the large device structure, but it suffers non-uniform turn-on issue. This non-uniform turn-on phenomenon in HV NMOS is caused by the strong snapback characteristic during ESD stress. The gate-coupled technique can alleviate this issue, but the added gate-grounded resistor sacrifices a large layout area.

In order to increase the breakdown voltage, the N Grade region below the N+ diffusion [37]-[38] and the field oxide between the drain side and the polygate can be used. The P Field under the bulk is for device isolation. The higher breakdown voltage causes higher electrical field and more interface trap in the field oxide. An optional low doped N-type layer named N Drift implant below the field oxide can minimize the peak electric field and let the device avoid the hot-carrier effect, but it also cause a longer current path from drain to source, as shown in Fig. 3.3(a) [38]. Due to the drift layer and the grade region are of the same type, the current will flow into the drift layer first and then to the source side. This current flow causes current-crowding in the N Drift region. On the contrary, the device without the drift layer has more uniform current distribution from drain to source. With the increasing of the “d”

spacing, the trigger voltage of device with drift implant will be increased by the longer current path. The trigger voltage of device without Drift implant is kept the same because the trigger voltage is determined by the N Grade/ HV P Well junction. Therefore, the HV NMOS without the drift implant can switch quickly and have better It2 level. In addition, the HV PMOS also has the same effect.

The HV N-type SCR (HV NSCR) is to insert a P+ diffusion in the drain side of the HV NMOS to form a SCR path, as shown in Fig. 3.3(b) [38]. The HV NSCR is a NMOS triggered SCR, due to the trigger voltage of SCR is always higher than NMOS, and the NMOS will be triggered first during ESD stress. Then, the SCR will be triggered and snapback to its low holding voltage and high It2 characteristic. In fact, a part of current can flow from P+ diffusion to HV P Well to trigger on the parasitic vertical PNP BJT earlier and the turn-on parasitic PNP BJT can also provide current to trigger the other parasitic NPN BJT.

To compare with the trigger voltage of HV NMOS and HV NSCR, the trigger voltage of HV

NSCR is smaller than the HV NMOS. With the increasing of “d” spacing, the trigger voltage and the holding voltage of HV NSCR with N Drift implant will be increased. So, the It2 value of HV NSCR without the N Drift implant is higher than the HV NSCR with the N Drift implant.

3.1.3 The High-Voltage BJT with Embedded SCR Structure (B-SCR)

The bipolar-triggered SCR (B-SCR) device consists of a added P+ diffusion in the collector of the NPN transistor, this device can conduct much higher current than NPN transistor, as shown in Fig. 3.4 [39]. Both the trigger voltage and the ESD protection capability of NPN-triggered B-SCR depend on the P+ spacing. Under small P+ spacing about 5μm, the trigger voltage is similar to that of NPN BJT. With increasing the P+ spacing from 5μm to 10μm, the trigger voltage can be decreased substantially, as shown in Fig. 3.5 [39].

On the other hand, the larger P+ spacing decreases the It2 value.