Because of the total power dissipation of one certain device is fixed at the product of the It2 and holding voltage (power = It2 x Vhold ), the SCR device can sustain a much higher It2 than other devices in a smaller layout due to its low holding voltage characteristic. So, it had been used to protect the internal circuits against ESD damage for a long time. But, the trigger voltage of the HV SCR is too large to protect the internal circuit. Therefore, how to decrease the trigger voltage in HV operation is another issue.
There are several SCR-based structure had been verified. The application method is to integrate two kinds of devices into one device by using the low holding voltage characteristic of SCR and the low trigger voltage of other devices. The integration method can be one device with parasitic SCR path or SCR device with parasitic trigger device.
1.3.1 The Initial-On Parasitic Structure Technique
In the past, the traditional ESD protection devices are use the parasitic BJT to turn on the GGNMOS and use the avalanche breakdown to turn on the SCR. But, with the device scaling, the internal circuits are fabricated on thinner oxide, the traditional ESD protection design cannot be able to effectively protect it. The initial-on technique means the ESD device is turned on when the IC is floating without any power bias, when the I/O pad is zapped by ESD, the ESD device is already standby to discharge the ESD current from pad to ground as shown in Figs. 1.9(a) ~ 1.9(e).
The design window of the ESD protection device is between the power supply (VDD) and the internal circuit’s gate oxide breakdown voltage as shown in Fig. 1.10. The holding voltage should be higher than the VDD to avoid the latchup effect and the trigger voltage should be lower than the gate oxide breakdown voltage to discharge the ESD current efficiently. One device with lower trigger voltage by initial-on technique is verified by the SCR device with PMOS-triggered and RC-based ESD transient detection circuit as shown in Fig. 1.11 [13]. The source and drain terminals of the PMOS transistor are connected to the additional N+ diffusion and P+ diffusion of the SCR structure. The additional N+ and P+
diffusions are used to trigger the N Well and P Substrate. The gate terminal of the parasitic PMOS is controlled by the RC-based ESD transient detection circuit.
Under PS-mode stress, the gate voltage of embedded PMOS is initially kept at zero in the power-rail ESD clamp circuit. The PMOS will turn on by the zero bias and conduct the ESD current from the N Well and inject into P Substrate of the SCR device. With these two trigger nodes, the SCR can be launched quickly. The initial-on PMOS transistor provides another path to make the voltage bias and induce base current between the emitter and base in the two BJTs to turn on the SCR device as shown in Fig. 1.12.
Due to the holding voltage, turn-on resistance and ESD robustness of SCR are influenced by its anode-to-cathode spacing, the layout structure can be changed to merge the n trigger node into the source terminal of PMOS transistor as shown in Fig. 1.13. Through this method, the trigger voltage, holding voltage can be reduced and the It2 will be increased.
1.3.2 The Dual-Direction SCR with Extra Trigger Circuit
Traditional SCR device provides only one direction ESD protection path. The dual-direction SCR device can protect each I/O pad against ESD stress in the PS-mode,
PD-mode, NS-mode and ND-mode [14]. This dual-direction SCR device is composed of a symmetrical five-layers NPNPN structure with one lateral PNP (Q1) and two vertical NPN (Q2 and Q3), as shown in Fig. 1.14(a). The extra trigger circuit comprises two pairs of Zener diodes (D1~D4) with back-to-back connection, as shown in Fig. 1.14(b). When a positive ESD pulse is stress at the anode of dual-direction SCR and its cathode is relatively grounded, the Zener diode D1 will be reverse breakdown and let the ESD current to trigger on the Q3 and Q1 transistor. The positive ESD current can be discharged through the current path1 and the negative ESD current through the current path2. The TLP I-V curve of dual-direction SCR is shown in Fig. 1.14(c). The dual-direction SCR provides low holding voltage and low impedance path to discharge the huge ESD current under every stress mode.
Although the SCR device is more area efficiency than other ESD protection devices. To improve the area efficiency in SCR device is an important challenge of manufacture. The layout structure divide into three kinds of square-shaped cells, named a corner cell, a center cell and an edge cell, respectively. As their names imply, they disposed in the corner location, center location and edge location. Figs. 1.15(a) ~ 1.15(g) shows three kinds of cells, each cell provides current flow either to or from P+ region. The center cell can discharge in four directions; the edge cell can discharge in two directions; the corner cell can discharge in one direction. Compared with traditional structure, the cell based structure can improve the current capability substantially.
1.3.3 The Gate-Coupled Technique
Except the SCR device provides good ESD robustness. The GGNMOS and GDPMOS are also used in ESD protection devices. Generally, according to the lower β gain of GDPMOS, the GDPMOS will have very unapparent snapback characteristic than the GGNMOS as shown in Figs. 1.1(b) and 1.1(c). Due to the snapback mechanism, the multiple finger type layout of GGNMOS will suffer the non-uniform turn on issue. Once the one of the multiple fingers turns on, the current will conduct through this path soon, while the other fingers are not turn on yet. The more current flow through the finger, the more heat generates.
It may cause the device failure on the most heat accumulation location as shown in Figs.
1.16(a) and 1.16(b).
Due to the snapback mechanism, the GGNMOS have lower holding voltage than the GDPMOS and the GGNMOS have higher It2 than the GDPMOS. The symbol of the ESD robustness is the It2 value, so the GGNMOS is preferred to be the ESD protection device. If
the non-uniform turn on effect can be delayed or decreased, the ESD level must be increased.
To improve the turn on uniformity, the gate-coupled and substrate-triggered designs have been reported.
The gate-coupled technique is used to lower the trigger voltage and to ensure uniform ESD current distribution [15]-[16]. The couple capacitor can be made by a poly layer under the wire-bonding metal pad or the parasitic capacitance without increasing extra layout area;
the resistor can also be made by poly layer, the product of the capacitor and the resistor is set to micron second order to distinguish the ESD stress as the previous RC-based circuit. Fig.
1.17 shows the gate-coupled structure, while the positive ESD stress occurs on the pad with relatively grounded VSS, the gate voltage of the GGNMOS is logic high. Thus, the ESD device can use the ESD voltage to trigger itself and not to work by the avalanche breakdown of the parasitic BJT. Furthermore, this coupled gate voltage can lowered the energy band of the channel surface and concentrate the ESD current at a smaller turn-on region in the channel surface of the GGNMOS. It also means there is a high electric field across the gate oxide. From the semiconductor physics, the gate-coupled technique can uniformly turn the channel current but it cannot enhance the turn-on uniformity of parasitic lateral BJT in the GGNMOS.
If the rising time of the ESD pulse be smaller, the trigger voltage could be also reduced.
This is why a faster rising time of pulse can trigger a transient latchup event during normal operation. In order to build a wide safety ESD margin, it is necessary to consider different rising time of pulse as shown in Fig. 1.18.
Moreover, in order to make sure the gate-coupled effect, there are three kinds of HV devices to be tested as the NPN BJT, NPN-SCR and the NSCR. The HV NPN BJT device is designed on the N+ Buried Layer (NBL) and there are two current paths as shown in Fig.
1.19(a) without using the sinker layer to gain more chipper cost. The sinker layer is a high doping optional layer to let the current flow deeper to prevent the hot-spots on the surface, non-uniform current flow and early failure. So, how to avoid such disadvantages on the HV NPN device without sinker layer is a cost down issue. The HV NPN-SCR device is to insert a P+ diffusion in the collector region of the NPN BJT, then there is a SCR path (P/N/P/N) be established, as shown in Fig. 1.19(b). The HV NSCR is to insert a P+ diffusion in the drain region of the NLDMOS and there is a SCR path from the drain to source, as shown in Fig.
1.19(c). In these test devices, the gate-coupled technique can reduce the trigger voltage more by larger gate-grounded resistor.
1.3.4 The Substrate-Triggered Technique
The substrate-triggered technique is to draw an electric connection from the P+ of substrate or N+ of N Well [17]. The current flows into the substrate or well can change the turn-on resistance of the ESD protection device during ESD stress. It means the substrate current can change the turn-on area or the turn-on path as parasitic lateral BJT in the NMOS to sustain higher ESD stress. Comparing to the gate-coupled, there is no gate bias to lower the energy bands on the surface channel of the substrate-triggered NMOS. But, the substrate bias can lower the energy bands in the substrate region and extend the current distribution. The turn-on behavior of the substrate-triggered GGNMOS device is the parasitic lateral BJT of all fingers can be uniformly turned on. With the increasing of the substrate current, the trigger voltage and the turn-on resistance of the device can be reduced as shown in Fig. 1.20.
The substrate-triggered circuit structure is also use the RC-based detection circuit to trigger the ESD protection device as shown in Fig. 1.21. During the positive ESD stress, the voltage of point A is logic low to trigger the PMOS (Mp1) and let the voltage of point B be logic high. Then, the NMOS (Mn2) is triggered and let the voltage of point C be logic low.
The turn on of the Mp1 can conduct the current from VDD to trigger the P+ diffusion of P Substrate; the turn on of the Mn2 can draw the current from the N+ diffusion of N Well to VSS and it means the N Well has been triggered.
These two types of substrate-triggered methods can be used in any device to reduce its trigger voltage. For example, the trigger voltage of HV SCR is too high to protect the internal circuit. Moreover, in order to avoid the latchup effect of HV SCR, the stacked-device technique can be adapted to raise the holding voltage, but the trigger voltage is also rise up.
The trigger node can be set on the N+ of N Well and P+ of P Substrate to trigger the parasitic NPN and PNP BJTs synchronously. Then, the HV SCR can be triggered on without junction avalanche breakdown mechanism.
When the trigger current is applied in p-trigger node, the NPN BJT in the SCR device is active, and the collector current of NPN is generated to bias the PNP transistor. Then, the PNP is turned on, the collector current of PNP is also generated to further bias the NPN transistor. The positive-feedback regenerative mechanism of latchup is initiated by the substrate-triggered current in SCR structure instead of avalanche breakdown mechanism. On the other hand, when the trigger current is drawn from the n-trigger node, the positive-feedback mechanism is also generated.
On the whole-chip ESD protection, the double-triggered SCR (including the n-trigger
and p-trigger) is set between the power-rail, I/O pad to VDD and VSS, respectively. In order to save the layout area, the RC-based ESD detection circuit can be shared and connect to each double-triggered SCR, as shown in Fig. 1.22.
1.3.5 The Native-NMOS-Triggered Technique
Using the parasitic PMOS structure to trigger the SCR ESD protection device is introduced as above. There is another trigger method by using the native-NMOS with very low threshold voltage about 0.1 V to trigger the SCR device [18]. Compared with the traditional low-voltage-triggered SCR (LVTSCR), the drain of native NMOS in native-NMOS-triggered SCR (NANSCR) is directly coupled to the anode of SCR, but the drain of NMOS in LVTSCR is set across the N Well/P Substrate junction of the SCR device, as shown in Figs. 1.23(a) and 1.23(b), respectively.
The gate of native NMOS is connected to a negative bias circuit (NBC) to keep off the NANSCR during normal circuit operation. The NBC is composed of clock generator, capacitors and diodes. The output negative voltage of NBC can be tuned to fulfill various applications. During the ESD event, the NBC is relatively floating, the native NMOS is an initial-on device as the PMOS-triggered SCR. Then, the trigger current flows into the base of NPN and the base voltage of NPN will be raised up by the substrate resistor (Rsub). Once the voltage across the base and emitter of NPN exceeds 0.7 V, the NPN in SCR structure is turned on. After the NPN turns on, the PNP is also turned on by the collector current of NPN.
Therefore, the positive-feedback mechanism of the NANSCR is initiated by the trigger current of the initial-on native NMOS in the NANSCR device. Finally, the NANSCR will be triggered on to discharge the ESD current. In addition, comparing with the TLP I-V curve of the LVTSCR and NANSCR, the turn-on resistance and holding voltage of NANSCR are smaller than those of LVTSCR on the same device width.
1.3.6 The Dummy-Gate Structure Technique
The dummy-gate structure is used to block the shallow trench isolation (STI) and silicide between the diffusion regions as shown in Figs. 1.24(a) and 1.24(b) [19], the ESD current discharge path can be changed to enhance the turn on speed of the ESD protection device. For example, to merge the dummy-gate structure with the substrate-triggered SCR
(STSCR) device. Due to the deeper STI region causes a longer current path from the anode to cathode, the dummy-gate structure can block the STI region to smaller the current path. This STSCR with dummy-gate structure can be used in input, output and power-rail ESD protection device. In order to prevent the device suffering latchup, the voltage drop elements (such as diodes) can be stacked with the dummy-gate structure STSCR to raise the total holding voltage.
Comparing on the STSCR device with STI and dummy-gate structure, the trigger voltage can be further reduced by the dummy-gate structure than STI structure under the same trigger current. The reason is the current gain (β) of parasitic BJT in dummy-gate structure is higher than in STI structure by the shorter current path.
1.3.7 The Self-Substrate-Triggered Technique
The self-substrate-triggered technique is to conduct the ESD current to the desired finger location and use the ESD current to trigger other fingers [20]. This trigger method will improve the turn-on uniformity and the HBM and It2 level of the GGNMOS substantially, but the trigger voltage and holding voltage will not change.
Due to the base resistance in parasitic NPN of the center-finger GGNMOS is higher than other fingers, the center-finger of GGNMOS is always triggered first. Once the center-finger of NMOS has been triggered, the ESD voltage will let the device into snapback status. Therefore, the ESD current will be only discharged through few part of device to cause the non-uniform turn on issue.
In order to guarantee the center-finger of the GGNMOS will turn on first, let the channel length of the center-finger be the minimum rule and other fingers with larger channel length. The cross-sectional view of the self-substrate-triggered GGNMOS is shown in Fig.
1.25, the source of the center-finger is connected to the substrate-triggered node.