Experimental Results

Five kinds of HV ESD protection devices have been investigated : LD-NMOS, LD-PMOS, NFOD, dual-direction SCR and NSCR. They are manufactured in a 0.25μm 18V BCD technology, the additional mask layers are HV N Well, HV NDDD, HV PDDD and P Drift. All of them are lightly doped layers and they are used to increase the breakdown voltage. The doping concentration of Drift layer is higher than DDD layer.

3.2.1 The High-Voltage LD-NMOS

The device cross-sectional view and layout view of HV LD-NMOS in the given 0.25μm 18V BCD process are shown in Figs. 3.6(a) and 3.6(b), respectively. The HV LD-NMOS is fabricated in the HV N Well and the source and bulk regions are inside it. The effective channel length is the overlap region of the P Drift and the polygate; the HV NDDD layer in the drain region is used to increase the breakdown voltage; the HV RPO (Resistor Protect Oxide) layer is used to block the silicide region and increase the surface resistance between the drain side and polygate. The breakdown voltage is determined by the HV N Well/P Drift junction while the LD-NMOS is gate-grounded and the ESD pulse is zapped at drain side. In

addition, the β gain of the parasitic NPN transistor is large enough to cause strong snapback characteristic after the device enters trigger state.

The split layout parameters are the N+ edge to contact spacing of the drain side named N_C, the OD region beyond N+ edge of the drain side named D_O, the HV NDDD spacing of the drain side named H_N, the P+ edge to polygate spacing of the source side named P_P and the device total width named W.

To measure the TLP I-V curve, the failure criterion is determined by the leakage current over 1μA when the drain bias is 18V. With increasing the device total width from 400μm to 800μm (one finger width is 50μm), the trigger voltage, holding voltage and the It2 value can be increased a little due to the non-uniform turn-on characteristic of the LD-NMOS is more serious than traditional NMOS, as shown in Figs. 3.7(a) and 3.7(b). With increasing the D_O and P_P spacing of the drain side and source side, the holding voltage will be raised and the It2 value will be decreased due to the total power dissipation is kept the same, as shown in Figs.3.8 and 3.9, respectively. With increasing the N_C spacing of the drain side, the ballast resistance of the surface will be increased and the ESD current can flow deeper to protect the gate oxide. Therefore, the holding voltage can be increased due to the longer current path from drain to source and the It2 value can be increased due to the deeper current path have higher current conduction area. With increasing the N_C spacing from 1μm to 4μm, the holding voltage can be doubled and the It2 value can be increased from 0.2A to 2.5A, as shown in Figs. 3.10(a) and 3.10(b). With increasing the N_C spacing from 1μm to 3μm and H_N spacing from 9μm to 18μm on the same time, the holding voltage and It2 value seem to not change substantially, as shown in Figs. 3.11 ~ 3.13. But, when the N_C spacing is 4μm, the holding voltage and It2 value are decreased with the H_N spacing increasing. The maximum holding voltage and It2 value can be implemented by N_C spacing with 4μm and H_N spacing with 9μm, as shown in Figs. 3.14(a) and 3.14(b). Moreover, the leakage will be improved to 0.1 nano ampere order while the N_C spacing is above 1μm, as shown in Figs.

3.7 ~ 3.14.

The HBM and MM robustness are measured by HANWA ESD simulator HED W5100D, the failure criterion is determined by the I-V curve shifts over 30％. Table 3.1 ~ 3.4 show the HBM and MM ESD levels in different layout parameters of LD-NMOS as above, the HBM level will pass 2kV and the MM level will pass 200V when the N_C spacing is 3μm or above. Therefore, the N_C spacing is the critical ESD design parameter.

In addition, to investigate the influence on separating the source and bulk regions, there

are four layout parameters to discuss with the source to bulk spacing (S_B). The four layout parameters are device total width, polygate length and channel length, as shown in Fig. 3.15.

Theoretically, with increasing the S_B spacing, the breakdown voltage will not change, but the current should flow through an added resistor built by the separation of the source and bulk region. Then, the trigger voltage will be increased to turn-on the device.

With increasing the total width from 100 and 200μm and S_B spacing from 0 and 2μm, the measurement shows that the larger total width can obtain larger It2 level and the no butted structure is suitable for the larger total width uniform turn-on, as shown in Figs. 3.16(a) ~ 3.16(c). With increasing channel length from 0.35 and 0.5μm and S_B spacing from 0 and 2μm, the better It2 level can be obtained by smaller channel length and butted structure, as shown in Figs. 3.17(a) ~ 3.17(c). With increasing the polygate length from 1 and 1.5μm and S_B spacing from 0 and 2μm, the trigger voltage will be increased by larger polygate length substantially due to the current flow through an added path in HV N Well region and the better It2 level can be obtained by smaller polygate length and butted structure, as shown in Figs. 3.18(a) ~ 3.18(c). Therefore, the butted structure, relative small channel length and polygate length are suitable for LD-NMOS to be a ESD protection device.

3.2.2 The High-Voltage LD-PMOS

Figs. 3.19(a) and 3.19(b) shows the cross-sectional and layout view of the LD-PMOS, the LD-PMOS is fabricated in the HV N Well as the LD-NMOS. The effective channel length is the polygate length subtracts its overlap region of the HV PDDD layer. The HV PDDD layer is used to increase the breakdown voltage. Due to the β gain of PNP transistor is smaller than NPN transistor, the snapback characteristic will be reduced to very unapparent.

The breakdown voltage is determined by the HV N Well/HV PDDD junction while the LD-PMOS is gate-VDD and the ESD pulse is zapped at source side.

The split layout parameters are the P+ edge to contact spacing of the drain side named P_C, the HV PDDD spacing of the drain side named H_P, the N+ edge to polygate spacing of the source side named N_P and the device total width named W.

To measure the TLP I-V curve, the failure criterion is also determined by the leakage current over 1μA when the gate bias is 18V. With increasing the device total width from 400μm to 800μm, the trigger voltage is almost the same, but holding voltage will be decreased and It2 value will be increased, as shown in Figs. 3.20(a) and 3.20(b). With

increasing the H_P spacing from 6μm to 15μm, the trigger and holding voltage are almost the same, but the It2 value will be decreased, as shown in Figs. 3.21(a) and 3.21(b). With increasing the P_C spacing from 1μm to 3μm, the trigger and holding voltage are almost the same, but the It2 value will be increased, as shown in Figs. 3.22(a) and 3.22(b). With increasing the N_P spacing from 1μm to 4μm, the trigger voltage is almost the same, but the holding voltage will be decreased and the It2 value will be increased, as shown in Figs.

3.23(a) and 3.23(b). Moreover, the It2 value of LD-PMOS is too low in different layout splits.

Table 3.5 ~ 3.8 show the HBM and MM ESD levels of different layout parameters of LD-PMOS as above, the HBM and MM level are too low to pass the specification 2kV and 200V, respectively. Therefore, the LD-PMOS is not suitable to be a ESD protection device.

3.2.3 The High-Voltage NFOD

The N-type Field Oxide Device (NFOD) is fabricated through replacing the gate oxide by the Shallow Trench Isolation (STI), as shown in Fig. 3.24. The NFOD will be turned on by the parasitic NPN transistor turn-on due to the channel is no longer exist. To investigate the influence on ESD performance, there are four layout parameters have to be discuss, the device total width named W, STI spacing named S, N+ edge to contact spacing of drain side named N_C and source to bulk spacing named S_B. In addition, the C spacing means the P Drift edge to STI edge spacing and it is fixed at 0.5μm.

With increasing the total width from 100μm to 200μm (one finger width is 50μm) and S_B spacing from 0 and 2μm, the trigger and holding voltage are almost the same no matter what the S_B spacing is. But the larger S_B spacing reduces the It2 value apparently when the width is 200μm, as shown in Figs. 3.25(a) ~ 3.25(c). With increasing the S spacing from 1 and 1.5μm and S_B spacing from 0 and 2μm, the trigger voltage will be increased substantially due to the added path in the HV N Well region and the holding will be increased a little. The It2 value will be higher when the S_B spacing is 2μm, as shown in Figs. 3.26(a)

~ 3.26(c). With increasing the N_C spacing from 2 and 4μm and S_B spacing from 0 and 2μm, the trigger and holding voltage are almost the same no matter what the S_B spacing is, but the It2 value will be increased apparently. Moreover, when the S_B spacing is 2μm, the It2 value can be increased a little, as shown in Figs. 3.27(a) ~ 3.27(c).

Therefore, the better ESD performance in NFOD can be obtained by larger device total width, larger N_C spacing and butted structure. In addition, the leakage current of the

different NFOD as above are all in 0.1 nano ampere order before the device is destroyed.

3.2.4 The High-Voltage Dual-Direction SCR

There are three kinds of dual-direction SCR have been tested, the dual-direction structure is used when the power supply is operate between negative to positive voltage. Figs.

3.28 (a) and 3.28(b) show cross-sectional view and the layout diagram of the type I SCR, it is fabricated in the HV N Well and the HV N Well is floating. The parasitic diode is no longer exist than traditional SCR device. There are two SCR path in this structure, the path 1 (P+ (P Drift) /HV N Well/P Drift/N+) from left to right side is a short path when node 1 is zapped and node 2 is grounded, the path 2 (P+ (P Drift) /HV N Well/P Drift/N+) from right to left side is a long path when node 2 is zapped and node 1 is grounded. In addition, the width of this dual-direction SCR is 50μm.

There are two layout parameters to be tested in the type I SCR, the P+ edge to STI edge spacing named C and the STI spacing named S. With increasing the C spacing from 1 and 4μm and fix the S spacing at 2 and 3μm, the holding voltage can be increased substantially in path 2 and the holding voltage can be increased a little in path 1, as shown in Figs. 3.29(a) and 3.29(b), 3.30(a) and 3.30(b). The reason why the holding voltage of path 2 is higher than path 1 is the longer current path. With increasing the S spacing from 2 and 4μm and fix the C spacing at 3μm, the holding will be also increased in path 1 and path 2 but not obvious than tuning the C spacing, as shown in Figs. 3.31(a) and 3.31(b). Therefore, the C spacing is the dominant factor to improve the holding voltage in type I SCR

Fig. 3.32 shows the type II SCR structure, this dual-direction SCR is fabricated in the P Substrate and the P Substrate is floating. The low doping concentration layers of HV PDDD and HV NDDD are used to increase the breakdown voltage and the type III SCR is to replace the HV PDDD layer by the P Drift layer, as shown in Fig. 3.34. The modified layout parameter of type II and III SCR is the STI spacing named S. With increasing the S spacing from 8 and 14μm, the holding voltage can be both increased about 5V and the holding voltage of path 2 is over the operation voltage 18V to avoid the latchup issue in type II and III SCR, as shown in Figs. 3.33(a) and 3.33 (b), 3.35(a) and 3.35(b).

The It2 value of these three kinds of SCR are all passed 5A in path 1 and 4A in path 2 The HBM and MM level of them are all passed 8kV and 400V in path 1, respectively. With increasing the modified parameter spacing, the HBM and MM level can be increased about 6kV and 300V, respectively, as shown in Figs. 3.29(c) and 3.29 (d), 3.30(c) and 3.30(d),

3.31(c) and 3.31(d), 3.33(c) and 3.33(d), 3.35(c) and 3.35(d). In addition, the leakage current of these three types SCR are all in pico ampere order before the device is destroyed.

Therefore, the SCR devices have the best ESD performance in It2 value, HBM level and MM level than other devices.

3.2.5 The High-Voltage NSCR

The NSCR is made by inserting a P+ diffusion in the drain side of the LD-NMOS to establish a SCR path from drain to source [40]. Due to the doping concentration of the N Well is higher than the HV NDDD, by adding the N Well beneath the P+ diffusion of the drain side can be used to conduct currents into the HV N Well and hence increase the turn-on speed of the NSCR, as shown in Fig. 3.36. The NSCR is a LD-NMOS triggered SCR, where the LD-NMOS is used to triggered the SCR. Therefore, the trigger voltage is almost the same as LD-NMOS. Some variation still exists due to the injection hole currents from the anode of the SCR.

There are three layout parameters be modified to find the ESD rule, the device total width named W, the N+ edge to contact spacing of the drain side named N_C, the polygate length and the channel length. With increasing the total width from 100μm to 200μm (one finger width is 50μm) and S_B spacing from 0 and 2μm, the holding voltage are almost the same no matter what the S_B spacing is and the larger It2 value can be obtained by larger total width and butted structure, as shown in Figs. 3.37(a) ~ 3.37(c). With increasing the N_C spacing from 2μm to 4μm and S_B spacing from 0 and 2μm, the higher holding voltage and It2 value can be obtained by larger N_C spacing, as shown in Figs. 3.38(a) ~ 3.38(c). With increasing the polygate length from 1μm to 1.5μm and S_B spacing from 0 and 2μm, the trigger voltage can be increased substantially by the added current path in the HV N Well region. The higher It2 value can be obtained by larger S_B spacing when the polygate length is relative small, as shown in Figs. 3.39(a) ~ 3.39(c). With increasing the channel length from 0.35μm to 0.5μm and S_B spacing from 0 and 2μm, the higher It2 value can be obtained by larger channel length and S_B spacing, as shown in Figs. 3.40(a) ~ 3.40(c).

The It2 value as above NSCR devices are almost 2A and the holding voltage is higher than that of the traditional SCR. Moreover, the leakage current of the NSCR is in 0.1 nano ampere order before the device is destroyed. Therefore, the better ESD performance of the NSCR can be obtained by larger total width, N_C spacing and channel length.