Power MOS Transistors

MOS transistors can drive large amounts of power are called power transistors to distinguish them from low-power or small-signal devices. The power MOS can conduct large currents at low drain-to-source voltage by the low impendence characteristic. At low drain-to-source voltage (V_DS<<V_GS-V_t), the Shichman-Hodges equation in the linear region will be derived from I_d=k(V_GS-V_t)V_DS+kV_DS²/2 to I_d=k(V_GS-V_t)V_DS. The on resistance RDS(on) varies inversely with the product of the transconductance and the effective gate voltage (VGS-Vt), it will be RDS(on)=1/k(VGS-Vt). The RDS(on) of the power MOS transistors are usually measured at a specified gate voltage VGS and junction temperature. The RDS(on) of a power MOS transistor typically increases 50％ when the junction temperature rises from 25℃ to 125℃.

The metallization resistance becomes significant for on resistance of less than an Ohm order, and the equation for RDS(on) then becomes RDS(on) =1/k(VGS-Vt)+RM. Where the RM

is the sum of the resistance of the source and drain metallization. This metallization resistance is difficult to calculate because it depends on transistor geometry. There are several metal line layout patterns have been published as shown in Figs. 2.1(a) ~ 2.1(c). Fig. 2.1(a) shows a common arrangement in which both terminations lie on the same side of the transistor. The paired terminations may be more adjacent to the bond pads, but they produce excessive voltage drop and an uneven distribution of current in the device. Fig. 2.1(b) shows a better arrangement where the source and drain terminations lie on the opposite sides of the transistor. This arrangement delivers a more even distribution of current and exhibiting a lower total resistance than the pattern in Fig. 2.1(a). Fig. 2.1(c) shows the method to minimize the metallization resistance. The termination points lie on the middle of both buses, so the current does not have to flow through the full length of the buses.

The smart power integrated circuit technology is composed of VLSI digital/analog signal processing and high power output current driver on the same chip. The percentage split in chip area is uncommonly by 50% to 50% each. The signal processing part is consist of low voltage (LV) circuits；The power output current driver usually operates in high voltage (HV) and/or high current supply.

The smart power integrated circuit technology applies in Automotive Electronics, Telecommunications, Power management, LCD (Liquid Crystal Display) or EL (Electro Luminescence) industry, etc [21]. Especially the large number of column and row drivers of the LCD industry, the driving speed in dependent on the frame rate and scan rate of the display. For a refresh frame rate of 60 frames per second on the VGA definition (640 x 480), a minimum scan rate of 30 kHz is needed. For these reasons, MOS technology is preferred to approach these performances. How to improve the density and switching speed of the high voltage output transistors is the main challenge in the next generation of high-definition (HD) performance.

Power devices in smart power integrated circuit technology are usually required to perform switching functions. The gate drive characteristic of the MOSFETs is more favorable than the bipolar junction transistors (BJTs) with large base current to turn on/off. One of the main advantages of power MOSFETs is that the gate only requires a bias voltage with no steady-state current to switch between the on and off states. Due to above reasons, the inherent switching speed of MOSFETs is faster than for power BJTs.

Most high voltage devices are used as switches operating between the on and off states and designed to operate in the 1^st quadrant, occasionally in the 3^rd quadrant as shown in Fig.

2.2. The I-V curve is similar to the conventional MOSFETs except that the power devices usually switch between fully on and fully off – cutoff or triode region. The power devices rarely operate in the saturation region (except as amplifiers) because of power dissipation limits.

Power MOSFETs can be categorized into V-MOS, VDMOS, UMOS, IGBT and LDMOS. The V-MOS have a V-groove etch from the top side of the wafer using a preferential etch and the channel is formed along the wall of the V-groove as shown in Fig.

2.3(a). The V-MOS was the first commercial power MOSFET structure, however it is quickly replaced by the VDMOS due to manufacturing problems and the concentration of high electric field at the tip of the V-groove. The VDMOS has a conventional surface channel while still relying on double diffusion to produce the short channel length as shown in Fig.

2.3(b). The UMOS uses a trench etching technique to turn the channel into a vertical direction as shown in Fig. 2.3(c). In the V-MOS, VDMOS and UMOS, the forward blocking capability is provided by the P Well to N Epi junction. Due to higher doping concentration of the P Well region, the depletion region extends mostly into the N Epi region. Therefore, the choice of N Epi doping concentration can directly affects the breakdown voltage and on-resistance of the power MOSFETs. The IGBT (Insulated Gate Bipolar Transistor) is use the P+ substrate to replace the N+ substrate and then a merged MOS-Bipolar device can be made as shown in Fig. 2.3(d). The IGBT offers enough amounts of current handling capability, but with slower switching speed. The IGBT is a dominant power device in high current application. The V-MOS, VDMOS, UMOS, IGBT as above are vertical devices, the drawback of the vertical devices is that it is difficult to include multiple power devices on the same chip. But the lateral structure allows all terminals to be accessed from the top surface of the chip.

The current flows from the drain, laterally along the surface through the MOS channel and up into the source, hence the name Lateral Double-Diffused MOSFETs (LDMOS) as shown in Fig. 2.4(a) [22]-[25]. LDMOS generally has a higher on-resistance due to the longer current path than vertical devices. Furthermore, the breakdown voltage of the LDMOS depends critically on the curvature of the P Well to N Drift region junction. In order to obtain high breakdown voltage, it is necessary to use a low doping concentration in the N Drift region. However, this will cause a high turn-on resistance.

To provide a device with high breakdown voltage and low turn-on resistance, an advanced technique called REduced SURface Field (RESURF) was developed as shown in Fig. 2.4(b) [26]-[27]. The RESURF device structure is the same as the LDMOS, except the much thinner N Epi layer is added for the N Drift region. Through a well-tuning doping concentration in the N Drift region, a much lower turn-on resistance can be produced without decreasing in breakdown voltage.

The breakdown voltage of LDMOS is mainly between 20 V to 100 V and is more suitable for automotive applications. The remaining issue is to reduce the series resistance of the metal interconnection and bonding wires. Due to the specific lower on-resistance and high breakdown voltage, the LDMOS can as for output current driver and self high-voltage ESD protection device simultaneously.

This chapter will discuss the whole mechanisms of the LDMOS including the turn-on mechanism, the double-snapback characteristic and the isolation method to implement the high breakdown voltage.

2.2 The Turn-On Mechanism and Double-Snapback Characteristic of the High-Voltage LD-NMOS and

High-Voltage NMOS Devices

The turn-on mechanism of the LD-NMOS device is caused by the positive feedback between the turn-on BJT of the source side and the N/N+ junction avalanche breakdown of the drain side and it’s called the double snapback characteristic. Although the N/N+ junction is the most basic parasitic structure in the device, which plays a major role in the snapback characteristic.

In order to analyze the I-V curve of the LD-NMOS structure, there are three points that have been sampled as shown in Fig. 2.5(a). Point A denotes the turn-on BJT of the source side and the point C denotes the N/N+ junction avalanche breakdown of the drain side. With increasing the applied voltage in the drain side, the more excess electrons from the N+ source induce the more excess holes from N+ drain in the HV N Well/P Body junction. These space charges will become denser at the junction and raise the electric field. Moreover, one part region of the HV N Well with excess holes become an extension of the P Body layer. In other words, this effect is the same as the “Kirk effect [28]-[29]” of the BJT and the extension region will reach the N+ drain region until the excess electrons concentration is less than the N+ drain doping concentration. As a result, the electrical field peak moves from the HV N Well/P Body junction to the N/N+ junction of the drain side, as shown in Fig. 2.5(b). This electric field peak leads the N/N+ junction avalanche breakdown and feedbacks additional hole current to the P Body.

The electric field of point A is large enough to trigger the impact ionization effect and the electric field of point B will enhance the ionization. Due to the avalanche multiplication occurred in the HV N Well/P Body junction, the voltage to sustain the junction breakdown is reduced, and then it snapbacks to low voltage and causes a negative slope after point A. Point C denotes the electric field peak reaches the N/N+ junction to cause the junction avalanche breakdown. Then, the feedback hole current will improve the multiplication effect in the HV N Well/P Body junction and snapback to low voltage again.

Compared to other structure of HV device, the HV NMOS with deeper N Well and N+

Buried Layer (NBL) can also have the double snapback characteristic, as shown in Fig. 2.6(a).

Due to the doping concentration of the NBL is higher than the N Well region, the breakdown

voltage is determined by the NBL/P Well junction and the first snapback is caused by the turn-on of BJT. After turn-on the BJT, the current flows vertically into the NBL region will result in a longer current path and the turn-on resistance will become larger. When the current further increases, the “Kirk effect” happens and the electric field peak moves from NBL/P Well junction to N Well/N+ junction. Then, the N Well/N+ junction will go into avalanche breakdown and increase the multiplication rate to snapback to lower holding voltage, as shown in Fig. 2.6(b). The current path of this HV structure will be changed from vertical path to lateral path and get a smaller turn-on resistance after the second snapback.

But not all HV devices have the double snapback characteristic [30], if the current path will not change, the second snapback characteristic will be not obvious or be no longer exist.

Figs. 2.7(a) and 2.7(b) show the HV device structure without the double snapback characteristic and its TLP I-V curve. The shallow N Grade region is to sustain the high breakdown voltage, before and after the N Grade/P Well junction breakdown, the current path is always in the lateral direction.