In order to reach the desired ESD performance in 0.25μm 18V BCD process, there are various layout splits have been verified in this thesis.
This thesis is composed of five chapters. Chapter 1 presents the fundamental concept of ESD protection design by device layout modification and extra trigger circuit. In order to get the appropriate trigger voltage and holding voltage in high voltage operation to protect the
internal circuit and suppress the latchup effect, there are several methods to reduce the trigger voltage and the suitable device structure to avoid the latchup happens
In chapter 2, presents an overview on several power MOS transistors and their advantages and disadvantages in current path and reliability. To research one kind of power MOS transistors, the DMOS is the main topic of this thesis. Then, discuss the turn-on mechanism and double-snapback characteristic in HV LD-NMOS and HV NMOS. Such turn-on mechanism is very important on designing the trigger and holding voltage.
In chapter 3, presents the HV BJT with controllable trigger and holding voltage, the HV NMOS with Embedded SCR structure and HV BJT with Embedded SCR Structure those have been reported first. Then, the experimental results show the ESD performance of HV LD-NMOS, HV LD-PMOS, HV NFOD, HV dual-direction SCR and HV NSCR by layout modification. The ESD performance of LD-NMOS, NFOD and NSCR can be improved to 2A by increasing the N+ edge to contact spacing of the drain side. The dual-direction SCR can be used in discharging the ESD current while the operation voltage is from negative to positive. With increasing the layout parameters of dual-direction SCR, the It2 value, HBM and MM level can be improved to about 4A, 6KV and 300V, respectively.
In chapter 4, presents the failure mechanism of the LD-NMOS and introduce the methods of no turn-on parasitic BJT and no snapback characteristic in LD-NMOS. To make sure the no snapback characteristic can be made correctly, the PSB (P type Sub Body) layer of 0.25μm 18V BCD process is added to let the ESD protection device not to snapback. The PSB layer is verified in small device (total width <5k μm) and large device (total width > 5k μm) to investigate the influence on ESD performance of LD-NMOS. In larger device, the PSB layer can reach the no snapback characteristic and have the best turn-on uniformity.
Finally, the main results of this thesis are summarized in chapter 5, the future work is to research the holding voltage is different by TLP and 370A measuring. In addition, the trigger elements have to be added in the dual-direction SCR to reduce the trigger voltage without extra layout area.
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(c) (d)
Fig. 1.1 The I-V curve of the four common ESD protection devices: (a) gate-grounded NMOS (GGNMOS), (b) gate-VDD PMOS (GDPMOS), (c) parasitic silicon controlled rectifier (SCR), and (d) diode.
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Fig. 1.2 The four pin-combination modes for ESD test: (a) positive-to-VSS (PS-mode), (b) negative-to-VSS (NS-mode), (c) positive-to-VDD (PD-mode), and (d) negative-to-VDD (ND-mode).
Fig. 1.3 The whole-chip ESD protection circuits in CMOS IC.
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(b) (c)
Fig. 1.4 (a) The parasitic SCR path in CMOS ICs. (b) The equivalent circuit of SCR. (c) The two terminals and four layers P-N-P-N of SCR.
Fig. 1.5 The latchup-free current gain (β) product parabola curve.
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Fig. 1.6 (a) The N+/N Well guard ring, (b) The P+/P Substrate guard ring, (c) The double guard ring.
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Fig. 1.7 The device cross-sectional views of (a) isolated HV NMOS, (b) non-isolated HV NMOS, (c) non-isolated symmetric HV NMOS, (d) isolated asymmetric HV
NMOS and HV PMOS.
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Fig. 1.8 (a) The stacked power rail ESD protection device and its RC-based detection circuit. (b) The TLP I-V curves of single FOD and stacked-FOD.
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Fig. 1.9 (a) ~ (b) The traditional ESD protection device with the initial-off characteristic.
(c) ~ (e) The ESD protection device with the initial-on characteristic.
Fig. 1.10 The ESD protection design window in traditional SCR device.
Fig. 1.11 The cross-sectional view of the initial-on SCR with PMOS trigger technique.
Fig. 1.12 The equivalent circuit of the initial-on SCR with PMOS trigger.
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Fig. 1.13 The layout view of the initial-on SCR with PMOS trigger (a) The common layout pattern, (b) The n-trig node merged into the source side of the embedded PMOS structure.
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Fig. 1.14 (a) The cross-sectional view of the dual-direction SCR structure, (b) The trigger node and the trigger method with two pair back-to-back Zener diode, (c) The TLP I-V characteristic of the dual-direction SCR.
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(b) (c) (d)
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Fig. 1.15 (a) The layout cell structure of the dual-direction SCR, (b) The layout view of corner cell, (c) The layout view of edge cell, (d) The layout view of center cell, (e) The cross-sectional view of corner cell, (f) The cross-sectional view of edge cell, (g) The cross-sectional view of center cell.
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Fig. 1.16 (a) The ESD current always flow through the center-finger of GGNMOS first, (b) The center-finger will burn out by the joule heating.
Fig. 1.17 The gate-coupled structure and the turn-on sequence of the gate-coupled technique.
Fig. 1.18 The TLP I-V curves of various rising time of the ESD pulse.
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Fig. 1.19 (a) The HV NPN BJT, (b) The HV NPN-SCR, (c) The HV NSCR.
Fig. 1.20 The TLP I-V curves and turn-on resistances of the different substrate trigger current on GGNMOS (added trigger current：curve A > curve B > curve C).
Fig. 1.21 The double-substrate-triggered structure (including the P-trigger node and N-trigger node).
Fig. 1.22 The whole-chip ESD protection with shared ESD detection circuit for input, output and power-rail ESD clamp devices.
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Fig. 1.23 The circuit schematics of (a) the native-NMOS-triggered SCR (NANSCR), (b) the traditional LVTSCR.
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Fig. 1.24 The circuit schematics of (a) the native-NMOS-triggered SCR (NANSCR), (b) the traditional LVTSCR.
Fig. 1.25 The cross-sectional view of the self-substrate-triggered GGNMOS. The P+
trigger node connects to the source terminal of the center-finger.
CHAPTER 2
OVERVIER ON POWER MOSFETs FOR HIGH-VOLTAGE ESD PROTECTION DESIGN
2.1 Power MOS Transistors
MOS transistors can drive large amounts of power are called power transistors to distinguish them from low-power or small-signal devices. The power MOS can conduct large currents at low drain-to-source voltage by the low impendence characteristic. At low drain-to-source voltage (VDS<<VGS-Vt), the Shichman-Hodges equation in the linear region will be derived from Id=k(VGS-Vt)VDS+kVDS2/2 to Id=k(VGS-Vt)VDS. The on resistance RDS(on) varies inversely with the product of the transconductance and the effective gate voltage (VGS-Vt), it will be RDS(on)=1/k(VGS-Vt). The RDS(on) of the power MOS transistors are usually measured at a specified gate voltage VGS and junction temperature. The RDS(on) of a power MOS transistor typically increases 50％ when the junction temperature rises from 25℃ to 125℃.
The metallization resistance becomes significant for on resistance of less than an Ohm order, and the equation for RDS(on) then becomes RDS(on) =1/k(VGS-Vt)+RM. Where the RM
is the sum of the resistance of the source and drain metallization. This metallization resistance is difficult to calculate because it depends on transistor geometry. There are several metal line layout patterns have been published as shown in Figs. 2.1(a) ~ 2.1(c). Fig. 2.1(a) shows a common arrangement in which both terminations lie on the same side of the transistor. The paired terminations may be more adjacent to the bond pads, but they produce excessive voltage drop and an uneven distribution of current in the device. Fig. 2.1(b) shows a better arrangement where the source and drain terminations lie on the opposite sides of the transistor. This arrangement delivers a more even distribution of current and exhibiting a lower total resistance than the pattern in Fig. 2.1(a). Fig. 2.1(c) shows the method to minimize the metallization resistance. The termination points lie on the middle of both buses, so the current does not have to flow through the full length of the buses.
The smart power integrated circuit technology is composed of VLSI digital/analog signal processing and high power output current driver on the same chip. The percentage split in chip area is uncommonly by 50% to 50% each. The signal processing part is consist of low voltage (LV) circuits；The power output current driver usually operates in high voltage (HV) and/or high current supply.
The smart power integrated circuit technology applies in Automotive Electronics, Telecommunications, Power management, LCD (Liquid Crystal Display) or EL (Electro Luminescence) industry, etc [21]. Especially the large number of column and row drivers of the LCD industry, the driving speed in dependent on the frame rate and scan rate of the display. For a refresh frame rate of 60 frames per second on the VGA definition (640 x 480), a minimum scan rate of 30 kHz is needed. For these reasons, MOS technology is preferred to approach these performances. How to improve the density and switching speed of the high voltage output transistors is the main challenge in the next generation of high-definition (HD) performance.
Power devices in smart power integrated circuit technology are usually required to perform switching functions. The gate drive characteristic of the MOSFETs is more favorable than the bipolar junction transistors (BJTs) with large base current to turn on/off. One of the main advantages of power MOSFETs is that the gate only requires a bias voltage with no steady-state current to switch between the on and off states. Due to above reasons, the inherent switching speed of MOSFETs is faster than for power BJTs.
Most high voltage devices are used as switches operating between the on and off states and designed to operate in the 1st quadrant, occasionally in the 3rd quadrant as shown in Fig.
2.2. The I-V curve is similar to the conventional MOSFETs except that the power devices usually switch between fully on and fully off – cutoff or triode region. The power devices rarely operate in the saturation region (except as amplifiers) because of power dissipation limits.
Power MOSFETs can be categorized into V-MOS, VDMOS, UMOS, IGBT and LDMOS. The V-MOS have a V-groove etch from the top side of the wafer using a preferential etch and the channel is formed along the wall of the V-groove as shown in Fig.
2.3(a). The V-MOS was the first commercial power MOSFET structure, however it is quickly replaced by the VDMOS due to manufacturing problems and the concentration of high electric field at the tip of the V-groove. The VDMOS has a conventional surface channel while still relying on double diffusion to produce the short channel length as shown in Fig.
2.3(b). The UMOS uses a trench etching technique to turn the channel into a vertical direction as shown in Fig. 2.3(c). In the V-MOS, VDMOS and UMOS, the forward blocking capability is provided by the P Well to N Epi junction. Due to higher doping concentration of the P Well region, the depletion region extends mostly into the N Epi region. Therefore, the choice of N Epi doping concentration can directly affects the breakdown voltage and on-resistance of the power MOSFETs. The IGBT (Insulated Gate Bipolar Transistor) is use the P+ substrate to replace the N+ substrate and then a merged MOS-Bipolar device can be made as shown in Fig. 2.3(d). The IGBT offers enough amounts of current handling capability, but with slower switching speed. The IGBT is a dominant power device in high current application. The V-MOS, VDMOS, UMOS, IGBT as above are vertical devices, the drawback of the vertical devices is that it is difficult to include multiple power devices on the same chip. But the lateral structure allows all terminals to be accessed from the top surface of the chip.
The current flows from the drain, laterally along the surface through the MOS channel and up into the source, hence the name Lateral Double-Diffused MOSFETs (LDMOS) as shown in Fig. 2.4(a) [22]-[25]. LDMOS generally has a higher on-resistance due to the longer current path than vertical devices. Furthermore, the breakdown voltage of the LDMOS depends critically on the curvature of the P Well to N Drift region junction. In order to obtain high breakdown voltage, it is necessary to use a low doping concentration in the N Drift region. However, this will cause a high turn-on resistance.
To provide a device with high breakdown voltage and low turn-on resistance, an advanced technique called REduced SURface Field (RESURF) was developed as shown in Fig. 2.4(b) [26]-[27]. The RESURF device structure is the same as the LDMOS, except the much thinner N Epi layer is added for the N Drift region. Through a well-tuning doping concentration in the N Drift region, a much lower turn-on resistance can be produced without decreasing in breakdown voltage.
The breakdown voltage of LDMOS is mainly between 20 V to 100 V and is more suitable for automotive applications. The remaining issue is to reduce the series resistance of the metal interconnection and bonding wires. Due to the specific lower on-resistance and high breakdown voltage, the LDMOS can as for output current driver and self high-voltage ESD protection device simultaneously.
This chapter will discuss the whole mechanisms of the LDMOS including the turn-on mechanism, the double-snapback characteristic and the isolation method to implement the high breakdown voltage.
2.2 The Turn-On Mechanism and Double-Snapback Characteristic of the High-Voltage LD-NMOS and
High-Voltage NMOS Devices
The turn-on mechanism of the LD-NMOS device is caused by the positive feedback between the turn-on BJT of the source side and the N/N+ junction avalanche breakdown of the drain side and it’s called the double snapback characteristic. Although the N/N+ junction is the most basic parasitic structure in the device, which plays a major role in the snapback characteristic.
In order to analyze the I-V curve of the LD-NMOS structure, there are three points that have been sampled as shown in Fig. 2.5(a). Point A denotes the turn-on BJT of the source side and the point C denotes the N/N+ junction avalanche breakdown of the drain side. With increasing the applied voltage in the drain side, the more excess electrons from the N+ source induce the more excess holes from N+ drain in the HV N Well/P Body junction. These space charges will become denser at the junction and raise the electric field. Moreover, one part region of the HV N Well with excess holes become an extension of the P Body layer. In other words, this effect is the same as the “Kirk effect [28]-[29]” of the BJT and the extension region will reach the N+ drain region until the excess electrons concentration is less than the N+ drain doping concentration. As a result, the electrical field peak moves from the HV N Well/P Body junction to the N/N+ junction of the drain side, as shown in Fig. 2.5(b). This electric field peak leads the N/N+ junction avalanche breakdown and feedbacks additional hole current to the P Body.
The electric field of point A is large enough to trigger the impact ionization effect and the electric field of point B will enhance the ionization. Due to the avalanche multiplication occurred in the HV N Well/P Body junction, the voltage to sustain the junction breakdown is reduced, and then it snapbacks to low voltage and causes a negative slope after point A. Point C denotes the electric field peak reaches the N/N+ junction to cause the junction avalanche breakdown. Then, the feedback hole current will improve the multiplication effect in the HV N Well/P Body junction and snapback to low voltage again.
Compared to other structure of HV device, the HV NMOS with deeper N Well and N+
Buried Layer (NBL) can also have the double snapback characteristic, as shown in Fig. 2.6(a).
Due to the doping concentration of the NBL is higher than the N Well region, the breakdown
voltage is determined by the NBL/P Well junction and the first snapback is caused by the turn-on of BJT. After turn-on the BJT, the current flows vertically into the NBL region will result in a longer current path and the turn-on resistance will become larger. When the current further increases, the “Kirk effect” happens and the electric field peak moves from NBL/P Well junction to N Well/N+ junction. Then, the N Well/N+ junction will go into avalanche breakdown and increase the multiplication rate to snapback to lower holding voltage, as shown in Fig. 2.6(b). The current path of this HV structure will be changed from vertical path to lateral path and get a smaller turn-on resistance after the second snapback.
But not all HV devices have the double snapback characteristic [30], if the current path will not change, the second snapback characteristic will be not obvious or be no longer exist.
Figs. 2.7(a) and 2.7(b) show the HV device structure without the double snapback characteristic and its TLP I-V curve. The shallow N Grade region is to sustain the high breakdown voltage, before and after the N Grade/P Well junction breakdown, the current path is always in the lateral direction.
2.3 The Isolation Technique of High-Voltage Devices
There are two isolation techniques have been reported to reach the high breakdown voltage. The first isolation method is called the self isolation. It is mostly used in MOS technology and the source and drain junction isolate by itself under reverse bias, as shown in Fig. 2.8(a). In addition, the potential of source will be always grounded. The second isolation method is called the junction isolation, the device will be enclosed by the PN junction and the potential of source may be above ground potential, as shown in Fig. 2.8(b). With such kinds of isolation technique, the trigger voltage of the ESD protection device can be increased and resist the external noises.
(a) (b)
(c)
Fig. 2.1 Three kinds of layout patterns and its current flow path (a) The layout structure of the same side current flow, (b) The layout structure of the opposite side current flow, (b) The layout structure of the minimum metallization.
Fig. 2.2 The operation region of the power transistors.
(a) (b)
(c) (d)
Fig. 2.3 Four kinds cross-sectional views of power devices: (a) The VMOS device, (b) The VDMOS device, (c) The UMOS device, (d) The IGBT device.
(a) (b)
Fig. 2.4 (a) The LDMOS device, (b) The RESURF device.
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Fig. 2.5 (a) The three TLP I-V sampled points of LD-NMOS, (b) The electric field distribution versus the applied current.
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Fig. 2.6 (a) The device structure with double snapback characteristic of HV NMOS, (b) The TLP I-V curve of device structure with double snapback characteristic of HV NMOS.
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Fig. 2.7 (a) The device structure without double snapback characteristic of HV NMOS, (b) The TLP I-V curve of device structure without double snapback characteristic of HV NMOS.
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Fig. 2.8 (a) The self isolation structure, (b) The junction isolation structure.
CHAPTER 3
DEVICE PARAMETERS MODIFICATION FOR HIGH-VOLTAGE ESD PROTECTION DESIGN
The high-voltage (HV) ESD protection devices should be provided with a higher breakdown voltage than operation voltage to guarantee they won’t be triggered in normal circuit operation. The method of providing a higher breakdown voltage is usually through a low doped layer under the drain side. This chapter will introduce some HV devices that have been reported and present the experimental results of HV LD-NMOS, HV LD-PMOS, HV N-type Field Oxide Device (NFOD), HV Dual-Direction Silicon Controlled Rectifier (DD-SCR) and HV NMOS with embedded SCR (NSCR) in a 0.25μm 18V BCD technology.
3.1 The High-Voltage ESD Protection Devices
There are several high-voltage ESD protection devices that have been developed in different two processes. In the high-voltage (HV) process, a low doping layer is added in the drain and source sides named DDD-structure to increase the breakdown voltage. The ESD robustness of the asymmetric structure is better than symmetric structure in the HV process as described in chapter 1. The asymmetric structure means the DDD layer is added in the drain side. In the Bipolar-CMOS-DMOS (BCD) process [31]-[35], there are BJT, CMOS and DMOS to use in the high-voltage operation. In addition, the diode with high reverse breakdown voltage and high-voltage SCR are also available in these two processes.
3.1.1 The High-Voltage Bipolar Junction Transistor with Controllable Trigger and Holding Voltage
To provide effective whole-chip ESD protection, on-chip ESD protection devices are added in different parts of ICs. The required ESD specification of breakdown voltage, trigger
voltage and holding voltage in each part are different. So, this requires devices with high electrical flexibility to meet the different ESD specifications.
In the BCD process, the high-voltage bipolar junction transistor (HV BJT) with controllable trigger and holding voltage has been developed by well-adjusted layout parameter, as shown in Fig. 3.1 [36]. The holding voltage can be controlled by changing the
“d” spacing (the clearance between P Body edge and N+ emitter); the trigger voltage can be controlled by changing the “t” spacing (the distance between P Body and N Well), respectively.
In order to understand the physical mechanism of the influence on changing each layout parameter, to investigate the current flow, electrical field and the impact ionization in the
In order to understand the physical mechanism of the influence on changing each layout parameter, to investigate the current flow, electrical field and the impact ionization in the