Chapter 1 Introduction
1.2 Thesis Organization
This thesis presents our research results of RF MOSFET layout effect on low frequency noise and high frequency characteristics, with major purpose for RF and analog circuit applications. The main effect of our focus is the mechanical stress introduced from shallow trench isolation (STI), which increases with technology scaling and becomes dramatically significant in nanometer scale devices. In this thesis, three types of new MOSFET layout, namely narrow-OD, multi-OD, and donut devices are proposed to modulate the transverse stress from STI.
At first, an overview on low frequency noise theory and measurement methods is presented in chapter 2. Then, the layout dependence of STI stress and its effect on device parameters like drain current (IDS), transcondutance (Gm), and effective mobility (eff) are described in chapter 3. The proposed new MOSFETs with layouts of narrow-OD, multi-OD, and donut were fabricated in 90 nm low leakage CMOS process. An extensive device characterization has been carried out through I-V, C-V, S-parameters, and charge pumping (CP) current measurements. Note that the C-V characterization was performed based on S-parameters measurement, which can solve the problems of conventional C-V measurement, such as the parasitic capacitances from pads, interconnection lines, and substrate coupling and gate leakage induced abnormal C-V fall-off. However, one more parasitic capacitance arising from 3-D gate fringing effect cannot be removed from the open deembedding method implemented in S-parameters characterization. Thus, 3-D RLC simulator like Raphael was employed in this thesis to calculate the fringing capacitances contributed from gate sidewalls and finger ends.
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Based on the mentioned characterization techniques, STI top corner rounding (TCR) is identified as a key factor affecting I-V, Gm, gate capacitances, LFN, and high frequency performance, etc.
In chapter 4, MOSFET layouts effect on LFN will be presented, with a comprehensive characterization on all of the device structures such as standard multi-finger, narrow-OD, multi-OD, and donut MOSFETs, and covering both NMOS and PMOS. The layout effect can be examined through an extensive comparison between different device structures. Also, the interface trap density Nit extracted by CP method is taken as one of key parameters responsible for flicker noise, i.e. LFN under the condition that number fluctuation model is the dominant mechanism, tentatively for NMOS. Two more topics to be covered in chapter 4 are the body contact layouts effect and strain effect on LFN. In this study, totally five body contact layouts, such as multi-ring, U-shape, L-shape, parallel and perpendicular stripes are designed for an investigation on their effect on LFN. A review of strain effect will be classified as stress from strain engineering in 65nm high speed CMOS process and STI stress from new MOSFET layouts introduced in chapter 3. Chapter 5 will focus on MOSFET layout effect on high frequency characteristics, such as fT, fMAX, and RF noise parameters. An extensive characterization will cover different device structures and also the dependence of frequency and bias. Note that two-port or four-port deembedding is indispensable in high frequency characterization for parasitic RLC extraction and elimination, which is necessary for an accurate extraction of intrinsic device performance under high frequency operation. As for body contact layout effect, four-port test structure is required to accommodate 4-terminal MOSFETs with separate body terminal and a new body network model has been developed to simulate the body contact layout and body biases effects. In the end, chapter 6 concludes this thesis with a summary and suggestions for future work.
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Chapter 2
Low Frequency Noise Theory and Measurement Method
2.1 An Overview of CMOS Technology and Low Frequency Noise
It has been well known that noise exists as a fundamental problem in semiconductor devices and electronic circuits. In electronic devices, noise appears as random fluctuations in current or voltage around their DC level, due to fluctuations in carriers transport through the conduction channel. The impact from noise on the desired signal may cause failure of electronic circuits operation when the noise power becomes too large to keep sufficient signal to noise ratio (SNR). Furthermore, the mentioned problem becomes increasingly tough in miniaturized devices accompanied with supply voltage scaling and squeezed dynamic range.
Attributed to the nature of random fluctuations, noise is generally characterized by probability density function (PDF) based on multiple measurements over time. The time average of the measured noise currents or noise voltages approaches zero when integrated long enough and provides no useful information; instead, the square quantities namely power spectral density (PSD) is used to characterize noise. The PSD is measured with a spectrum analyzer or dynamic signal analyzer, which will be described in section 2.2.
The experimental indicates that the noise spectral density increases with decreasing frequency at lower frequencies and becomes white thereafter. The corner frequency between the frequency dependent noise and white noise is typically from few Hz up to MHz range and may vary with device types, device dimensions, and bias conditions, etc. The physical mechanism behind the white noise source is well known. However, the excess noise at low frequencies, namely low frequency noise (LFN) brings many questions with lot of debates and open up an interesting research area. Note that the LFN is also known as flicker noise or 1/f noise due to the fact that the frequency dependence sometimes approaches 1/f.
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The aggressive advancement of CMOS technology into nanoscale regime in recent five years has driven transistor gate delay to below 10 ps and intrinsic cut-off frequency (fT) well above 100 GHz [4]. According to International Technology Roadmap for Semiconductor (ITRS) [4], the demand on devices and interconnection lines scaling in the area of analog and RF is not as stringent as that for high speed logic CMOS. However, much more stringent criterion on the flicker noise at low frequencies (i.e., LFN) and thermal noise at high frequencies is required and specified for analog and RF circuit design, as shown in Table 2.1(a) and (b) for near term and long term, respectively [4]. The yellow blocks marked for 2011~2014 represent that the manufacturing solutions are known but not yet optimized.
Unfortunately, the red blocks marked for 2015 and thereafter highlight the problems for which the manufacturable solutions do not exist today. Obviously, the 1/f noise, i.e. LFN emerges as a big roadblock from 2015 and on. As compared with bipolar transistors, CMOS transistors generally suffer higher flicker noise (LFN), due to the nature of surface channel conduction.
As a result, the solutions to suppressing LFN become more challenging to CMOS technology, even though CMOS is superior in terms of scalability, high integration, low cost, and low standby power. To facilitate the extension of CMOS technology into RF and analog domain, an in-depth study on LFN in MOSFETs and its dependence on layouts and geometry scaling becomes critically important and is selected as one of research topics in this thesis. It has been recognized that LFN in transistors introduces particular problem in analog and RF circuits like voltage controlled oscillators (VCOs) and mixers. For VCOs, the LFN is upconverted to phase noise at small frequency offsets from the carrier frequency and then sets the ultimate separation limitation to two channels [5-8]. Fig. 2.1 illustrates schematically phase noise spectrum and different physical origins. As for mixers, the LFN originated from transistors may lead to severe degradation of SNR [9,10]. This can be understood if the signal is translated to very low frequency domain where the flicker noise may dominate and
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overwhelm the signal, particularly worse for low voltage operation. The impact from LFN on mixer may be relieved by using long channel transistors; however the penalty of to be paid is the degradation of transconductance and circuit speed.
Table 2.1(a) RF and Analog Mixed-Signal CMOS Technology Requirements – Near term [4]
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Table 2.1(b) RF and Analog Mixed-Signal CMOS Technology Requirements – Long term [4]
Fig.2.1 Schematical illustration of phase noise spectrum in VCO
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2.2 Low Frequency Noise Theory
In the past several decades, the origins and physical mechanisms underlying flicker noise remain an open question, with lot of debates and arguments in the experimental results and modeling to match the measurement. Number fluctuation model and mobility fluctuation model appear as two most popular mechanisms to explain and predict the measured flicker noise [11,12]. In 1957, McWhorter published a flicker noise model based on quantum mechanical tunneling transitions of electrons between the gate oxide and channel [11]. In practice, the tunneling time varies exponentially with distance, and it is assumed that trap density is uniform in both energy and distance from the channel interface to extract the time constants for generating flicker noise. The McWhorter model, namely number fluctuation model may be useful due to its simplicity and good agreement with experimental, particularly for n-channel MOSFETs [12,13]. However, the mobility fluctuation model appears to better explain the flicker noise measured from p-channel MOSFETs [14,15]. As compared to surface channel MOSFETs, buried-channel MOSFETs or bipolar junction transistors (BJT) demonstrate significantly lower flicker noise [16-21]. The published results are in favor of the number fluctuation model that the flicker noise is originated from the traps in the oxide or at oxide/channel interface. However, the surface carrier mobility is reduced compared to the bulk value due to additional surface scattering (acoustic phonon and surface roughness), which has an impact on the mobility fluctuation. Hooge mobility noise [22], which is sensitive to the crystalline quality, can be employed to explain the higher flicker noise for surface channel devices in which the carriers are in close proximity to the gate oxide and may suffer aggravated mobility fluctuation. In the following, the number fluctuation and mobility fluctuation models will be described in more detail.
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2.2.1 Number Fluctuation Theory [11]
The physical mechanism underlying the number fluctuation noise is the interaction between the channel carriers and slow traps in the gate oxide, which is illustrated in Fig. 2.2.
The dynamic exchange of carriers between the gate oxide and channel causes a fluctuation in the surface potential (S) and then gives rise to fluctuations in the inversion carrier density
Qinv. This in turn leads to noise in the drain current. Note that Qinv (the fluctuation in the inversion carrier density) can occur even without a current flowing the channel and the channel current is only used to sense the fluctuations. The mathematical formulas for expressing number fluctuation model in different operation regions are provided as follows In weak inversion region
-Nt the density of traps at quasi Fermi level
The frequency dependence with the exponent may deviate from 1 under the condition that the trap density Nt is not uniform in depth. For the case when the trap density near the gate oxide/channel interface is higher than that in the interior of the gate oxide, tends to be
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smaller than 1. For the opposite case, may become larger than 1. As for the bias dependence predict by the number fluctuation model, the normalized drain current noise SIDS/IDS2 varies with approximately as 1/IDS2 or 1/(VGS-VT)2 in strong inversion region given by (2.2)~(2.5) while is nearly independent of bias in weak inversion region, shown in (2.1). In this work, the LFN in terms of SIDS/IDS2 measured from n-channel MOSFETs just follows number fluctuation model and varied with IDS according to the relationship of 1/IDS2.
Fig.2.2 Schematical illustration of electrons in the channel of MOSFET moving in and out of the traps giving rising to fluctuations in the inversion carrier density and thereby the drain current.
2.2.2 Mobility Fluctuation Theory
Mobility fluctuation is another mechanism, which can contribute flicker noise. The mobility fluctuation model was first proposed by F.N. Hooge with an empirical formula given for the resistance fluctuation [23]. According to the Hooge empirical formula, the drain current noise generated by fluctuation in the channel carrier mobility can be written as (2.6).
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IDS H
DS inv
S q
I fWLQ
(2.6)
where H is a dimensionless parameter and referred as Hooge parameter. The typical values of
H range between 10-3 and 10-6 for surface channel transistors. H may be down to 10-7 for buried channel transistors like N+ gate pMOSFETs and even lower to the order of 10-8 for JFETs. Note that phonon scattering was proposed as the primary source generating mobility
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fluctuation noise [22]. The effective mobility eff of the channel carriers is determined by different scattering mechanisms, which vary in different ways with the effective normal field E⊥eff as a function of inversion carriers density QINV and body depletion charge QB. As a result,
H is not only dependent on technology but also on the bias conditions. In general, each scattering process generates mobility fluctuation noise with the amount given by each respective Hooge parameter, denoted as Hj. Assume the scattering processes are independent of each other and then Matthiessen’s rule can be applied as follows
1 1
eff j j
(2.7) The fluctuations in different scattering processes are assumed independent. Then the variation applied to (2.7) can lead toThe power spectral density can be derived as
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It can be understood from (2.11) that H varies with biases due to the bias dependent factor
eff /j
2. The total drain current noise is evaluated by adding the noise contribution from each channel segment derived for linear region as follows.2 2 0 2
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2
1 1
( )
IDS H H
DS ox GS T ox GT
S q q
I f WLC V V f WLC V
(2.13) The drain current noise contributed from mobility fluctuation as shown in (2.13) predicts that the larger H and shorter channel length (L) will lead to higher flicker noise whereas the wider channel width (W) and higher gate overdrive VGT can help reduce the flicker noise. The thinner gate oxide thickness is another beneficial factor, which can suppress flicker noise. In our experimental, the mobility fluctuation model can provide much better fit to the flicker noise measured from p-channel MOSFETs than number fluctuation model.
2.3 Low Frequency Noise Measurement System
Three flicker noise measurement systems with different equipment configurations are employed in this thesis for characterization of low frequency noise (LFN) in MOSFETs with different layouts. The conventional one is Celestry 9812B Noisepro system, which is supported by NDL and has been commonly used in transistor flicker noise characterization but limited to measurement using DC probes. The other two are new systems built up in our RF Lab. – one is SR570 system and the other one is model-5184 system. The major difference from Celestry 9812B is that these two LFN systems can support both RF and DC test structures, with RF GSG probes and DC probes, respectively. SR570 system shown in Fig.
2.3 is equipped with SR570 LNA (trans-resistances amplifier), Agilent DSA 35670 (dynamic signal analyzer), and HP4142B (DC power supply). The model-5184 LNA shown in Fig. 2.4 contains 5184 LNA (voltage amplifier), PA14A1 for ultra low noise DC source, low pass filter, Agilent 35670, and HP4142B. Note that Agilent ICCAP is adopted for measurement auto-control and data collection.
1) SR570 Low Frequency Noise Measurement System
Fig. 2.3 illustrates SR570 LFN measurement system in which the SR570 LNA was a
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trans-resistances amplifier produced by Stanford Research Systems. Essentially, LNA acts as a key element in this flicker noise measurement system through which it can provide the second stage low noise gain to reduce system noise and offer sufficiently large signal amplitude to dynamic signal analyzer (DSA) without increasing the undesired noises. In practice, the SR570 LNA can provide an offset current source at the DUT output (i.e., drain terminal of MOSFETs), which serves as an input to the amplifier. The DUT output current can be modulated by the low noise offset current source, so as not to drive the amplifier into saturation. The SR570 is also equipped with a filter with different options, such as low-pass, high –pass or bandpass filter. In our applications, we typically set bandpass filter to select the frequency range of our interest, i.e. 1 ~ 100k Hz. The HP4142B DC power supply was controlled by ICCAP to provide the gate bias for MOSFET through a low pass filter in order to remove the power supply’s noise within the frequency range of interest that is above 1Hz.
In other words, the supply voltage through the low pass filter is nearly a pure DC voltage source under the condition that the signal above 1Hz was removed by the low pass filter. The LNA output is connected to DSA, which can perform dynamic signal (V/ Hz) measurement and analysis. All the equipments such as 4142B, SR570 LNA, and Agilent DSA 35670 are integrated together and the measurement can be carried out through the control of ICCAP . Through a dynamic signal analysis done by DSA, we can obtain the measured noise from ICCAP. In general, we have to make a simple calculation to recover the original noise measured from DUT output stage. The measured noise is transformed to current spectrum density with a unit of A2/Hz.
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Fig.2.3 Schematic of SR570 flicker noise measurement system setup with SR570 LNA (trans-resistance amplifier), Agilent DSA 35670 (dynamic signal analyzer), and HP4142B (DC power supply)
Unfortunately, The measurement system adopting SR570 LNA has a stringent current limitation of 5 mA. For advanced multi-finger RF MOSFETs, which sometimes have large total width for sufficient current drivability and transconductance, this current limitation generally restricts the DUTs to limited operation conditions, such as linear or subthreshold regions. To solve the mentioned problem, we proposed a new system configuration by using model-5184 LNA to overcome the current limitation. Unlike SR570, model 5184 LNA is a kind of voltage amplifier with a separated output bias source. In the following, we will have a discussion on this new LFN measurement system.
2) New Configuration with Model 5184 LNA and ultra low noise DC source (PA14A1) An appropriate operation of SR570 LNA requires that the gain setting resistor should be lower than the output resistance of DUT (rout). As for the new solution using model 5184 LNA (voltage amplifier), the voltage gain and LNA noise are independent of the output resistance of DUT. In this way, the LNA noise is independent of the DUT and thus we can obtain a system noise level from measurement without DUT. The noise floor of the system can be pushed to 10-20 (V2/Hz), which is well below that of DUT in the frequency range of our interest. However, one major drawback of this voltage-mode LNA is that it does not include a
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DUT output biasing source, thus reducing the system integration level. Therefore, a reliable and ultra-low noise DC source at DUT output is required to minimize the extra noise contributed from the system. Battery is one of low noise sources, which can effectively reduce the noise generated from power supply. Besides the simple setup using batteries, we propose a new solution using an ultra low noise DC source (PA14A1) instead of batteries. A complete system configuration incorporating batteries or low noise DC source (PA14A1) is illustrated in Fig. 2.4. In practice, we implement on a PCB (printed circuit board) the metal lines in three paths for connecting LNA (model 5184), low noise source (PA14A1), and DUT drain terminal as shown in Fig. 2.5 (a) and (b).
In Fig.2.5(b), the ultra low noise DC source (PA14A1) was used. The advantage of using PA14A1 is that it can achieve the desired output voltage but a simple setup with batteries shown in Fig. 2.5(a) cannot meet the requirement.
In conclusion, we can obtain almost the same measurement results under the same bias condition by using SR570 LNA and model 5184 LNA either with batteries or PA14A1.
Besides the mentioned achievement, we have extended this work to 4-terminal MOSFET flicker noise measurement in both NMOS and PMOS.
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Fig.2.4 Schematic of low frequency noise measurement system consisting of model 5184 LNA (voltage amplifier), HP4142B for DC supply, and Agilent 35670 for dynamic
Fig.2.4 Schematic of low frequency noise measurement system consisting of model 5184 LNA (voltage amplifier), HP4142B for DC supply, and Agilent 35670 for dynamic