Open Deembedding Methods for Intrinsic C gg Extraction

在文檔中 射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路 (頁 60-71)

Chapter 3 Analysis of Layout Effect on STI Stress and Device Parameters

3.5 STI Top Corner Rounding (TCR) Technique – Stress and W

3.6.1 Open Deembedding Methods for Intrinsic C gg Extraction

In this thesis, two dummy open test structures, namely openM3 (open deembedding to M3) and openM1 (open deembedding to M1) illustrated in Fig. 3.15 are designed to investigate the differences and the final impact on eff extraction. Note that the gate capacitances after openM3 and openM1 deembedding are defined as Cgg(DUT,OM3) and Cgg(DUT,OM1) shown in (3.14) and (3.15).

( , 3 ) , ( 3) : ' 3

gg DUT OM gg mea gg OM gg

CCC DUT s C after openM deembedding (3.14)

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( , 1) , ( 1) : ' 1

gg DUT OM gg mea gg OM gg

CCC DUT s C after openM deembedding (3.15)

(a) (b)

Fig. 3.15 Layout of dummy open test structures for multi-finger MOSFETs (a) dummy openM3 for open deembedding to M3 (b) dummy openM1 for open deembedding to M1

Table 3.2 presents the gate capacitances measured from multi-finger MOSFET (Cgg,mea), dummy openM3 and dummy openM1 (Cgg(OM3) and Cgg(OM1)), and those after openM3 and openM1 deembedding, denoted as Cgg(DUT,OM3) and Cgg(DUT,OM1). Note that multi-finger MOSFETs with simultaneously varied WF and NF under fixed Wtot= WF×NF, i.e. W2N16, W1N32, and W05N64 as shown in Fig. 3.2 are adopted for this characterization and analysis.

The bias condition is fixed at |VDS|=0.05V and |VGS|=1.2V for NMOS and PMOS to enable a linear I-V characteristics appropriate for the proposed model (3.1)~(3.4) for eff extraction.

The results indicate that Cgg(OM3) measured from dummy openM3 is independent of the variation of NF whereas Cgg(OM1) measured from dummy openM1 increases with increasing NF. Moreover, Cgg(OM1) is apparently larger than Cgg(OM3) and the difference increases with NF. The difference between Cgg(OM1) and Cgg(OM3), denoted as Cgg(M1~M3) represents the parasitic capacitance from M3 through M2 and down to M1 and the dependence of NF comes from that associated with M2 and M1 following the multi-finger layout. Raphael simulation was performed to calculate the 3-D parasitic capacitances contributed from dummy openM3 and dummy openM1 as shown in Fig. 3.16 (a) and (b), respectively. Note that dummy openM1

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incorporates M3/M2/M1 stack layers in Fig. 3.16(b). Table 3.3 summarizes the difference

Cgg(M1~M3) between Cgg(DUT,OM3) and Cgg(DUT,OM1), which are extracted from openM3 and openM1 deembedding on multi-finger NMOS with NF=16 and 32 (W2N16, W1N32). The

Cgg(M1~M3) from measurement indicates a linear dependence on NF, and the difference divided by NF, namely Cgg0(M1~M3) keeps nearly a constant of 0.32 ± 0.1 fF/finger.

Furthermore, Cgg(M3) and Cgg(M1~M3) calculated by Raphael simulation for dummy openM3 and dummy openM1 (NF=1) achieve the difference Cgg0(M1~M3)=0.32 fF/finger. The good match between measurement and simulation proves the accuracy and the improvement of openM1 over openM3 deembedding. It is assumed that Cgg(DUT,OM1) extracted through openM1 deembedding should be the intrinsic gate capacitance, which is determined by Cox(inv) and total gate area Ag=NF×WF×Lg. For multi-finger MOSFETs with fixed Wtot=WF×NF, the intrinsic gate capacitances should be independent of NF and keep a constant under varying NF. To verify this point, Cgg(DUT,OM3) and Cgg(DUT,OM1) extracted from openM3 and openM1 deembedding are plotted versus NF, as shown in Fig. 3.17 (a) and (b). The results indicate that both Cgg(DUT,OM3) and Cgg(DUT,OM1) reveal a linear dependence on NF, but Cgg(DUT,OM1) vs. NF, presents much smaller slope than that of Cgg(DUT,OM3). The experimental with proven accuracy highlights that some other components of parasitic capacitance cannot be removed, even using openM1 deembeeding, i.e. the best one of existing methods for a clean deembedding.

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Table 3.2 Gate capacitances measured from multi-finger MOSFET (Cgg,mea), dummy open structures (Cgg(OM3), Cgg(OM1)), Cgg(DUT,OM3) and Cgg(DUT,OM1) after openM3 or openM1 deembedding

NMOS WF=2um

NF Cgg,mea (fF) Cgg(OM3) (fF) Cgg(DUT,OM3) (fF)

16 65.89 20.6 45.29

32 72.11 20.6 51.51

64 85.54 20.6 64.94

NMOS WF=2um

NF Cgg,mea (fF) Cgg(OM1) (fF) Cgg(DUT,OM1) (fF)

16 68.07 28.12 39.95

32 74.1 32.57 41.53

NMOS, VDS=0.05V, VGS=1.2V 2-port, open_M1 2-port, open_M3 NMOS, VDS=0.05V, VGS=1.2V

Table 3.3 Cgg(DUT,OM3) and Cgg(DUT,OM1), extracted from openM3 and openM1 deembedding on multi-finger NMOS with NF=16, 32. Cgg(M3) and Cgg(M1~M3) calculated by Raphael simulation for dummy openM3 and dummy openM1. A comparison of Cgg(M1~M3)=Cgg(DUT,OM3)- Cgg(DUT,OM1) from measurement and Cgg(M1~M3)=Cgg(M1~M3)-Cgg(M3) from simulation.

Simulation

NMOS finger numbers NF=1

Cgg Cgg(DUT,OMx) (fF) Cgg(DUT,OMx) (fF) Cgg(OMx) (fF)

openM3 45.29 51.51 0.126

openM1 39.95 41.53 0.446

Cgg(M1~M3) (fF) 5.34 9.98 0.32

Cgg0(M1~M3) (fF/finger) 0.334 0.312 0.32

Measurement NF=16 NF=32

(a) (b)

Fig. 3.16 3-D dummy open test structures for Raphael simulation (a) M3 only for openM3 (open deembedding to M3) (b) M3/M2/M1 stack for openM1 (open deembedding to M1)

44 openM1 deembedding on multi-finger NMOS (W2N16, W1N32, W05N64) with fixed WFNF

(a) Cgg(DUT,OM3) vs. NF : linear function '=0.4107 fF/finger, '=38.1 fF (b) Cgg(DUT,OM1) vs. NF :

=0.0988 fF/fingerr, =38.4 fF .

To explore the mechanism responsible for this new oberservation, a rigorous analysis was performed by using Raphael simulation and the results suggest that the parasitic capacitances lumped into Cgg,mea can be classified into two categories : one is contributed from from pads, interconnection lines, and substrate, and the other from gate sidewall and finger ends, namely Cof (sidewall fringing capacitance) and Cf(poly-end) (finger end fringing capacitance). The former one is a kind of extrinsic parasitic elements and can be removed through a dedicated open deembedding like openM1. As shown previously, openM1 can realize an open deembedding to the bottom metal, i.e. M1 to achieve a clean deembedding to the layers above poly gate. However, the latter one is actually a kind of intrinsic parasitic capacitance arising from the poly-gate fingers and the surrounding conductors like S/D diffusion regions and the contact plugs, and cannot be removed using any existing deembedding methods. To solve this problem, 3-dimensional capacitance simulation is performed using Raphael to calculate Cof and Cf(poly-end) as follows.

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3.6.2 3-D Fringing Capacitances Simulation and Analysis using Raphael [42]

In the following, 3-D Raphael simulation has been conducted to calculate the fringing capacitances from gate sidewall, i.e. Cof = Cg,Difff +Cg,CT and another component from gate finger ends, namely Cf(poly-end). Fig.3.18 illustrates a 3-D MOSFET structure for Raphael simulation. The 3-D structure incorporates four conducting regions, such as poly gate, channel region, source/drain diffusion region, and contact to source/drain region. The physical profiles of the dielectric layers between every two conductors can be referred to technology file in foundry PDK. As individual electrode is specified for each conducting region as mentioned, the three components of coupling capacitances from the gate to other three regions can be calculated. Among the three components, gate to channel region is the intrinsic gate capacitance responsible for Qinv and IDS, and the other two components, i.e. gate to S/D diffusion regions (Cg,Difff) and gate to contact (Cg,CT) constitute the sidewall fringing capacitance, given by Cof = Cg,Difff +Cg,CT . Fig. 3.19 (a) and (b) depict the structure of multi-finger MOSFETs in planar view and cross-sectional view, which were built in Raphael for 3-D fringing capacitances simulation.

Source diffusion Channel diffusion Drain diffusion

Contact Contact

Tox Poly gate

Fig.3.18 Schematical drawing of 3-D MOSFET structure for Raphael simulation. The 3-D structure incorporates four conducting regions, such as poly gate, channel region, source/drain diffusion region, and contact to source/drain

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(a) (b)

Fig.3.19 Multi-finger MOSFET structure built in Raphael for 3-D capacitance simulation (a) planar view (b) cross sectional view

Fig. 3.20(a)-(d) present Cg,CT, Cg,Diff, and Cof, calculated for MOSFETs with square contact corresponding to various geometry parameters, such as Lg, Lgct, Tg, and Tox over a wide range of variations. All of the parasitic capacitances indicate a weak dependence on Lg over a wide range of variation from 80 nm to 160 nm, shown in Fig. 3.20(a) and Cof keeps around 0.28fF/m. The results suggest that the gate sidewall fringing capacitances Cof = Cg,CT+Cg,Diff are not scalable with Lg and the impact on high frequency performance will go up with Lg scaling. For Lgct fixed at 140 nm on layout, according to 90 nm low leakage CMOS design rule, Cg,Diff dominates near 80% of the total parasitic capacitance Cof and Cg,CT contributes the remaining portion, i.e. around 20%. Fig. 3.20(b) presents the parasitic capacitances subject to varying Lgct. Interesting results are demonstrated with a significant dependence on Lgct that is in contrast with the weak dependence on Lg. Note that the increase of fringing capacitances with Lgct scaling highlights the impact from the inter-electrode space shrinkage in miniaturized devices on high frequency or high-speed circuit performance.

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Besides the sidewall fringing capacitances Cof, finger-end fringing capacitance, namely Cf(poly-end) is another element of the parasitic capacitances, which always exists in MOSFETs and cannot be removed by existing open deembedding methods. Again, Raphael simulation was employed to calculate Cf(poly-end), which is required to enable an accurate extraction of truly intrinsic gate capacitance (Cgg,int) and determination of W. Both Cof and Cf(poly-end) are not scalable with device scaling and may dominate intrinsic gate capacitance in miniaturized MOSFETs. As a result, Cof and Cf(poly-end) appear as key parameters to be known for an accurate extraction of eff in multi-finger MOSFETs with various layout dimensions. Fig. 3.21 illustrates the planar view of a multi-finger MOSFET in which three components of fringing capacitances, such as Cf(poly-end), Cg,Diff, and Cg,CT are depicted. This graphical analysis explains that the finger-end fringing capacitance is proportional to NF but is independent of WF and

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Wtot. On the other hand, the sidewall fringing capacitance is determined by both WF and NF and in a linear proportional to Wtot. For narrow-OD MOSFETs (Fig. 3.2) with simultaneously varied NF and WF under a specified Wtot= WF×NF, Cf(poly-end) will increase with increasing NF and its weighting factor increases dramatically in very narrow MOSFETs with large NF and small WF. According to 90 nm CMOS design rule, Cf(poly-end) is around 0.064 fF/finger from Raphael simulation.

Fig. 3.21 (a) Schematical illustration of multi-finger MOSFET layout (b) three components of fringing capacitances associated with each gate finger : Cf(poly-end) represents finger-end fringing capacitance, Cg,Diff, and Cg,CT are gate sidewall fringing capacitances.

Based on an extensive simulation and analysis on two categories of parasitic capacitances, the intrinsic gate capacitance extraction flow and analysis can be derived as follows. At first, Cgg(DUT,OM1) can be re-written as two parts, one of which is proportional to NF and another is independent of NF, given by (3.16)

( , 1) ( ) ( ) ( ) ( ( ) )

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F F tot

W NW (3.19) then Cgg(DUT,OM1) of multi-finger MOSFETs with various NF but fixed W NF FWtot can be expressed as a linear function of NF with the slope and intercept defined as  and  as follows

( , 1)

Note that the first term of the intercept  in (3.22) is the intrinsic gate capacitance (Cgg,intWtot), which contributes the inversion carriers QinvWtot responsible for channel current IDS in (3.1).

With Cof known from Raphael simulation, Cgg,int can be extracted from in (3.22). In fact, Cof

and Lg extracted from (3.23) and (3.24) should be self-consistent to validate the accuracy and it has been proven that Cof =0.28 fF/m and Lg =80 nm are the right ones to meet the target Cox(inv). Also, with Cof determined by Raphael simulation and Lg calculated by (3.24), W can be extracted from (3.21). The accurate extraction of Cof, Cox(inv), Lg, and W is pre-requisite to accurate determination of intrinsic gate capacitance Cgg,int, inversion carrier density Qinv, and effective mobility eff in intrinsic channel region.

Taking Cgg(M1~M3), which is proportional to NF and referring to (3.20)~(3.22) for that with openM1 deembedding, we can derive the expressions for that with openM3

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( , 3 ) ' '

gg DUT OM F

C N (3.26)

( ) ( ) 0( 1~ 3)

' ( W L Cg) ox inv Cf poly end Cgg M M

      (3.27)

( )

' (Cox invLg Cof)Wtot

  (3.28) The results derived for openM3 deembedding indicate that the intercept ’ for openM3 in (3.28) keeps the same as  for openM1 in (3.22) under a fixed Wtot; however, the slope ’ for openM3 in (3.27) appears larger than the slope  for openM1 in (3.21). In the following, , andW determined from multi-finger MOSFETs with openM1 deembedding, and (', ’) from those with openM3 deembedding will be presented for a comparison and verification on the proposed model.

Referring to Fig. 3.17(a) and (b) for Cgg(DUT,OM3) and Cgg(DUT,OM1) extracted by openM3 and openM1 deembedding. The results indeed demonstrate a linear relationship for both openM3 and openM1 deembedding, with nearly the same intercept, =38.1~38.4 fF but significant difference in the slope. The result validates the model for  given by (3.22)=(3.28), and provides a simple solution that the intrinsic gate capacitance Cgg,int defined as Cox(inv)Lg in (3.17) can be extracted from the slope no matter which kind of dummy open structures was used. The slope for openM1, given as =0.0988 fF/finger appears much smaller than that of openM3, '=0.4107 fF/finger. The experimental results just match the prediction from our proposed model and the difference between  and ' comes from Cgg(M1~M3), given by (3.21) and (3.27).

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3.6.3 Effective Mobility Extraction for MOSFETs with Various Layouts

在文檔中 射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路 (頁 60-71)