Chapter 3 Analysis of Layout Effect on STI Stress and Device Parameters
3.5 STI Top Corner Rounding (TCR) Technique – Stress and W
3.6.3 Effective Mobility Extraction for MOSFETs with Various Layouts
facilitate a thorough and precise extraction of 3-D parasitic capacitances and accurate determination of the intrinsic gate capacitance Cgg,int. Taking the developed characterization process with proven accuracy, the fundamental device parameters like Cox(inv), Lg, W, Cof, Cf(poly-end) can be determined with reliable accuracy for nanoscale MOSFETs. Table 3.4 summarizes the key parameters for multi-finger NMOS.
Table 3.4 Multi-finger MOSFET device parameters extracted from DC I-V and RF C-V characterization flow
Device types NMOS_W2N16_openM1
Bias condition Vds=0.05V, Vg=1.2V
NF 16
WF m 2
Lg m 0.08
Tox(inv) A 30
Cox(inv) fF/m2 11.51
fF/finger 0.0988
fF 38.37
Cof,sim fF/m 0.2812
Cf(polyend) fF/finger 0.0640
Cox(inv) =(/WFNF-Cof)/Lg fF/m2 11.47
Tox(inv)=0ox/Cox(inv) A 30.10
W=(-Cf(polyend))/(Cox(inv)*Lg) m 0.0379
In the following, the effective mobility eff can be extracted from linear I-V model (3.3)~(3.4) in which Weff and Qinv have been determined with proven accuracy for miniaturized MOSFETs with various layouts. In this approach, the layout dependent STI stress effect on eff can be determined with high precision due to the fact that all of the parasitic effects, such as W from STI TCR, gate related 3-D fringing capacitances, and pads/interconnection lines introduced parasitic capacitance have been taken into the
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characterization flow. Fig. 3.22 presents eff extracted from the group of narrow-OD NMOS, i.e. multi-finger NMOS with simultaneously varied WF and NF under fixed Wtot=WF×NF, (W2N16, W1N32, and W05N64), shown in Fig. 3.2. Note that VGT is taken to compensate VT variation from INWE. The results indicate a monotonical degradation trend in eff with finger width (WF=WOD) scaling from 2m to 0.5m and proves the impact from STI compressive
on electron mobility. Taking W2N16 as the reference, eff degradation in W1N32 is as small as 1.3% and that of W05N64 increases to around 6.8%. Referring to Gm versus VGT (Fig.
3.7(b)), Gm degradation in W1N32 and W05N64 just follows the same trend and suggests that
eff degradation is the dominant factor. As for multi-OD NMOS with an aggressive channel width scaling, eff versus VGT shown in Fig. 3.23 reveals substantially large degradation. For OD8 with WOD=0.25m, the eff appears 33.6% lower than OD1 and the eff degradation further increases to 37.3% for OD16 with WOD=0.125m.
0.1 0.2 0.3 0.4 0.5 0.6 0.7 50
100 150 200 250
Narrow-OD NMOS Vds=0.05V
eff extraction with W in Weff Qinv=Cgg,int*VGT
eff(cm2 /V-s)
W2N16 W1N32 W05N64
VGT (V)
Fig. 3.22 Effective mobility eff versus VGT for narrow-OD NMOS determined with consideration of W in Weff and Cgg,int for Qint. Narrow-OD NMOS : W1N32, W05N54, standard : W2N16. Linear operation condition : VDS=0.05V, VGT=VGS - VT.
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0.1 0.2 0.3 0.4 0.5 0.6 0.7 50
100 150 200 250
eff extraction with W in W
eff
Qinv=Cgg,int*VGT
Multi-OD NMOS Vds=0.05V
eff(cm2 /V-s)
OD1(W2N16) OD8
OD16
VGT (V)
Fig. 3.23 Effective mobility eff versus VGT for multi-OD NMOS determined with consideration of W in Weff and Cgg,int for Qint. Multi-OD NMOS : OD8 (WOD=0.25m), OD16 (WOD=0.125m), standard : OD1 (WOD=2m)W2N16. Linear operation condition : VDS=0.05V, VGT=VGS - VT.
In comparison with narrow-OD and multi-OD MOSFET with enhanced, donut MOSFETs were designed to verify another extreme case, that is the elimination of , along the direction of channel width. For NMOS shown in Fig. 3.24 (a), D1S1 suffer around 7.13%
degradation while D10S10 gain 10.03% enhancement in eff compared to the standard W2N16. The eff enhancement in D10S10 NMOS just match the original expectation that the elimination of compressive , can benefit electron mobility. As for eff degradation in D1S1 NMOS compared to W2N32, the increase of along the channel length, due to the minimal gate to STI edge space is considered the major cause responsible for electron mobility degradation. Regarding PMOS shown in Fig. 3.24 (b), both donut devices, i.e. D1S1 and D10S10 gain eff improvement over the reference W2N32. Interestingly, D1S1 PMOS can achieve 11.8% eff enhancement, which is obviously higher than 6.1% realized by D10S10 PMOS. The opposite trend w.r.t. NMOS in D1S1 layout can be explained by the mechanism that compressive stress along the channel length, i.e. can improve hole mobility but degrade electron mobility, as shown in Table 3.1. The experimental result proves that D1S1
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PMOS with the minimal gate to STI edge distance, resulting the highest compressive // and minimized ⊥ can benefit the most in hole mobility. Again, the layout dependence of eff is overdrive VGT is converted to an effective normal field Eeff according to the formulas (3.29) and (3.30) for NMOS and PMOS, respectively.
( ) universal mobility theory predicts that MOSFETs with various channel lengths, oxide thickness, and doping concentration should follow a universal curve when the effective mobility is expressed in the form of eff vs. Eeff [43]. It can be explained by the mechanism that variations in the mentioned device parameters are actually incorporated in the body
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charge and inversion carriers density (Qb and Qinv) and transformed into Eeff. However, the layout dependent stress is not the kind of parameter and may not impose its effect on eff via Eeff. The mentioned argument explains why the eff vs. Eeff for both narrow-OD and multi-OD NMOS with various WOD would not follow a universal curve. Similar results are achieved for donut NMOS and PMOS shown in Fig. 3.27. A comparison between donut MOSFETs and multi-finger MOSFETs with the same Wtot is illustrated in Fig. 3.28(a) and (b) for NMOS and PMOS, respectively. However, eff vs. Eeff indeed demonstrates three regions corresponding to three scattering mechanisms, such as coulomb scattering in low field, phonon scattering in
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Fig. 3.27 Effective mobility eff versus Eeff for donut MOSFET (D1S1, D10S10) determined with consideration of W in Weff and Cgg,int for Qint (a) NMOS : Eeff (VGT 2VT) / 6Tox inv( ) (b) PMOSEeff (VGT 3VT) / 9Tox inv( ).
57 mechanisms : coulomb scattering in low field, phonon scattering in medium field, and surface roughness scattering in high field.
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3.7 CP Current Measurement for Interface States Extraction and Analysis of STI Stress Effect
Charge pumping technique has been widely used to characterize interface state densities in MOSFETs [44,45]. In thin gate films, leakage current is relatively high due to quantum mechanical tunneling of carriers through the gate. As a result, the traditional technique of extracting interface traps density. Collecting simultaneous re high frequency C-V measurement data and comparing the difference can’t be used because the C-V is very hard to achieve at the leakage current level.
However, charge-pumping measurements can still be used to extract interface trap density, and the effect of gate leakage can be compensated for by measuring charge-pumping current at lower frequency and subtracting it from measurement results at higher frequencies.
Stress effect on interface traps is one of major concerns for deployment of stress engineering in the state-of-the-art process. In the form of localized interface-state generation, is a key reliability issue. In order to improve the understanding of the physical mechanism resulting in STI stress degradation, there is a great need for experimental results of variations in Si-SiO2 interface state density and distribution under the gate of the device.
In this work, the use of charge pumping to accurately measure Si-SiO2 interface trap density in four-terminal RF CMOS is described.
The charge pumping measurements are operated by Agilent 81110A signal generator, Keithley708A switch, and HP 4156 DC supply. Fig. 3.30 illustrates the experimental facilities of CP measurement for a cross-section MOSFET in 4T structure. The basic charge-pumping technique involves measuring the substrate current while applying voltage pulses of fixed amplitude, rise time, fall time, and frequency to the gate of the transistor, with the source, drain, and body tied to ground. The pulse also can be applied with fixed amplitude, voltage base sweep or a fixed base, variable amplitude sweep. Fig. 3.31 illustrates the pulse waveform
59
employed for the Elliot method in which the base level (Vbase) is swept from accumulation to inversion while keeping the pulse amplitude (Va) constant. Note that ICP,max can occur under the condition of Vbase< VFB and Vbase+Va= Vh > VT and the accuracy is justified with a clear plateau for ICP,max and a precise linear dependence on amplitude (Va) and frequency (not shown).
N+ N+
Bulk
Agilent 81110A Icp
Vr Vb Vbase
+ -+
--HP 4156
+ -+
--Keithley 708A
Fig.3.30 Schematic of experimental set-up of the charge pumping measurement applied to MOSFET with four terminals
Fixed amplitude and varying base level are obtained from an Agilent 81110A, which is connected to the gate terminal and varying the pulse base level from accumulation to inversion while keeping the amplitude of the pulse constant. Electrons captured in the traps in the inversion mode then recombined with holes in the accumulation mode. This electron-hole recombination process gave rise to a current flow from the substrate to the channel.
Recombination of charge through interface traps in the substrate results in the flow of charge pumping current in the bulk.
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Fig.3.31 CP pulse waveform : tr and tf are the rising and falling times, Vbase and Vh are swept from accumulation (Vbase <VFB) to inversion (Vh >VT), under fixed pulse amplitude Va=Vh-Vbase,
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Chapter 4
RF MOSFET Layout effect on Low Frequency Noise
4.1 Low Frequency Noise Analysis in Two-port 3T MOSFET
MOSFET layout effect on I-V, Gm, eff, and gate capacitance for Qinv, have been presented in chapter 3. The experimental results can be explained by the collective effects from layout dependent STI stress and W from STI TCR. Due to the fact that LFN is one of critical issues considered in RF and analog circuits design, MOSFET layout effect on LFN will be investigated and described in this chapter.
The multi-finger layout structure has been widely used for RF application to get better fMAX by minimizing the parasitic gate resistance (Rg) [46], but the inconsistent STI stress effect on device characteristics need to be more discussed, and the multi-finger device type is insufficient for analyzing. In this chapter, four kinds of layout, namely multi-finger, narrow-OD, multi-OD, and donut MOSFETs with the same total width are designed to investigate channel wdith (WOD) scaling effect on LFN. The STI stress might be highly considered, but on the other hand, the W due to STI TCR is increasingly important [47].
Thus it is essential to distinguish the W effect from the STI stress.
4.2 Narrow-OD MOSFET and Comparison with Standard MOSFET
The multi-finger structure with finger number NF=16, 32, and 64, finger width WF= 2, 1, and 0.5m respectively. The total width and channel length are fixed at 32um and 0.09um.
The he measured SID/IDS2 at frequency 50Hz are plotted versus IDS for narrow-OD devices under various VGT (0.1~ 0.7V).
The measurement result of narrow-OD for the STI stress mechanism analysis as shown in Fig. 4.1 The normalized drain current noise SID/IDS2 of the W2N16 and W1N32 devices are
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about 2 times higher than W05N64. The difference between W2N16 and W1N32 seems to be ignorable. The phenomena can be explained by the delta width effect overcome the STI stress on the performance for narrow-OD devices. The delta width effect dominated in the W05N64 LFN characteristic, but the delta width effect and STI stress effect are comparable in W1N32 LFN characteristic. From the above discussion, the compressive stress // effect is not obvious for NMOS narrow-OD device. But the influence of these two mechanisms (STI stress effect and delta width effect) is different in NMOS and PMOS, and this will be a further bias conditions, which indicates that number fluctuation model given by (4.1) is the dominant mechanism appears in NMOS LFN.
N the density of traps at quasi Fermi level
(4.1)
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4.3 Multi-OD MOSFET and Comparison with Standard MOSFET
The LFN in terms of SID/IDS2 for OD1 and OD16 NMOS in the frequency domain is shown in Fig. 4.3 The noise spectrum follows 1/f characteristics over a wide frequency domain from 4 to 10K Hz. It means that the measured LFN is a typical flicker noise. It is interesting to show that the OD16 gets lower SID/IDS2 than OD1 over a wide range of frequencies, although the interface trap density Nit of OD16 is higher than that of OD1.
101 102 103 104
64
To further analyze the mechanism responsible for LFN, the measured SID/IDS2 at frequency 50Hz are plotted versus IDS for both OD1 and OD16 NMOS under various VGT (0.1~ 0.7V) as shown in Fig. 4.4.
10
-410
-310
-210
-1210
-1110
-10VDS= 50mV, VGT= 0.1 ~ 0.7V
NMOS
W2N16_OD1 W2N16_OD16
S
ID/I
DS 2( 1 /H z )
Drain Current I
DS(A)
1/I2
DS
Fig.4.4 SID/IDS2
vs. IDS under varying |VGT| (0.1~0.7V) for NMOS multi-OD devices
Herein, the measured NMOS multi-OD SID/IDS2 also follows a function proportional to 1/IDS2 over the whole range of bias conditions, which indicates that number fluctuation model given by (4.1) is the dominant mechanism appears in NMOS LFN
Therefore, SID/IDS2 of NMOS is proportional to Nit/Weff and that predicts the decrease of LFN with increasing the effective width Weff. It is believed that the OD16 device suffers higher transverse compressive stress as well as interface traps Nit, which may aggravate the scattering effects and increase the flicker noise [50]. However, the larger Weff can eliminate these effects. The mentioned mechanism can explain why the OD16 devices can have the lower LFN as compared to OD1.
As for the LFN in terms of SID/IDS2 for PMOS OD1, OD8, and OD16 in the frequency domain is shown in Fig. 4.5 The devices are all with gate finger number at 16 and the poly width is 2um thus the total width is 32m.
65
101 102 103 104 105
10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8
Sid/Id2 (1/Hz)
Frequency (Hz) PMOS
VDS=-50mV, VGT=-0.5V
OD1
OD8 & OD16
Fig. 4.5 The low frequency noise SID/ID2
measured for the multi-OD devices, OD1, OD8, and OD16.
It is easy to show that the OD8 and OD16 have higher SID/IDS2 than OD1 over a wide range of frequencies, and the OD8 is nearly equal to OD16. SID/IDS2 of PMOS is tells that the OD16 device suffers the most critical mobility degradation. However, the larger Weff can eliminate these effects and thus the LFN of OD8 is very close to OD16. The mentioned Weff mechanism is exist in PMOS but the effect Weff cannot overcome the mobility degradation effect for PMOS multi-OD devices. The resulting STI stress and mobility degradation effect dominates over the delta width effect.
66
10-4 10-3 10-2
10-12 10-11 10-10 10-9 10-8
VDS= -50mV,
VGT= -0.1, -0.3, -0.5, -0.7V
PMOS
Standard OD8 OD16
S ID/I DS 2 (1/Hz)
Drain Current I
DS (A) 1/IDS
Fig.4.6 SID/IDS2
vs. IDS under varying |VGT| (0.1~0.7V) for PMOS multi-OD devices
4.4 Donut MOSFET and Comparison with Standard MOSFET
Fig. 4.7 (a) and (b) make a comparison of LFN in terms of SID/ID2 between the standard and donut devices for NMOS and PMOS, respectively. The noise spectrum follows 1/f characteristics over a wide frequency domain from 4 to 10K Hz. It means that the measured LFN is a typical flicker noise. The standard device reveals near twice larger SID/ID2 as compared to donut devices for both NMOS and PMOS, under a specified gate overdrive voltage, |VGT|= 0.7V. In contrast, the donut device D10S10 with the most extended gate to STI-edge distance indicates the lowest SID/ID2.
The results can be consistently explained by the fact that D10S10 can keep free from ⊥
as well as interface traps near STI edge, and the smallest // due to 10 times larger space away from the STI edge compared to D1S1.
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Fig.4.7 The low frequency noise SID/ID2 measured for the standard and donut devices (a) NMOS (b) PMOS: Standard (multi-finger W2N32), Donut D1S1, and D10S10.
To further explore the mechanism responsible for LFN, the measured SID/IDS2 at frequency 50Hz are plotted versus IDS for three different devices, under various |VGT| (0.1~ 0.7V) shown in Fig. 4.8 (a) and (b) for NMOS and PMOS, respectively. For NMOS devices, the measured LFN characteristic is dominated by number fluctuation model given by (4.1) in which SID/IDS2 is proportional to Nit/IDS2 and that predicts the increase of LFN with increasing the traps density Nit.
It is believed that the gate to STI-edge overlap region will suffer the most severe compressive strain as well as interface traps Nit [51], and the donut devices can eliminate these effects along the gate width, i.e. in the transverse direction. According to previous study, the stress generated traps may aggravate the scattering effect and increase the flicker noise.
The mentioned mechanism can explain why the donut devices free from gate to STI-edge overlap region can have the lowest LFN.
68 (a) NMOS (b) PMOS Standard : multi-finger W2N32, Donut, D1S1 and D10S10.
4.5 Comparison of LFN between NMOS and PMOS
LFN measurement was carried out using Celestry 9812B noise analyzer and Agilent 35670A dynamic signal analyzer. Noise data was collected under varying VGS in linear region (|VDS|=0.05V). According to LFN theory described in chapter 2, the normalized noise power spectral density (SID/IDS2) is taken to be an appropriate parameter for a comparison of LFN in various devices with different drain current IDS. Note that the comparison was made under frequency (<10 Hz) and the difference decreases at higher frequency. The results suggest that conventional design using PMOS in VCO for low phase noise is no longer valid. Two potential causes are proposed responsible for the higher LFN revealed in PMOS : one is
69
thicker Tox(inv) due to worse P+ poly gate depletion [48] and the other is lower eff for holes in PMOS than electrons in NMOS [49]. The first cause can be identified from the measurement that Cgg,DUT or Cgg,int of PMOS appears smaller than that of NMOS and Tox(inv) extracted from PMOS is around 3.2 nm, i.e. 0.2 nm thicker than that of NMOS. Referring to LFN models, described in chapter 2, the thicker Tox(inv), i.e. the lower Cox(inv) will lead to higher SID/IDS2. As for the second one, the lower eff may bring worse mobility fluctuation and higher LFN.
101 102 10-12
70
(WODxNOD =0.125mx16) : NMOS and PMOS, under |VGT|=0.3V and |VDS|=0.05V. multi-OD MOSFET : NF=16, WODxNOD =2 m
Fig. 4.10 (a) and (b) indicate SID/IDS2 measured from multi-OD MOSFETs OD8 and OD16, respectively. Again, NMOS and PMOS with the same multi-OD layout and under the same bias condition (|VGT| and |VDS|) are put in the plot to make a comparison. As can be seen, the noise level increases with increasing OD number for PMOS devices, over the entire drain current range. For the NMOS devices, the noise level get lower with increasing OD number.
This is due to the delta width effect is dominant in NMOS LFN characteristic. The difference between NMOS and PMOS become higher under this condition.
4.6 Layout Dependence of Interface States and Low Frequency Noise
The basic charge-pumping technique involves measuring the substrate current while applying voltage pulses of fixed amplitude, rise time, fall time, and frequency to the gate of the transistor, with the source, drain, and body tied to ground. The pulse can be applied with fixed amplitude, voltage base sweep or a fixed base, variable amplitude sweep. The rise time and fall time used in this research is 100nS. The gate is switched from inversion to accumulation and vice versa using an Agilent 81110A waveform generator. In inversion, some of the minority carriers pumped by the n+ terminal are trapped on the interface states. During the transition from inversion to accumulation, the mobile electrons of the inversion layer are collected by the n+ contact before the majority carriers, flowing from the p+ contact, reach the interface. Next, the recombination of the electrons trapped on the interface states with majority carriers gives rise to a net CP current Icp, measured with an HP 4146. The experiment is computer-controlled by Sagi software which offers multiple options and real-time parameter extraction.
Charge-pumping current measured as a function of base level as shown in Fig. 4.11 The
71
amplitude of the gate signal was changed from 1.5V to 1.7V. All experiments are very close indicates that no visible generation of maximum charge pumping current.
-2.0 -1.5 -1.0 -0.5 0.0 0
20 40 60 80 100
90nm NMOS W05N64 Va= 1.5V
Va= 1.6V Va= 1.7V
Icp(pA)
Vbase (V)
Tr=Tf= 100ns f= 1MHz Vr=Vb= 0V Start base= -2V Stop base= 0V
Fig.4.11 Comparison of measured charge pumping current with different pulse amplitude (Va)
Fig.4.11 Comparison of measured charge pumping current with different pulse amplitude (Va)