Multi-OD MOSFET and Comparison with Standard MOSFET1

在文檔中 射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路 (頁 83-0)

Chapter 3 Analysis of Layout Effect on STI Stress and Device Parameters

4.3 Multi-OD MOSFET and Comparison with Standard MOSFET1

The LFN in terms of SID/IDS2 for OD1 and OD16 NMOS in the frequency domain is shown in Fig. 4.3 The noise spectrum follows 1/f characteristics over a wide frequency domain from 4 to 10K Hz. It means that the measured LFN is a typical flicker noise. It is interesting to show that the OD16 gets lower SID/IDS2 than OD1 over a wide range of frequencies, although the interface trap density Nit of OD16 is higher than that of OD1.

101 102 103 104

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To further analyze the mechanism responsible for LFN, the measured SID/IDS2 at frequency 50Hz are plotted versus IDS for both OD1 and OD16 NMOS under various VGT (0.1~ 0.7V) as shown in Fig. 4.4.

10

-4

10

-3

10

-2

10

-12

10

-11

10

-10

VDS= 50mV, VGT= 0.1 ~ 0.7V

NMOS

W2N16_OD1 W2N16_OD16

S

ID

/I

DS 2

( 1 /H z )

Drain Current I

DS

(A)

1/I2

DS

Fig.4.4 SID/IDS2

vs. IDS under varying |VGT| (0.1~0.7V) for NMOS multi-OD devices

Herein, the measured NMOS multi-OD SID/IDS2 also follows a function proportional to 1/IDS2 over the whole range of bias conditions, which indicates that number fluctuation model given by (4.1) is the dominant mechanism appears in NMOS LFN

Therefore, SID/IDS2 of NMOS is proportional to Nit/Weff and that predicts the decrease of LFN with increasing the effective width Weff. It is believed that the OD16 device suffers higher transverse compressive stress as well as interface traps Nit, which may aggravate the scattering effects and increase the flicker noise [50]. However, the larger Weff can eliminate these effects. The mentioned mechanism can explain why the OD16 devices can have the lower LFN as compared to OD1.

As for the LFN in terms of SID/IDS2 for PMOS OD1, OD8, and OD16 in the frequency domain is shown in Fig. 4.5 The devices are all with gate finger number at 16 and the poly width is 2um thus the total width is 32m.

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101 102 103 104 105

10-15 10-14 10-13 10-12 10-11 10-10 10-9 10-8

Sid/Id2 (1/Hz)

Frequency (Hz) PMOS

VDS=-50mV, VGT=-0.5V

OD1

OD8 & OD16

Fig. 4.5 The low frequency noise SID/ID2

measured for the multi-OD devices, OD1, OD8, and OD16.

It is easy to show that the OD8 and OD16 have higher SID/IDS2 than OD1 over a wide range of frequencies, and the OD8 is nearly equal to OD16. SID/IDS2 of PMOS is tells that the OD16 device suffers the most critical mobility degradation. However, the larger Weff can eliminate these effects and thus the LFN of OD8 is very close to OD16. The mentioned Weff mechanism is exist in PMOS but the effect Weff cannot overcome the mobility degradation effect for PMOS multi-OD devices. The resulting STI stress and mobility degradation effect dominates over the delta width effect.

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10-4 10-3 10-2

10-12 10-11 10-10 10-9 10-8

VDS= -50mV,

VGT= -0.1, -0.3, -0.5, -0.7V

PMOS

Standard OD8 OD16

S ID/I DS 2 (1/Hz)

Drain Current I

DS (A) 1/IDS

Fig.4.6 SID/IDS2

vs. IDS under varying |VGT| (0.1~0.7V) for PMOS multi-OD devices

4.4 Donut MOSFET and Comparison with Standard MOSFET

Fig. 4.7 (a) and (b) make a comparison of LFN in terms of SID/ID2 between the standard and donut devices for NMOS and PMOS, respectively. The noise spectrum follows 1/f characteristics over a wide frequency domain from 4 to 10K Hz. It means that the measured LFN is a typical flicker noise. The standard device reveals near twice larger SID/ID2 as compared to donut devices for both NMOS and PMOS, under a specified gate overdrive voltage, |VGT|= 0.7V. In contrast, the donut device D10S10 with the most extended gate to STI-edge distance indicates the lowest SID/ID2.

The results can be consistently explained by the fact that D10S10 can keep free from ⊥

as well as interface traps near STI edge, and the smallest // due to 10 times larger space away from the STI edge compared to D1S1.

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Fig.4.7 The low frequency noise SID/ID2 measured for the standard and donut devices (a) NMOS (b) PMOS: Standard (multi-finger W2N32), Donut D1S1, and D10S10.

To further explore the mechanism responsible for LFN, the measured SID/IDS2 at frequency 50Hz are plotted versus IDS for three different devices, under various |VGT| (0.1~ 0.7V) shown in Fig. 4.8 (a) and (b) for NMOS and PMOS, respectively. For NMOS devices, the measured LFN characteristic is dominated by number fluctuation model given by (4.1) in which SID/IDS2 is proportional to Nit/IDS2 and that predicts the increase of LFN with increasing the traps density Nit.

It is believed that the gate to STI-edge overlap region will suffer the most severe compressive strain as well as interface traps Nit [51], and the donut devices can eliminate these effects along the gate width, i.e. in the transverse direction. According to previous study, the stress generated traps may aggravate the scattering effect and increase the flicker noise.

The mentioned mechanism can explain why the donut devices free from gate to STI-edge overlap region can have the lowest LFN.

68 (a) NMOS (b) PMOS Standard : multi-finger W2N32, Donut, D1S1 and D10S10.

4.5 Comparison of LFN between NMOS and PMOS

LFN measurement was carried out using Celestry 9812B noise analyzer and Agilent 35670A dynamic signal analyzer. Noise data was collected under varying VGS in linear region (|VDS|=0.05V). According to LFN theory described in chapter 2, the normalized noise power spectral density (SID/IDS2) is taken to be an appropriate parameter for a comparison of LFN in various devices with different drain current IDS. Note that the comparison was made under frequency (<10 Hz) and the difference decreases at higher frequency. The results suggest that conventional design using PMOS in VCO for low phase noise is no longer valid. Two potential causes are proposed responsible for the higher LFN revealed in PMOS : one is

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thicker Tox(inv) due to worse P+ poly gate depletion [48] and the other is lower eff for holes in PMOS than electrons in NMOS [49]. The first cause can be identified from the measurement that Cgg,DUT or Cgg,int of PMOS appears smaller than that of NMOS and Tox(inv) extracted from PMOS is around 3.2 nm, i.e. 0.2 nm thicker than that of NMOS. Referring to LFN models, described in chapter 2, the thicker Tox(inv), i.e. the lower Cox(inv) will lead to higher SID/IDS2. As for the second one, the lower eff may bring worse mobility fluctuation and higher LFN.

101 102 10-12

70

(WODxNOD =0.125mx16) : NMOS and PMOS, under |VGT|=0.3V and |VDS|=0.05V. multi-OD MOSFET : NF=16, WODxNOD =2 m

Fig. 4.10 (a) and (b) indicate SID/IDS2 measured from multi-OD MOSFETs OD8 and OD16, respectively. Again, NMOS and PMOS with the same multi-OD layout and under the same bias condition (|VGT| and |VDS|) are put in the plot to make a comparison. As can be seen, the noise level increases with increasing OD number for PMOS devices, over the entire drain current range. For the NMOS devices, the noise level get lower with increasing OD number.

This is due to the delta width effect is dominant in NMOS LFN characteristic. The difference between NMOS and PMOS become higher under this condition.

4.6 Layout Dependence of Interface States and Low Frequency Noise

The basic charge-pumping technique involves measuring the substrate current while applying voltage pulses of fixed amplitude, rise time, fall time, and frequency to the gate of the transistor, with the source, drain, and body tied to ground. The pulse can be applied with fixed amplitude, voltage base sweep or a fixed base, variable amplitude sweep. The rise time and fall time used in this research is 100nS. The gate is switched from inversion to accumulation and vice versa using an Agilent 81110A waveform generator. In inversion, some of the minority carriers pumped by the n+ terminal are trapped on the interface states. During the transition from inversion to accumulation, the mobile electrons of the inversion layer are collected by the n+ contact before the majority carriers, flowing from the p+ contact, reach the interface. Next, the recombination of the electrons trapped on the interface states with majority carriers gives rise to a net CP current Icp, measured with an HP 4146. The experiment is computer-controlled by Sagi software which offers multiple options and real-time parameter extraction.

Charge-pumping current measured as a function of base level as shown in Fig. 4.11 The

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amplitude of the gate signal was changed from 1.5V to 1.7V. All experiments are very close indicates that no visible generation of maximum charge pumping current.

-2.0 -1.5 -1.0 -0.5 0.0 0

20 40 60 80 100

90nm NMOS W05N64 Va= 1.5V

Va= 1.6V Va= 1.7V

Icp(pA)

Vbase (V)

Tr=Tf= 100ns f= 1MHz Vr=Vb= 0V Start base= -2V Stop base= 0V

Fig.4.11 Comparison of measured charge pumping current with different pulse amplitude (Va)

Fig. 4.11 indicate the interface trap density Nit over the energy levels swept through the Fermi level, which is calculated from the base-level CP current for multi-OD devices as shown in (4.2).

_ max

cp eff it

I qfW LN (4.2) Where f is the frequency of applied pulse, and Weff L is the device area. According to (4.2), Icp_max is proportional to Nit and Nit can be extracted from the Icp under specified f and device dimension Weff L.

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Standard and Multi-OD MOSFET Nit Analysis

-1.2 -1.0 -0.8 -0.6 -0.4

30 40 50 60 70 80 90 100 110 120

90nm NMOS W2N32 OD16

Icp(pA)

Vbase (V) Tr=Tf= 100ns

f= 500kHz

Vr=Vb= 0V, Va=1.7V

Fig. 4.12 Charge pumping current measurement of standard and multi OD device

Fig. 4.12 presents ICP vs. Vbase for W2N32 (standard multi-finger) and OD16 (multi-OD) NMOS. The measurement was repeated for different devices layouts and the extracted trap densities are summarized. A statistical drawing of the data in is shown in Fig. 4.13. It is noted that Wtotal is used to reflect the W effect. In Fig. 4.13, it is found that the compressive stress may introduce additional interface traps in OD16 devices. However, the normalized difference of Nit between OD1 and OD16, denoted as Nit(OD16,OD1))/ Nit(OD1) decreases from 55% to 10%

due to the DW effect. This implies that for the multi-OD devices are affected by DW effect significantly, as well as low frequency noise.

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10 12 14 16 18 20 22 24

N

it

= I

cp

/ qfWL

N it ( 1 0 1 0 * c m -2 )

OD1 OD16 OD1 OD16 N

it

= I

cp

/ qfW

eff

L

Fig.4.13 Interface trap density Nit of OD1 and OD16 devices extracted by using Weff and W, measured at VD=VS= VB= 0V and Va = 1.7V.

Standard and Narrow-OD MOSFET Nit Analysis

As shown in Fig. 4.14, it is found that the charge pumping current is found to be the smallest for W05N64 compared to the W2N16. To confirm that the W05N64 has more interface traps than W2N16, stable and repeatable measurement should be taken statistically that only a slight fluctuation of data among devices is acceptable. However, the difference of each die (~37%) is much larger than device variation ( ~16%) which is shown in Fig. 4.15.

The layout effect of narrow OD device on interface trap density remain in discussion here.

This has to be devoted to explore the details in the trend for the LFN with narrow-OD devices.

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Fig. 4.14 Charge pumping current of three narrow OD devices, and maximum charge pumping current comparison among each measurement die

W2N16 W1N32 W05N64

4.7 Low Frequency Noise Model Parameter Extraction for Simulation

As for doughnut PMOS shown in Fig.4.8 (b), the measured SID/IDS2 follows a simple power law of 1/IDS and manifests itself governed by mobility fluctuation model, according to Hooge empirical formula expressed in. Note that the Hooge’s parameter αH is dimensionless

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and may vary with biases and process technologies. The reduction of LFN measured from donut PMOS suggests the suppression of mobility fluctuation due to the eliminated compressive .

 

2

2

1 :

H eff DS ID

DS DS

H

S qV

I f L I

the Hooge parameter

(4.3)

0.2 0.4 0.6

10-4 10-3

Standard D1S1 D10S10 pMOS

VDS= -50mV

Hooge parameter, H

|VGT| (V)

Fig. 4.16 Hooge’s parameter versus gate-over-drive voltage |VGT| for standard and doughnut devices biased at |VGT|= 0.1~0.7V

Hooge’s parameter is a figure of merit for low frequency noise comparison between 10-7 and 10-3. Fig. 4.16 shows the extracted Hooge’s parameter versus |VGT| from the mean value of several PMOS devices. The standard device shows larger H than the doughnut devices. It is explained that the larger enhancement in the surface roughness mobility results in the more phonon scattering limited mobility for standard devices and thus the higher Hooge’s parameter can be attributed to lower channel mobility.

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Chapter 5

RF MOSFET Layout Effect on High Frequency Characteristics

5.1 Two-port S-parameters Measurement and Deembedding

2-port network parameters can be explained most easily by considering a network with only two ports [63], an input port and an output port, like the network shown in Fig. 5.1

+

To characterize the performance of such a network, any of several parameter sets can be used, each of which has certain advantages. Each parameter set is related to a set of four variables associated with the two-port model. Two of these variables represent the excitation of the network, and the remaining two represent the response of the network to the excitation.

If the network of Fig. 5.1 is excited by voltage sources V1 and V2, the network currents I1 and been described, as before, by two linear equations similar to equations (5.1), except that the variables and the parameters describing their relationships would be different. However, all parameter sets contain the same information about a network, and it is always possible to calculate any set in terms of any other set.

Scattering parameters, which are commonly referred to as s-parameters, are a parameter

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set that relates to the traveling waves that are scattered or reflected when a 2-port network is inserted into a transmission line. Another important advantage of s-parameters stems from the fact that traveling waves, unlike terminal voltages and currents, do not vary in magnitude at points along a lossless transmission line. This means that scattering parameters can be measured on a device located at some distance from the measurement transducers, provided that the measuring device and the transducers are connected by low-loss transmission lines.

Following the bias conditions and dc characterization, S-parameters were measured by using HP8510C vector network analyzer from 0.5GHz up to 40 GHz, and the DC supply is HP 4142. A valid calibration needs to be performed prior to the S-parameter measurement, which requires SOLT (Short, open, load, through) calibrations between the two ports of pad and SMA.

Open and short de-embedding are done on the measured two port S-parameters to extract the intrinsic ac characteristics in terms of Y-parameters for C-V model parameter extraction[64] and H-parameters for determination. Z-parameters and Y-parameter of the intrinsic MOSFETs were obtained from S-parameters after de-embedding and used to extract the resistance and such as Rg, Rs, Rd [64]. The intrinsic MOSFET incorporating the parasitic, as extracted was adopted by ADS simulation to do I-V and C-V model parameter extraction and optimization simultaneously. The accuracy of intrinsic MOSFET model has been extensively verified and validated by good match with the measurement.

5.2 Two-port 3T MOSFET with Multi-finger, Multi-OD, and Donut Structures

Test structures were fabricated using 90nm RFCMOS process technology, all devices are designed to 2-port test-key with GSG pads for High frequency measurement. Multi-finger structure with finger number NF=16, 32, and 64, finger width WF= 2, 1, and 0.5, the total width and channel length are fixed at 32um and 0.09um. Another set of multi-finger type with

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NF=32, 64, and 128, finger width= 2, 1, and 0.5, the total width and channel length are fixed at 64um and 0.09um, respectively. The multi-OD device with gate finger number NF= 16, finger width WF= 2, 0.25, 0.125um and OD number NOD= 1, 8, 16 accordingly with fixed OD space 0.2m. Doughnut devices with two layout dimensions D1S1 and D10S10 are also characterized here. D1S1 represents donut MOSFET in which the space from poly gate to STI edge follows the minimum rule, and D10S10 denotes donut MOSFET with 10 times larger space between poly gate and STI edge.

The parameters in equivalent circuit would be extracted and discussed in the following chapters. De-embedding method and parameter extraction are major subjects and small signal equivalent circuit model constructed by extracted parameters would be verified by using Agilent Advanced Design System (ADS) simulator to make the parameter extraction method and extracted parameters solider.

5.2.1 Intrinsic Device and Parasitic RLC Parameters Extraction and Analysis – Layout Effect and Bias dependence

The intrinsic gate resistance obtained by Y-method of standard and doughnut were extracted at VDS= 1.2V and VGS= 1V are plotted in Fig. 5.2 From the extracted Rg at various frequencies, we can find easily it is frequency independent and does not appear non-quasi-static (NQS) effect because of sufficient high frequency and short channel.

0 5 10 15 20 25 30 35 40 45

0 50 100 150 200 250 300

350 90nm W2N32 NMOS

VDS=1.2V, VGS=1V Std

D1S1 D10S10

Rg (Ohm)

Frequency (Ghz)

Fig. 5.2 The extracted Rg of standard and doughnut devices as a function of frequency with

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VDS= 1.2V, VGS= 1V

Fig. 5.3 and Fig. 5.4 shows the extracted Rg for NMOS and PMOS with standard and doughnut devices at saturation region. We can see Rg shows very weak gate bias dependence for short channel devices. Based on above results, we can see there is no different between Y-method and Z-method extracting results, and thus we can confirm the exact value of poly gate resistance for different test patterns.

0.8 0.9 1.0 1.1 1.2

Fig. 5.3 Comparison of (a) Z-method and (b) Y-method Rg extraction for NMOS standard and doughnut devices

Fig. 5.4 Comparison of (a) Z method and (b) Y method Rg extraction for PMOS standard and doughnut device

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Table. 5.1, table. 5.2, and table. 5.3 is the parameter values which are for the gate resistance optimization of Z-method. The calculated Ag and B are mainly from the parameter gds, Cgg, Cgd, Cgs, gm, and Cds. The used devices are standard multi-finger W2N32, D1S1, and D10S10, including N type and P type MOSFETs.

Table. 5.1 The optimized parameters (Ag and B) for Z method Rg extraction of standard W2N32 device

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz 0.8 3.38E-03 7.68E-14 2.49E-14 5.19E-14 4.26E-02 1.89E-14 ####### ####### 7.07 0.9 4.06E-03 7.87E-14 2.51E-14 5.36E-14 4.68E-02 1.79E-14 ####### ####### 5.74 1 4.63E-03 8.00E-14 2.53E-14 5.47E-14 4.87E-02 1.72E-14 ####### ####### 4.85 1.1 5.15E-03 8.10E-14 2.56E-14 5.54E-14 4.92E-02 1.67E-14 ####### ####### 4.17 1.2 5.65E-03 8.17E-14 2.59E-14 5.58E-14 4.89E-02 1.63E-14 ####### ####### 3.59 Average 5.08 NMOS standard W2N32 bias dependent with vary Vgs (Vds=1.2V)

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz -0.8 3.84E-03 7.16E-14 2.39E-14 4.78E-14 1.60E-02 2.77E-14 4.42E+22 6.34E+23 5.91 -0.9 4.37E-03 7.28E-14 2.43E-14 4.86E-14 1.84E-02 2.78E-14 5.70E+22 7.07E+23 5.88 -1 4.88E-03 7.39E-14 2.47E-14 4.92E-14 2.01E-02 2.81E-14 6.78E+22 7.40E+23 5.65 -1.1 5.45E-03 7.47E-14 2.52E-14 4.95E-14 2.13E-02 2.81E-14 7.96E+22 7.40E+23 5.19 -1.2 5.96E-03 7.56E-14 2.58E-14 4.98E-14 2.21E-02 2.81E-14 8.96E+22 7.20E+23 4.71 Average 5.47 PMOS standard W2N32 bias dependent with vary Vgs (Vds= -1.2V)

Table. 5.2 The optimized parameters (Ag and B) for Z method Rg extraction of doughnut D1S1 device

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz 0.8 3.11E-03 7.73E-14 2.15E-14 5.57E-14 4.26E-02 2.58E-14 1.31E+23 1.96E+24 10.06 0.9 3.75E-03 7.93E-14 2.17E-14 5.76E-14 4.68E-02 2.48E-14 1.67E+23 1.98E+24 8.62

1 4.31E-03 8.05E-14 2.19E-14 5.85E-14 4.87E-02 2.42E-14 1.92E+23 1.95E+24 7.65 1.1 4.81E-03 8.15E-14 2.22E-14 5.93E-14 4.92E-02 2.36E-14 2.10E+23 1.85E+24 6.79 1.2 5.30E-03 8.22E-14 2.26E-14 5.96E-14 4.89E-02 2.33E-14 2.23E+23 1.75E+24 6.11 Average 7.85 NMOS doughnut D1S1 bias dependent with vary Vgs (Vds=1.2V)

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Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (S) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz -0.8 3.85E-03 7.06E-14 2.34E-14 4.72E-14 1.69E-02 2.67E-14 4.98E+22 7.06E+23 6.25 -0.9 4.27E-03 7.22E-14 2.38E-14 4.84E-14 1.97E-02 2.69E-14 6.31E+22 8.04E+23 6.37 -1 4.66E-03 7.34E-14 2.43E-14 4.92E-14 2.16E-02 2.72E-14 7.37E+22 8.53E+23 6.23 -1.1 5.05E-03 7.44E-14 2.48E-14 4.96E-14 2.30E-02 2.74E-14 8.38E+22 8.81E+23 6 -1.2 5.44E-03 7.51E-14 2.53E-14 4.98E-14 2.39E-02 2.75E-14 9.28E+22 8.84E+23 5.67

Average 6.1 PMOS doughnut D1S1 bias dependent with vary Vgs (Vds= -1.2V)

Table. 5.3 The optimized parameters (Ag and B) for Z method Rg extraction of doughnut D10S10 device

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm (A/V) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz 0.8 2.83E-03 7.82E-14 2.49E-14 5.33E-14 4.75E-02 3.33E-14 1.28E+23 2.31E+24 12.09 0.9 3.50E-03 7.99E-14 2.51E-14 5.48E-14 5.12E-02 3.27E-14 1.54E+23 2.34E+24 10.78 1 4.07E-03 8.10E-14 2.54E-14 5.56E-14 5.27E-02 3.21E-14 1.73E+23 2.31E+24 9.8 1.1 4.58E-03 8.18E-14 2.57E-14 5.61E-14 5.29E-02 3.14E-14 1.87E+23 2.24E+24 8.97 1.2 5.08E-03 8.25E-14 2.60E-14 5.65E-14 5.23E-02 3.07E-14 1.98E+23 2.14E+24 8.21 Average 9.97 NMOS doughnut D10S10 bias dependent with vary Vgs (Vds=1.2V)

Vgs gds (S) Cgg (F) Cgd (F) Cgs (F) gm

(A/V) Cds (F) B Ag

Ag/(w^2 +B ), f=40GHz -0.8 2.98E-03 7.12E-14 2.32E-14 4.80E-14 1.69E-02 3.22E-14 3.15E+22 8.02E+23 8.48 -0.9 3.65E-03 7.26E-14 2.36E-14 4.90E-14 1.94E-02 3.11E-14 4.48E+22 8.59E+23 7.96 -1 4.28E-03 7.36E-14 2.41E-14 4.95E-14 2.13E-02 3.01E-14 5.91E+22 8.91E+23 7.29 -1.1 4.90E-03 7.46E-14 2.47E-14 4.99E-14 2.26E-02 2.93E-14 7.30E+22 8.83E+23 6.49 -1.2 5.52E-03 7.54E-14 2.53E-14 5.01E-14 2.34E-02 2.87E-14 8.63E+22 8.49E+23 5.68 Average 7.18 PMOS doughnut D10S10 bias dependent with vary Vgs (Vds= -1.2V)

Narrow-OD Rg with Z-method and Y-method were extracted and plotted as a function gate bias, as shown in Fig. 5.5 that were obtained by the two methods are compared. Similar values were obtained for W2N16, which has the minimum finger number here. But for the W1N32 and W05N64, a slight difference between Z-method and Y-method. The lowering of Rg by Y-method attribute to the term in the denominator of 2

11 11

Re(Y )/Im(Y ) , this capacitive components become higher due to the poly gate to metal coupling introduced by poly gate to metal coupling capacitance, which is not clean enough for open metal3 de-embedding result.

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And this can be improved by applying metal1 de-embedding but will be at a significantly cost of chip area

Fig. 5.5 Comparison of (a) Z method and (b) Y method Rg extraction for NMOS narrow-OD device

As discussed before, the Rg lowering effect is fine and acceptable for narrow-OD devices with Y-parameter. But for multi-OD with even larger extrinsic parasitic capacitance, the Rg is dramatically different between there two method. Multi-OD Rg with Z-method and Y-method were extracted and plotted as a function gate bias, as shown in Fig. 5.6 that were obtained by the two methods are compared. Similar values were obtained for OD1 and OD8, which has nearly the same poly width here. But for OD16, a significant difference between Z-method and Y-method occurs and a totally different trends. The Y-method Rg of OD16 even lower than OD1. Same as narrow-OD devices, the lowering of Rg by Y-method attribute to the term in the denominator of 2

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the comparison result that the Z-parameter is suitable and more accurate than Y-parameter in most of the conditions and test patterns.

0.8 1.0 1.2

Fig. 5.6 Comparison of (a) Z method and (b) Y method Rg extraction for NMOS multi-OD device

Fig. 5.6 Comparison of (a) Z method and (b) Y method Rg extraction for NMOS multi-OD device

在文檔中 射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路 (頁 83-0)