Chapter 5 RF MOSFET Layout Effect on High Frequency Characteristics

5.3 Four-port 4T MOSFET with Various Body Contact Layouts

5.3.1 Four-port De-embedding Methods

The 4-port here has the same analytical de-embedding method for 2-port. The following equation is the matrix de-embedding method for 4-port devices:

_

meas o meas open

YYY (5.26)

_

short o short open

YYY (5.27)

1 1 1

_ _ (( ) ( ) )

dut meas o short o meas open short open

ZZZYY YY (5.28)

Thus, according to the above, the procedures of the two step de-embedding technique can be given as follows. First, we obtain the s-parameters (Smeas, Sopen, and Sshort) for DUT, open and short test structures and convert them to Y parameters (Ymeas, Yopen, and Yshort). Then perform the first step de-embedding by removing the parallel parasitics from both YDUT and Yshort according to the following equations

_

meas o meas open

YYY (5.29)

_

short o short open

YYY (5.30)

The last step of de-embedding is to perform the second de-embedding by removing the series parasitics Zshort_o, converting from Yshort_o, from Zmeas_o, converting from Ymeas_o according to the following equation

97

_ _

DUT meas o short o

ZZZ (5.31) 5.3.2 Intrinsic Device and Parasitic RLC Parameters Extraction and

Analysis – Body Contact Layout Effect and Bias dependence

As shown in the table, A 2*32um device with standard body layout is selected as a may cause the Cjd and Cjs lowering. The Fig. shows the source and drain junction capacitance Cjs and Cjd of standard, U shape, and L shape body contact layout. It is easily found that for the Cjs and Cjd without applied Rbb calibration, the capacitance at frequency higher than 500 Mhz dramatically drops because of the term 2(CjdCjs)2Rbb2 get higher. The phenomenon

Fig. 5.18 Cjs extraction versus frequency (a) without Rbb calibration and (b) after Rbb

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Fig. 5.19 Cjd extraction versus frequency (a) without Rbb calibration and (b) after Rbb calibration

Table. 5.5 Cjs extraction versus Vgb extraction

Vbs(V) Cjs(standard) Cjs(2-rings) Cjs(4-rings) Cjs(8-rings)

-0.6 2.67E-14 2.88E-14 3.32E-14 4.21E-14

0 3.50E-14 3.80E-14 4.34E-14 5.48E-14

0.6 9.50E-14 1.05E-13 1.24E-13 1.63E-13

Table. 5.6 The increment of Cjs with the body ring number increased

-0.6 7.87 16.5 33.3

0 8.57 15.4 32.57

0.6 10.5 20 41.05

Equation (Cjs_R2- Cjs_std)/ Cjs_std (Cjs_R4- Cjs_R2)/ Cjs_std (Cjs_R8- Cjs_R4)/ Cjs_std

Vbs(V) Capacitance of 4-rings

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Fig. 5.20 Cgs and Cgd extraction versus frequency of ring type body contact layout

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6

Fig. 5.21 Cjs extraction versus frequency of ring type body contact layout

Fig. shows the measured Csdb and Cbsd as a function of body bias Vbs for 1 ring and 8-Rings body contact layout devices. For a zero gate bias, the measured capacitance decreases with increasing junction reverse bias (Vbs< 0) due to the increase of the depletion widths of the individual junction components. It can also be seen that at Vgb= 0V (Vgs= Vbs= 0), corresponding to a depleted surface in the transistor channel. As the channel goes into accumulation (Vgb< 0V), the inner sidewall of source and drain junction comes into existence and the measured capacitance increases due to reduction of the depletion width of the

100

sidewall junction with increasing degree of accumulation.

-0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 multi-ring body contact structures (2-Rings, 4-Rings, and 8-Rings). It’s due to the more body contact we split, the more source side transmission line distance that may impact the total capacitance of source side capacitances as shown in Fig. 5.22.

These are mainly inter connect coupling capacitances introduced by both metal-to-metal and metal-to-contact interconnect.

The body resistance shows weak bias dependence, but strongly dependence on device geometry such as number of fingers and length of body contacts. In these case, 1/ Rbb scales with body contact length which is due to the length of resistive path.

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Table. 5.7 Body resistance and deep-N-well capacitance with different body shapes Body layout Rbb ( Ohm) Cdwn (fF)

Parallel 1415.48 105.6

L shape 691.86 132.8

U shape 600.97 140.9

Perpendicular 409.15 151.8 standard 384.21 155.4

2-Rings 310.25 166.6

4-Rings 212.87 187.7

8Rings 181.27 231.2

The extracted body resistance and capacitance values from Fig. can be viewed in Table.

The body resistance and capacitance values have been obtained after applying a slight optimization so that the best match for the simulated and measured Y-parameters can be achieved. The body resistance and capacitance values have been obtained after applying a slight optimization so that the best match for the simulated and measured Y-parameters can be achieved.

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Chapter 6 Conclusions

6.1 Summary

The potential impact from layout dependent STI stress on LFN and high frequency performance has been investigated on multi-finger MOSFETs with various layouts, such as narrow-OD and multi-OD. The monotonic decrease of Gm with finger width (WF) scaling in narrow-OD NMOS proves eff degradation from the compressive STI stress along transverse direction (). However, the multi-OD NMOS reveal an abnormal Gm increase for extremely narrow OD width to WOD=0.125m. The observed results suggest that STI stress is not the only mechanism governing the electrical property in miniaturized devices. STI TCR induced

W is identified as another key factor, which may overcome STI stress effect in determining channel current and Gm. Semi-empirical formulas have been derived to successfully predict WOD scaling effect on eff and Gm. Taking this method, W can be precisely extracted based on a simultaneous best fitting to eff and Gm and the resulted increase of effective width (Weff) is dramatically large to around 34% for OD16 with WOD=0.125m. The larger Weff becomes the major contributor to reducing LFN and overcome Nit effect in narrow-OD and multi-OD devices with sufficiently small WOD. The reduction of LFN with OD width scaling is the other evidence reflecting STI TCR induced W effect.

Unfortunately, the OD width scaling leads to a negative impact on high frequency performance like fT and fMAX, due to Gm degradation and undesired increase of Cgg. An improved open deembedding method can reduce the parasitic capacitances from inter-metal coupling but cannot eliminate gate related fringing capacitances. The multi-finger MOSFETs with miniaturized OD width cannot prevent from fT degradation. The trade-off between LFN and high frequency performance identified from this research work provides an important layout guideline for analog and RF circuit design.

103

The proposed donut MOSFETs demonstrate the advantages over the standard multi-finger MOSFETs, such as the lowest SID/IDS2 in low frequency domain (1~ 10K Hz) and higher fT in very high frequency region (100/50 GHz for N/P MOS). The elimination of STI stress and excess traps along the channel width is validated as the primary mechanism responsible for the enhancement of eff as well as fT, and reduction of LFN. The layout dependent stress mechanism can be applied to both NMOS and PMOS, even though their LFN are governed by different models. An innovative donut device layout for solving the potential degradation of fMAX and NFmin emerges as an interesting and important topic in the future work for RF and analog applications.

The variations of body contact layout reveal significant effect on body resistance (Rbb), junction capacitances (Cjs and Cjd), and gate capacitances (Cgs, Cgd, and Cgg). Multi-ring body contact layout offers the advantage of lower Rbb, but pays the penalty of larger junction capacitances and gate capacitance. The drawback of increased gate capacitances leads to degradation of high frequency performance like fT. For 8-ring body contacts, the measured fT is degraded by around 12.6%, compared to the standard multi-finger MOSFET with the same channel width (NFxWF). However, the fluence on fMAX from multi-ring body contact becomes a benefit instead of penalty. fMAX extracted from U-Gain method indicates around 9.84% and 8.41% improvement from 4-ring and 8-ring compared to the standard multi-finger MOSFET.

The mechanism responsible for fMAX improvement even under the condition of fT degradation introduces another interesting topic in future work.

6.2 Future Work

The proposed donut MOSFETs can provide the advantages over the standard multi-finger MOSFETs, such as the lower LFN for VCO or down-conversion mixer design.

Even though the improvement of eff and Gm can gain another benefit such as higher fT, the

104

significant increase of gate resistance Rg indeed leads to degradation of fMAX and RF noise, which are key parameters determining LNA and PA performance. An improved donut MOSEFT layout for solving the potential degradation of fMAX and NFmin emerges as an interesting and important topic in the future works for RF and analog applications.

The second interesting topic worthy of continuous research effort is to explore the mechanism responsible for fMAX improvement from multi-ring body contacts layout even with the penalty of fT degradation. The reduction of body resistance Rbb is considered one of key factors but the underlying mechanism is not truly understood. Furthermore, the impact from Rbb in single MOSFET on amplifiers like PA or LNA with cascade or cascade topology appears as another interesting subject in the future work.

The third interesting topic is the OD/STI density effect on STI stress and TCR profile, and their impact on eff, Gm, IDS, LFN, and high frequency performance (fT, fMAX , and NFmin).

Extremely narrow MOSFET with single gate-finger and multi-OD and multiple gate-finger and single narrow OD will be designed to investigate the mechanism.

The last one interesting topic to remark in the future work is the gate/channel orientation dependence of mobility modulation from STI stress. Single gate-finger MOSFETs with x- and y- gate/channel orientations and different channel width (WOD) will be implemented to explore the truth. Also, the results can facilitate analysis and modeling of donut MOSFETs with both x and y directions in the gate/channel orientation.

105

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