IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 19, NO. 11, NOVEMBER 2009 737
A 3–10 GHz CMOS UWB Low-Noise
Amplifier With ESD Protection Circuits
Chung-Yu Wu, Fellow, IEEE, Yi-Kai Lo, and Min-Chiao Chen
Abstract—A low-power fully integrated low-noise amplifier (LNA) with an on-chip electrostatic-static discharge (ESD) protec-tion circuit for ultra-wide band (UWB) applicaprotec-tions is presented. With the use of a common-gate scheme with agm-boosted tech-nique, a simple input matching network, low noise figure (NF), and low power consumption can be achieved. Through the combi-nation of an input matching network, an ESD clamp circuit has been designed for the proposed LNA circuit to enhance system robustness. The measured results show that the fabricated LNA can be operated over the full UWB bandwidth of 3.0 to 10.35 GHz. The input return loss(S11) and output return loss (S22) are less than 8 3 dB and 9 dB, respectively. The measured power gain (S21) is 11 1 5 dB, and the measured minimum NF is 3.3 dB at
4 GHz. The dc power dissipation is 7.2 mW from a 1.2 V supply. The chip area, including testing pads, is 1.05 mm 0.73 mm.
Index Terms—CMOS, electrostatic discharge (ESD), low-noise amplifier (LNA), ultra-wide band (UWB).
I. INTRODUCTION
I
T is known that ultra-wide band (UWB) technology offers the advantages of low-power consumption and high data rate for short-range communications [1]. The recent implan-tation of 3.1–10.6 GHz UWB systems integrated with CMOS technology is an attractive option because of its low cost and high-level digital integration. To date, many UWB circuits de-signed using CMOS technology have been reported [2]–[6].In a UWB receiver, a low-noise amplifier (LNA) is one of the most critical components due to the need for a high and flat gain response, good input matching, low noise figure of over 7.5 GHz bandwidth with a low power consumption and small chip area. Recently, different topologies for CMOS UWB LNAs have been proposed and investigated [3]–[6]. The use of a resistor feed-back is one of the features adopted in the design of UWB LNA. However, it can hardly satisfy the needs for wideband gain and noise requirement simultaneously under low power dissipation levels [3], [4]. The inductorless broadband circuits have also been proposed to minimize chip area [5]; however, a high level of power consumption makes these unsuitable for an integrated low-power system. In [6], an inductively degenerated common source topology is employed, but it cannot be operated on full UWB bands.
Since the RF CMOS circuit has been designed using con-tinuously scaled down CMOS technology, it is more
vulner-Manuscript received April 30, 2009; revised July 29, 2009. First published October 20, 2009; current version published November 06, 2009.
C.-Y. Wu is with the Department of Electronics Engineering, National Chiao-Tung University, Hsinchu, Taiwan (e-mail: cywu@alab.ee.nctu.edu.tw).
Y.-K. Lo and M.-C. Chen are with the Department of Electronics En-gineering, National Chiao-Tung University, Hsinchu, Taiwan (e-mail: yikailo@gmail.com).
Digital Object Identifier 10.1109/LMWC.2009.2032022
able to damage from electrostatic discharge (ESD). However, the use of, ESD protection circuits may degrade RF circuit per-formance, in particular, in UWB LNAs, where the parasitic ca-pacitance of ESD protection circuits may complicate the circuit design and seriously degrade its bandwidth. An inductive ESD protection technique [6] is proposed and simulated. Nonethe-less, despite their good performance on ESD immunity, full UWB bands cannot be achieved and no measurement results are available.
In this work, a low-power and fully integrated 3.0–10.35 GHz UWB LNA with on-chip ESD protection circuits in 130 nm CMOS process is designed and measured. By using a common-gate (CG) scheme with a -boosted technique, the proposed UWB LNA has a power dissipation of 7.2 mW on a 1.2 V voltage supply and achieves a power gain of dB, a min-imum noise figure (NF) of 3.3 dB, and sufficient input matching within all UWB bands. Both the RF and power pins are pro-tected by ESD diodes corresponding to the human-body model (HBM) ESD level of 1 kV.
In Section II, the circuit design is described. The experimental results are shown in Section III and a conclusion is provided in Section IV.
II. CIRCUITDESIGN
A schematic diagram of the proposed UWB LNA is shown in Fig. 1, where is the parasitic pad capacitance and is the dc blocking capacitor used to couple the input signal to the source of . Inductor at the source of is utilized to cancel the imaginary part impedance for the input impedance matching. Load inductor and resistor at drain is em-ployed to increase gain and bandwidth. The input CG stage is formed by , and . A -boosted tech-nique is realized by the inverting amplifier and which amplifies the input signal and feeds it to the gate of through the dc blocking capacitor to boost the equivalent transcon-ductance of . To improve bandwidth, a common-source (CS) amplifier consisting of and is cascaded to raise the overall gain and to extend the bandwidth. The sizes of , and are 4.6 nH, 1.17 nH, 10.9 nH, and 2.1 nH, respectively. In addition, all transmission lines are simulated by a 3-D EM simulator HFSS and estimated to be around 0.1 nH per hun-dred micrometers with a line width of 3 m. Finally, an output source-follower buffer and is designed to match the 50 system used for measurement.
To enhance the system’s robustness, an ESD protection cir-cuit is co-designed with the CG input stage. The ESD diodes are placed on both the RF and dc pads as shown in Fig. 1 to shunt the discharge current to ground to protect the LNA core circuit as in [7]. The area of each ESD diode, , and , is 5 m 5 m with a capacitance of about 40 fF.
738 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, VOL. 19, NO. 11, NOVEMBER 2009
Fig. 1. Schematic of the proposed UWB LNA.
Fig. 2. Simplified small signal schematic of the proposed LNA.
Assuming that the drain-source resistance of is much larger than the load impedance seen at the drain of and by grouping the capacitance of input ESD diodes and and pad capacitance to form and neglecting the large dc blocking capacitors and can be derived as follows:
(1) where is the transconductance of is gain of the inverting amplifier, and and are the gate-source capacitance of and , respectively. The value of is about 120 fF. is chosen to cancel the imaginary part of .
is set to 50 for input matching
(2) Fig. 2 represents the simplified small signal schematic of the proposed LNA where the gate-induced noise is neglected. In Fig. 2, is the source impedance, and are the drain current noise of and respectively, and and are the equivalent thermal noise currents of and , respec-tively. The noise from the cascaded CS amplifier is negligible because it is suppressed by the gain of its preceding stage. The overall noise appearing at the output node mainly consists of two components: one is the direct contribution of the noise cur-rent generated by , and via Path1, and the other is the
Fig. 3. Microphotograph of the proposed UWB LNA.
feedback noise power resulting from the noise generated by , and through Path2.
The noise contribution from Path1 is
, where is the impedance seen at the drain of . To calculate , it is assumed that the input impedance is equal to 50 and
as in (2). Thus, the noise voltage generated by and can be calculated as , whereas the noise from can be determined as ( , where is the impedance seen at the drain of . The drain current noise of is multiplied by the output impedance
seen at the drain node of , where
. Therefore, the feedback noise power can be derived as follows:
(3)
where , and and are
the channel thermal noise coefficients.
The overall noise factor of the LNA is defined as
(4) where is the gain of the LNA. Assuming the gain of the inverting amplifier is much greater than 1 and by using (3) and (4), the overall noise factor of the LNA can be derived using the following equation:
(5) As can be seen from the second and third terms in (5), by using the -boosted technique, the noise resulting di-rectly from and via Path1 can be reduced by a factor of . The noise from via Path2 appears in the fourth and last term of (5). The value of the fourth term is and results from the noise of , and entering Path2 and then emerging at the drain of . The last term in (5) originates from the drain current noise of
and is suppressed by a factor of .
The inverting amplifier and lowers the noise factor of a conventional CG LNA. However, the utilization of the inverting
WU et al.: 3–10 GHZ CMOS UWB LNA 739
TABLE I
COMPARATIVEPERFORMANCESUMMARY
Fig. 4. On-wafer measurement and Advanced Design System post layout sim-ulation results of the proposed LNA.
amplifier also contributes its own noise by introducing a feed-back path at the output node. Therefore, is 2–3 when noise contribution and suppression are taken into account.
III. EXPERIMENTRESULTS
The proposed ESD-protected UWB LNA is designed and fabricated using 130 nm CMOS technology. A source-follower output buffer and is integrated in the LNA for the purpose of measurement, as shown in Fig. 1. The simulated buffer loss is around 7.5 dB. With all the matching networks and ESD diodes located on the chip, the LNA occupies an area of 1.05 mm 0.73 mm, as shown in Fig. 3. The fabricated LNA dissipates 7.2 mW from a 1.2 V power supply. The measured of the proposed LNA is dB with a 3 dB bandwidth from 3.0 to 10.35 GHz, as demonstrated in Fig. 4, where the loss of the output buffer has been included. Due to process variations, the measured 3 dB bandwidth is about 3 GHz smaller than those in the simulation results. The measured minimum NF is 3.3 dB at 4 GHz and is below 5 dB from 3.0 to 7.5 GHz. However, the measured NF in the frequency range of 7.5–10.35 rises steeply because the measured peak gain and bandwidth at around 3 GHz is smaller than simulation results due to unexpected parasitics, and further degrades the noise suppression ability to the noise from the subsequent CS stage at high frequency. The measured is lower than dB, whereas is lower than dB over the full UWB bands as shown in Fig. 4. Finally, the input 1dB compression point
of the proposed LNA is dBm at 6 GHz.
Table I summarizes the measured performance of the pro-posed UWB LNA and presents the comparisons with other pub-lished UWB LNAs with measured data within the 3.1–10.6 GHz
UWB bands. As seen from Table I, the proposed LNA uses a -boosted technique has the best figure of merit (FOM). The FOM here appraises a maximum power gain , 3 dB band-width (BW), noise factor , and power consumption of the LNA and is defined as [4]
(6) In (6), and are absolute values, BW is in units of GHz, and is in units of mW. Moreover, only the proposed UWB LNA uses ESD protection circuits with a measured ESD level of 1 kV. As compared with those in [4]–[6], the proposed LNA can be op-erated in full UWB bandwidth. When compared with that in [3] where full UWB bandwidth is also achieved, the proposed LNA has a lower power consumption level and a better gain response. In addition, it is also evident that with integrated on-chip ESD protection diodes, the proposed LNA has sufficient perfor-mance over the entire UWB bandwidth.
IV. CONCLUSION
In this work, a low-power ESD protected 3.0–10.35 GHz UWB LNA is designed, fabricated, and measured. The proposed LNA is fabricated using 130 nm CMOS technology and has the advantage of better FOM, lower power consumption, full UWB bandwidth, and on-chip ESD protection. The measurement re-sults have verified that the proposed LNA can be applied to the CMOS UWB system.
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