Materials Science in Semiconductor Processing 9 (2006) 711–715
Comparison of InGaAs MOSFETs with
germanium-on-insulator CMOS
Albert Chin
a, C. Chen
a, D.S. Yu
a, H.L. Kao
a, S.P. McAlister
b,, C.C. Chi
c aDepartment of Electronics Engineering, Nano Sci. Tech. Ctr., Nat’l Chiao-Tung. University,University System of Taiwan, Hsinchu, Taiwan, ROC bNat’l Research Council of Canada, Ottawa, Canada
cDepartment of Physics, Nat’l Tsing Hua University, Hsinchu, Taiwan, ROC Available online 2 October 2006
Abstract
High mobility channel materials such as Ge and compound semiconductors (CS) show promise for future generation MOSFETs. The challenge is to integrate these materials with a Si substrate and create good interfaces in the devices. Here we show dislocation-free CSOI and Ge-on-insulator (GOI) devices with good characteristics. The InAlAs/InGaAs/InAlAs-OI on Si MESFETs shows a mobility of 8100 cm2/V s. To reduce the leakage current an Al2O3/InGaAs MOSFET was
fabricated. Good 451 cm2/V s mobility was obtained, higher than the 340 cm2/V s of GOI MOSFETs. However the marginally better mobility than GOI and 18X lower mobility than MESFETs indicate that the soft phonon scattering, high-k interface scattering and process variations are challenges for CS MOSFETs. In contrast, the GOI CMOS provides a simpler process and significantly higher electron and hole mobilities than its Si counterparts.
r2006 Elsevier Ltd. All rights reserved.
Keywords: Compound semiconductor FETs; Germanium-on-insulator; InGaAs MOSFET
1. Introduction
To continue current VLSI scaling trends, high-k dielectrics and metal-gates [1–7] have to be inte-grated into CMOS to reduce the large leakage current and DC power consumption. However, the mobility degradation in metal-gate/high-k/Si CMOSFETs is a challenge. This mobility degrada-tion is due to the ionic nature of the high-k dielectric, which leads to additional soft-phonon scattering. One method to overcome this problem is
to use strained-Si [4]; but this compromises the mobility enhancement, compared with the currently used poly-Si/SiON/strained-Si. A high mobility results in high transistor drive current, and is a key factor for achieving high circuit speeds. Thus it is desirable to improve the mobility beyond that of strained-Si devices. One candidate is Ge which shows significantly higher electron and hole mobi-lities compared with strained-Si. In this case, a Ge-on-insulator (GOI) structure is needed to reduce the transistor’s off-state leakage current which arises from the small energy band gap of Ge[8–13]. III–V MOSFETs have the potential of providing even higher electron mobilities. However, the technology challenge is to integrate III–V material with Si and 1369-8001/$ - see front matter r 2006 Elsevier Ltd. All rights reserved.
doi:10.1016/j.mssp.2006.08.066
Corresponding author. Tel.: +1 613 993 2514; fax: +1 613 990 7656.
form good interfaces in the MOSFET. Here we show the integration of a III–V material on Si, thus creating a compound semiconductor (CS) on-insulator (CSOI) device, using a process similar to that of our previous low-temperature wafer-bonded GOI [8–13]. The high electron mobility transistor (HEMT) [14–16] InAlAs/InGaAs/InAlAs-OI on Si showed a dislocation-free structure and an 8100 cm2/V s electron mobility. For comparison we fabricated an Al2O3/InGaAs MOSFET, which gave a significantly lower mobility than the InAlAs/ InGaAs HEMTs. However, the mobility value was higher than that of GOI devices [9]. The mobility improvement was limited by soft-phonon and interface scattering.
2. Experimental procedure
The first goal was to integrate the III–V material onto Si by forming a wafer-bonded CSOI structure, as shown in the process of Fig. 1. An inverted InAlAs/InGaAs/InAlAs HEMT structure was first grown on InP by molecular beam epitaxy (MBE)
[14–16]. Then a SiO2layer was deposited on top of
the InAlAs and the target Si wafer. To enhance the wafer-bonding at low temperatures an O2+exposure was used to activate the SiO2 surfaces, and the bonding was performed at 400 1C [8–12]. Then the InP substrate was thinned down followed by selective etching of the InP and InAlAs. InGaAs is a good etch stop when using an HCl-based solution, compared with InP and InAlAs. To fabricate a CSOI HEMT, the top n+ InGaAs contact layer over the gate was recess-etched to the InAlAs, where the gate electrode was formed by a Ti/Au Schottky contact. Then the source–drain contacts were formed by NiGeAu deposition[16].
A high-k/III–V MOSFET was also investigated in this study [17]. We used MBE to grow the 20 nm-InGaAs/300 nm-InAlAs quantum-well (QW) struc-ture on an InP substrate. Then the Al2O3 gate dielectric was deposited by RF sputtering from an Al2O3source. To study the Al2O3/InGaAs interface properties, the InGaAs surface with or without in situ atomic Al layer coverage was investigated before exposing the InGaAs to air. The Al-gate/ Al2O3/InGaAs/InAlAs MOSFET was fabricated by gate patterning, self-aligned Al/Yb deposition, and 400 1C rapid thermal annealing (RTA) to form the Schottky source–drain (SSD) contacts[18–20]. Such SSD contacts for InGaAs can avoid the difficult challenge of n+ ion implantation activation for source–drain contacts, as used in conventional CMOSFET fabrication.
3. Results and discussion
3.1. InAlAs/InGaAs/InAlAs-OI transistor
An InAlAs/InGaAs/InAlAs-OI device was exam-ined by cross-sectional transmission electron micro-scopy (TEM), as shown in Fig. 2(a), where no dislocations were seen at the resolution shown—this is important for high-yield IC fabrication. The white line in the middle of the SiO2layer is due to the O2 -plasma treatment, which is important for low temperature (400 1C) wafer-bonding and good mechanical strength. The CSOI design, which uses an inverted HEMT layer structure, is shown inFig. 2(b), and consists of an InAlAs barrier layer, two-dimensional (2D) planar n+Si doping layer, InAlAs top QW barrier, InGaAs QW channel, and InAlAs bottom QW barrier on the SiO2/Si substrate.
Fig. 3shows the Id– Vdcharacteristics of a 1.1 mm InAlAs/InGaAs/InAlAs CSOI transistor. For com-parison, data for a 0.35 mm SiO2/Si MOSFET are
O2 -plasma SiO2surface
treatment PECVD Oxide Deposition
Si wafer
In 5: InAlAs etch stop 4: InGaAs raised S&D 3: InAlAs QW barrier 2: InGaAs QW channel 1: InAlAs QW barrier SiO2 SiO2 Si Wafer 1: InAlAs QW barrier 2: InGaAs QW channel 3: InAlAs QW barrier 4: InGaAs raised S&D 5: InAlAs etch-stop
InP
Wafer bonding
InP 5: InAlAs etch stop 4: InGaAs raised S&D 3: InAlAs QW barrier 2: InGaAs QW channel 1: InAlAs QW barrier SiO2 SiO2 Si Wafer Selective etching of InP & InAlAs
4: InGaAs raised S&D 3: InAlAs QW barrier 2: InGaAs QW channel 1: InAlAs QW barrier SiO2 SiO2 Si Wafer
Fig. 1. Schematic of the process used to form the InAlAs/ InGaAs/InAlAs-on-insulator structure.
included. A high drive current of 0.41 mA/mm was measured, which is close to that for a 0.35 mm SiO2/ Si MOSFET. Such a high drive current in the CSOI HEMT is due to the high electron mobility of 8100 cm2/V s, which was determined using Hall measurements. The carrier density was 2.2 1012cm 2. The mobility value is nearly an order of magnitude higher than that for conven-tional Si and strained-Si devices.
3.2. Metal-gate/high-k Al2O3/InGaAs MOSFET It is well known that HEMTs or MESFETs are unsuitable for VLSI circuits due to their large gate leakage current. Therefore, a high-k/InGaAs MOSFET structure is preferred over a HEMT design. Fig. 4 shows the Id– Vd characteristics of an Al-gate/high-k Al2O3/InGaAs QW MOSFET.
In0.53Ga0.47As QW channel In0.52Al0.48As barrier layer In0.53Ga0.47As ohmic contact SiO2 and bonding interface Si 200nm SiO2 (a) Carriers from mod. doping EF EV In0.52Al0.48As In0.52Al0.48As In0.53Ga0.47As channel
2D planar impurity doping
EC φB
(b)
Fig. 2. Cross-sectional TEM and band diagram of the InAlAs/InGaAs/InAlAs FET structure. The middle InGaAs provides the channel, confined by InAlAs barriers. The upper InGaAs in the gate region was etched before depositing the metal gate.
0.0 0.5 1.0 1.5 2.0 2.5 0 5 10 15 20 25 1.0V 1.5V
Drain Current (mA)
Drain Voltage (V) InGaAs FET VG = 0.5V 0.0V -0.5V -1.0V 0.35μm Si MOS VG = 2.5V 2.0V -1.5V
Fig. 3. Comparison of the Id– Vd characteristics of InAlAs/ In0.53Ga0.47As CSOI MESFETs on Si (1.1 mm 50 mm) with 0.35 mm Si MOSFETs.
For comparison, the Id– Vd data from an Al2O3/ GOI device is also shown [9]. Unfortunately, the drive current of the Al/Al2O3/InGaAs nMOSFET is even less than that of an Al/Al2O3/GOI transistor. It is known from MBE studies that the native oxides of InGaO3and As2O3on InGaAs have weak bond strengths, requiring desorption temperatures of only 500 1C. Therefore, the poor mobility of the Al/Al2O3/InGaAs transistor may be due to these interfacial native oxides beneath the Al2O3 gate dielectric, as shown in the schematic diagram in
Fig. 5. Such a weakly bonded poor-quality oxide may give a high concentration of interface states by forming dangling bonds. This can limit III–V MOSFET development.
To overcome this problem the top InGaAs surface was covered by an in situ deposited Al layer a few atoms thick, which was converted to Al2O3 after air exposure, and during subsequent Al2O3 sputtering under O2+ conditions. Fig. 6 shows the Id– Vd characteristics of Al2O3/InGaAs MOSFETs with an in situ covered InGaAs surface. Signifi-cantly improved drain current is shown—better than the Al2O3/GOI and Al2O3/Si MOSFETs.
Such a drive current improvement is due to the higher electron mobility, as shown in Fig. 7. The mobility of the Al2O3/InGaAs transistor, with an improved interface, was 451 cm2/V s, which is 1.3 times higher than for an Al2O3/GOI MOSFET, and 2.5 times higher than that for the Al2O3/Si device. However, this mobility in Al2O3/InGaAs MOSFET is still 18 times lower than that of the HEMT, indicating that the soft-phonon and interface
0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 Al/Al2O3/GOI Al/Al2O3/InGaAs VG - VT = 2V (top) -0.5V step
Drain Current (mA)
Drain Voltage (V)
LG=10μm & WG=100μm
(InGaAs surface exposed to air)
Fig. 4. Id– Vdcharacteristics of Al/Al2O3/InGaAs MOSFETs on insulating InAlAs/InP, with the InGaAs surface exposed to air.
In In As Ga As As In As Ga As In As Ga O O As As As O In
Dangling bonds & interface states
Fig. 5. Schematic diagram of III–V oxide on InGaAs. Unlike SiO2/Si, more dangling bonds may be formed with the weak InGaO3and As2O3oxide on the InGaAs.
0.0 0.5 1.0 1.5 2.0 2.5 0 2 4 6 8 10 Al/Al2O3/Si Al/Al2O3/GOI Ta/Al2O3/InGaAs VG - VT =2V (top) - 0.5V steps
Drain Current (mA)
Drain Voltage (V)
Fig. 6. Id– Vdcharacteristics of Al/Al2O3/InGaAs UTB MOS-FETs on insulating InAlAs/InP, with an in situ covered Al2O3on the InGaAs. 0.0 0.2 0.4 0.6 0.8 1.0 0 200 400 600 800
Al/Al2O3/InGaAs (2.0nm EOT) Al/Al2O3/GOI (1.7nm EOT) Al/Al2O3/Si (1.7nm EOT)
Effective Mobility (cm
2/ V-sec)
Effective Field (MV/cm)
Fig. 7. Electron mobility of an Al2O3/InGaAs MOSFET compared with Si and GOI devices.
scattering are still limiting factors for the Al2O3/ InGaAs MOSFETs, even through the interface was covered by in situ deposited Al and converted into Al2O3.
4. Conclusions
We have fabricated defect-free InAlAs/InGaAs/ InAlAs-OI on Si, and high drive current CSOI HEMTs with a high 8100 cm2/V s mobility. The Al2O3/InGaAs MOSFET with an in situ interface treatment gave 1.3 or 2.5 times higher mobility than that of Al2O3/GOI or Al2O3/Si MOSFETs, respec-tively, but an inferior mobility compared with the HEMT structure. This suggests that the soft-phonon and interface scattering are the mechanisms limiting the performance.
Acknowledgment
The authors at NCTU would like to thank the partial support by the NSC (94-2215-E-009-062) of Taiwan.
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