switched resistors. The distortion of a switched resistor has been analyzed using the Volterra series. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant bandwidth of 125 MHz. The third-order intermodulation distortion is 86 dB at 10 MHz. The circuit dissipates 21 mW from a 3.3-V supply.
Index Terms—Distortion, programmable-gain amplifier (PGA), switched resistor, variable-gain amplifier (VGA).
I. INTRODUCTION
I
N A MODERN communication receiver, the received signal is quantized by an analog-to-digital converter (ADC) so that complex signal processing can be performed in the digital domain. As shown in Fig. 1, a programmable-gain amplifier (PGA) is usually placed in front of the ADC, adapting the loss variation of the transmission channel in order to ease the dynamic range requirement for the ADC. The gain of the PGA is digitally controlled by an automatic gain control (AGC) loop. The linear-in-dB gain control for the PGA is usually required to achieve constant settling time of the AGC loop [1]. In the broad-band wireline receiver such as very high-speed digital subscriber lines (VDSL), the ADC usually requires 12-bit resolution with 0.2–11 MHz signal spectrum. It indicates that the PGA needs to have smaller than 74-dB total harmonic distortion (THD) over the signal spectrum, and amplifies the received signal by 0 to 20-dB gain control range [2], [3]. Signal attenuation may be required to accommodate large input signal swing [4]. The PGA needs to maintain its high linearity and low noise over the entire signal bandwidth as well as gain range.High-speed PGAs have been realized using variable MOS transconductors in the disk drive applications [5], [6]. The linearity is limited by nonlinear characteristics of the transcon-ductors. Although the resistor-network feedback closed-loop architectures can achieve high linearity [7], previous designs involved tradeoff among gain range, bandwidth, linearity, and power dissipation.
Manuscript received March 6, 2003; revised July 4, 2003. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC-90-2215-E-009-110 and by the Lee-MTI Center, National Chiao-Tung University.
The authors are with the Department of Electronics Engineering, National Chiao-Tung University, Hsin-Chu 300, Taiwan, R.O.C. (email: jtwu@mail. nctu.edu.tw).
Digital Object Identifier 10.1109/JSSC.2003.817665
Fig. 1. Block diagram of an analog front-end.
This paper describes a PGA using an amplifier with low input impedance and resistor-network feedback to achieve high lin-earity and wide bandwidth simultaneously. The PGA meets the stringent requirements of the VDSL system. The paper is orga-nized as follows. Section II analyzes various PGA architectures. Section III contains the distortion analysis of switched resistors. The proposed PGA is described in Section IV. Section V shows the experimental results, and finally, conclusions are given in Section VI.
II. PGA ARCHITECTURES
The four basic gain variation techniques are shown in Fig. 2. Fig. 2(a) is a current divider. The dividing ratio is determined by the control voltage . The quadratic characteristic of the current divider makes it difficult to realize a linear-in-dB gain setting. A predistorting stage for may be required [8]. The overall linearity is limited by the input transconductor which generates .
The transconductance of the source-coupled pair shown in Fig. 2(b) is varied by changing the bias current of the transistors [9]. The circuit’s gain and the input-referred noise are propor-tional to and of the input transistors, respectively. When the input signal is weak, the large bias current is needed to obtain high-gain and low-noise performance. On the other hand, when the input signal is large, the low bias current can degrade the linearity.
In Fig. 2(c), the transconductance of the source-coupled pair is varied by changing the resistance of the degeneration resistor . When the input signal is weak, small is used to obtain high gain and low noise. When the input signal is large, large is used to obtain low gain and high linearity. Thus, this topology can achieve constant signal-to-noise-and-distortion ratio for the fixed output level regardless of the gain settings.
Fig. 2(d) shows a high-gain amplifier with resistor-network feedback. Its voltage gain can be varied by changing the ratios of and . High linearity can be achieved if the loop gain is large and the resistor network is linear. However, if the conventional operational amplifier is used [7], the variation of 0018-9200/03$17.00 © 2003 IEEE
Fig. 2. Basic topologies for gain variation.
Fig. 3. Degenerated differential pair with the super-source follower.
the feedback factor results in variations of the bandwidth and the total harmonic distortion. When the circuit is designed to cover the worst-case scenario over the entire gain range, its power consumption is not optimized.
Fig. 3 shows a variation of the Fig. 2(c) topology [10]. The source-coupled transistors are replaced by two super-source fol-lowers [11], [12], consisting of M1-M3- and M2-M4- . The improved output resistance of the super-source followers can reduce distortion when driving the resistive loads. However, the open-loop nature of the M3-M5 and M4-M6 current mirrors can limit the overall linearity of the circuit.
The circuit shown in Fig. 4 was derived from Fig. 3 [13]. It can also be shown as a variation of the Fig. 2(d) topology. As depicted in Fig. 4(a), it is a noninverting feedback configura-tion, with voltage gain approximately equal to . The input impedance of the amplifier is designed to be low. Thus, the PGA’s feedback factor is a constant, if is not changed. The overall voltage gain is varied by changing . One drawback of this configuration is that the voltage gain can only be larger than one. Signal attenuation is not possible.
A PGA with differential inverting configuration is shown in Fig. 5(a) [14]. The overall voltage gain is equal to the ratios of and . Thus, the signal amplification and atten-uation can be obtained easily through this configuration. Two voltage buffers, B1 and B2, are placed before the variable resis-tors and to provide high input impedance for the inputs.
(a)
(b)
Fig. 4. (a) Noninverting resistor-network feedback configuration. (b) Single-ended circuit schematic.
(a)
(b)
Fig. 5. Programmable-gain amplifier (PGA) simplified schematic.
With low input impedance of the input stage for the A1 amplifier and fixed resistances for and , the PGA can maintain a constant feedback factor, regardless of the values of and . Thus, the amplifier can be optimized for minimal power dissipation at a specific bandwidth. The PGA’s voltage gain can be varied by changing the resistances of and . When the PGA is placed in an AGC loop, and resistors will be ad-justed so that the average current signals flowing through the resistors remain constant, leading to little change of linearity at the PGA’s outputs.
To facilitate digital gain control, the variable resistors, and , are realized using the linear resistors in series with the MOSFET switches biased in the triode region, as shown
of the nonlinear effects of the MOSFET switch on the switched resistor is essential to obtain optimal tradeoff between the overall linearity and available bandwidth. Detailed analysis of the switched resistors is given in the following section.
III. SWITCHEDRESISTORANALYSIS
The circuit model for a switched resistor is shown in Fig. 6. To minimize the distortion, the MOSFET switch is usually con-nected to the virtual ground, such as the summing node of the feedback network. We can describe the drain current of the MOS transistor using Taylor series expansion at . Neglecting terms whose order is higher than three, the drain current is given by
(1) where is the drain–source conductance, and are the second- and third-order nonlinear coefficients, respectively. The body effect, mobility reduction, and carrier velocity saturation must be considered in order to understand their influence in the deep-submicron technology. Calculated from the simple level-two model of the device, the drain current can be expressed by [16]
(2) where is the effective surface mobility, is the gate-oxide capacitance per unit area, is the flat-band voltage, is the body-effect factor, and is the surface potential. Consid-ering the short-channel effects, the mobility term in the cur-rent–voltage characteristic shows a dependence on the voltage or channel electric field [17]. Therefore, it causes the dis-tortion in the switched resistor. Neglecting terms whose order is higher than three, the mobility reduction caused by voltage can be also expressed as
(3) where is the carrier mobility when and is the critical electric field which is approximately 6.09 MV/m for the 0.35- m CMOS technology used in this paper.
(4) (5) where is the input’s peak amplitude, is the linear conductance, and is the equivalent resistance of the switched resistor. The is proportional to the second-order nonlinear coefficient . The consists of two major contributors. One is the third-order coefficient of the drain current, and the other is due to the mixing of the second-order coefficient and the linear conductor .
By using these expressions in (1), (2), and (3), (4) and (5) can be rearranged as
(6)
(7) where is the device transconductance para-meter, and is the gate overdrive voltage. For a given , the distortions can be reduced by increasing which is equal to . The mobility reduction on shows up in the first term of (7); but it has the opposite effect against the body effect.
The setup shown in Fig. 7 has been used to measure the and of the switched resistors [16]. N-channel MOSFETs from a standard 0.35- m CMOS technology are measured. The dc gain of the voltage-mode operational amplifier (opamp) is 94 dB, which is enough to suppress the distortions caused by the opamp itself. The input is a sinusoidal signal with 0.5-V amplitude and 1-kHz frequency. The MOSFET’s body effect parameter is found to be 0.52 V , and its substrate bias is set to 1.83 V.
Both measured and calculated distortions versus the MOSFET’s are shown in Fig. 8. The MOSFETs with different size are all biased with a gate overdrive of 0.43 V. The resistance of is adjusted so that the equivalent total resistance of is 1 k . The calculated values from (6) and (7) are in good agreement with the measured data.
The measured and calculated distortions versus the MOSFET’s are shown in Fig. 9. The resistance of is adjusted so that the equivalent total resistance of is 1 k .
Fig. 8. Measured and calculatedHD and HD versus r .
Fig. 9. Measured and calculatedHD and HD versus V .
Under the condition of a fixed , the switched resistor exhibits an inversely proportional to the third order of the gate overdrive, and an inversely proportional to higher than fourth order of the gate overdrive. Thus, the most effective way to improve the linearity of a switched resistor is to increase the gate overdrive.
The measurement shows that the MOSFETs with different channel length have almost identical distortions if their channel resistances are adjusted to have the same value. Under the conditions of Fig. 8, the calculated first terms of (7) are approximately 34 and 60 dB less than the second terms of (7) for 0.35- and 1.4- m channel length, respectively. Although the influence of the mobility reduction increases when the channel length decreases, it is still not significant for the 0.35- m channel length. Thus, it can be concluded that the effect of mobility variation shown as the first term in (7) can be ignored for the 0.35- m technology.
In most switched resistor applications, the MOSFET’s gate overdrive is limited by the supply voltage. Distortions are re-duced by using the transistors with larger channel width. But increasing the device’s size also increases the gate-to-source ca-pacitor and the source-to-substrate caca-pacitor, shown as and in Fig. 6. If the capacitors are at the summing node of the
Fig. 10. MeasuredHD and HD versus the time constant R C .
Fig. 11. For givenR and targeted HD , the minimum device size can be determined. The channel length is 0.35m, R = 1 k, V = 0:5 V, and
V = 0:43 V.
feedback loop, such as the one shown in Fig. 5, they can degrade the stability and settling time of the circuit. Let
is proportional to the transistor’s channel width , then we have
(8) The is inversely proportional to the square of time constant
.
For the switched resistor, there is a tradeoff between linearity and bandwidth. The distortions versus time constant are shown in Fig. 10 for the MOSFET switches with different channel length. The switches with shorter channel length should be used when the short-channel effects on the distortions are still not significant. For a fully differential circuit configuration, the distortion can be suppressed effectively so that the is dominant. When the total resistance of and the design target of the are given, it is possible to calculate the minimum device size. The capacitor and versus the channel width are shown in Fig. 11. The capacitor increases with the channel width while the decreases with the channel width. If the targeted is 74 dB, the crossing point of the dash line and the line of versus channel width determines the minimum device size. It corresponds to the minimum capacitance of . Therefore, the switched resistors
Fig. 12. Proposed PGA circuit schematic.
can be effectively designed by calculating the minimum device size of the switches from (7), as follows:
(9) The body effect is neglected in the above equation.
As shown in Fig. 6, the frequency dependence of the distor-tion is due to the nonlinear juncdistor-tion capacitors, and . In most cases, the transistor’s source node is connected to the virtual ground, and the nonlinear effects of can be ignored. Increasing the channel width of the MOSFET switch results in larger , and potentially degrades the linearity. For given and input voltage amplitude, the effect of the larger on dis-tortions is compensated by a smaller across the transistor, so that the contribution of on distortion does not change signif-icantly. With the following conditions, k , V,
k , m m, fF, and
V, the estimated is 74 dB and the simula-tions show the distorsimula-tions are unchanged versus the frequency sweep up to several hundred megahertz.
IV. PGA CIRCUITDESCRIPTION
Fig. 12 shows the circuit schematic of the proposed PGA based on the architecture in Fig. 5. The two super-source fol-lowers [11], [12], M21–M28, are voltage buffers to provide high input impedance. The variable resistors, and , are two separate digitally controlled switched resistor networks. The high-gain current amplifier, consisting of M1–M15, has low input impedance and high output impedance. Transistors M1 and M2 form the input common-gate stages. The local feed-backs provided by the M3 and M4 transistors further reduce the input impedance of the M1 and M2 input stages. To enable the capability of common-mode rejection, the second gain stage is realized using the M11–M12 source-coupled pair. Not shown in the schematic is a continuous-time common-mode feedback (CMFB) which is applied to stabilize the common-mode voltage at the gates of the M11–M12 pair. The CMFB monitors the common-mode voltage and adjusts the currents of the M9 and M10 current sources. The transfer characteristic of the current amplifier is linearized by the two fixed resistors, and . The frequency compensation capacitors, and , create
Fig. 13. Chip micrograph of the PGA.
no right half-plane feedforward zero usually associated with the Miller compensation technique [18].
In addition to the nonlinear characteristics of the and switched resistors, other distortion sources in the PGA are sup-pressed by the negative feedbacks. The distortions caused by the two input super-source followers driving the resistive loads are suppressed by the internal feedback loops [16], which have the loop gain expressed as
(10) where and are the transconductances of M21 and M23, respectively, and is the output resistance of M25. If , the loop gain is insensitive to variation when changing the PGA’s voltage gain. Then, the loop gain can be approximated by .
The distortions caused by the current amplifier are suppressed by the negative feedbacks using the and linear resis-tors. The loop gain can be expressed as
(11) where is the transconductance of M11, is the output resistance of M9, is the output capacitive load, and is the parasitic capacitance at the gate node of M11. By freezing the values of and , this loop gain and the distortion of the current amplifier remain unchanged, regardless of the PGA’s voltage gain setting. At high frequencies, the zero caused by the compensation capacitors, and , can boost the loop gain, thus improving the amplifier’s linearity. Simulation shows that,
with pF and pF, the compensation
capacitors can improve the linearity by 3 dB, comparing with the traditional Miller compensation.
V. EXPERIMENTALRESULTS
A PGA test chip was fabricated in a standard 0.35- m CMOS technology. A micrograph of the chip is shown in Fig. 13. The active area occupies 0.18 . Power dissipation is 21 mW from a 3.3-V supply, of which 6.6 mW is consumed by the two input voltage buffers. The resistance of is 5 k , while the minimum and maximum resistances of are 0.42 and 4.2 k , respectively. At the maximum gain setting,
Fig. 14. Measured PGA’s gain versus digital control input.
Fig. 15. Measured PGA’s frequency response.
in the switched resistor of either or , the linear resistor is 0.31 k , and the MOSFET switch has a size of m m and an equivalent resistance of 0.11 k . The of this switched resistor is calculated to be 105 dB with 0.96-V gate overdrive voltage when the PGA’s output is 2 V . Since the targeted is 74 dB, the design margin is 31 dB. Thus, the switched resistor does not dominate the linearity of the PGA. The switched resistors are weighted to obtain a dB-linear gain step with a step size of 2 dB. Fig. 14 shows the measured PGA’s voltage gain versus the digital gain control input. The voltage gain can be varied from 0 to 19 dB. The maximum gain error is 1 dB at 20-dB gain setting. The measured PGA’s frequency response is shown in Fig. 15. The PGA maintains a constant bandwidth of 125 MHz over the entire gain range, while driving 2-pF capacitive loads.
Fig. 16 shows the measured third-order intermodulation distortion (IM3) of the PGA at different frequencies when the
Fig. 16. Measured PGA’s IM3 versus frequencies at 1 V and 2 V output.
Fig. 17. Measured IIP3 at 10 MHz.
outputs are 2 V and 1 V . As frequency increases, the IM3 worsens due to the attenuation of the amplifier’s loop gain and the nonlinear junction capacitors at the output nodes. With 2-V and 1-V output, the IM3 are 74 and 86 dB at 10 MHz, respectively. The variation of the IM3 for different gain settings is less than 5 dB over the 0–80-MHz frequency range for 1-V output. Fig. 17 shows the measured input-re-ferred third-order intercept point (IIP3) at 10 MHz. The IIP3 are 35 and 12 dBm for 0 and 19 dB gain settings, respectively. The input-referred noise is 8.63 nV Hz for 19-dB gain.
The PGA’s performance is summarized in Table I and com-pared with several previously published designs. Note that the input-referred noise is calculated at the maximum gain setting. In [6], the PGA is based on the architecture in Fig. 2(b). Thus, the differential pair generates quadratic nonlinearities. In [10], the linearity is limited by the open-loop current mirroring from
of the MOSFET switch, and depends on the transistor’s device size and gate overdrive voltage, as well as the associated linear resistor. Closed-form formulas for and have been de-rived, and verified with the experimental data.
A PGA has been designed and fabricated using a standard 0.35- m CMOS technology. The PGA has a voltage gain varying from 0 to 19 dB, while maintaining a constant band-width of 125 MHz. With 2-V and 1-V output, the IM3 are
74 and 86 dB at 10 MHz, respectively.
APPENDIX
A weakly nonlinear network can be represented by the sum of a linear term, a second-order term, and a third-order term, etc. [19]. This series is called the Volterra series. In Fig. 6, the Volterra series of the voltage can be described by
(12) where is the input’s peak amplitude, and , , and represent the Volterra coefficients. The drain current can be cal-culated as
(13) where is the linear resistor. Following the definition for har-monic distortions, the expressions for and in terms of the Volterra coefficients are given by
(14) (15)
Calculating the Volterra coefficients [16], , , can be obtained as
(16) (17) (18)
Center for chip fabrication.
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front-end circuits in data communication. From 1980 to 1982, he served in the Chinese Army as a Radar Technical Officer. From 1982 to 1988, at Stanford University, he focused his research on high-speed analog-to-digital conversion in CMOS VLSI. From 1988 to 1992, he was a Member of Technical Staff at Hewlett-Packard Mi-crowave Semiconductor Division, San Jose, CA, and was responsible for several linear and digital gigahertz IC designs. Since 1992, he has been with the Depart-ment of Electronics Engineering, National Chiao-Tung University, where he is now a Professor. His current research interests are integrated circuits and sys-tems for high-speed networks and wireless communications.
