Quasiresonant Control With a Dynamic Frequency
Selector and Constant Current Startup Technique for
92% Peak Efficiency and 85% Light-Load Efficiency
Flyback Converter
Yu-Chai Kang, Chao-Chang Chiu, Moris Lin, Chih-Pu Yeh, Jinq-Min Lin,
and Ke-Horng Chen, Senior Member, IEEE
Abstract—The proposed quasiresonant control scheme can be widely used in a dc–dc flyback converter because it can achieve high efficiency with minimized external components. The proposed dynamic frequency selector improves conversion efficiency espe-cially at light loads to meet the requirement of green power since the converter automatically switches to the discontinuous conduc-tion mode for reducing the switching frequency and the switching power loss. Furthermore, low quiescent current can be guaranteed by the constant current startup circuit to further reduce power loss after the startup procedure. The test chip fabricated in VIS 0.5 μm 500 V UHV process occupies an active silicon area of 3.6 mm2. The
peak efficiency can achieve 92% at load of 80 W and 85% efficiency at light load of 5 W.
Index Terms—Constant current startup (CCS) circuit, discon-tinuous conduction mode (DCM), dynamic frequency selector (DFS), proportion integral compensator.
I. INTRODUCTION
T
HE public awareness about environmental issues has been raised, so there are growing concerns over energy-saving topic and green power in recent years. Nowadays, elec-tronic equipment are widely used and developed, which brings tremendous commercial potentials about power-saving issues. Consequently, many researches put much emphasis on the power conversion efficiency and standby power losses of power converters.Most of the electronic equipment has to take the isolation between high and low voltage (LV) into considerations for the safety concerns. Thus, flyback topology uses one transformer to terminate any straight electric connection between high in-put voltage and the converter’s outin-put power stage. Besides, a
Manuscript received October 25, 2012; revised January 20, 2013 and March 20, 2013; accepted April 30, 2013. Date of current version April 30, 2014. This work was supported by the National Science Council, Taiwan, under Grants NSC 101-2220-E-009-047, NSC 101-2220-E-009-052, and NSC 101-2622-E-009-004-CC2. Recommended for publication by Associate Editor G. Escobar.
Y.-C. Kang, C.-C. Chiu, M. Lin, C.-P. Yeh, and K.-H. Chen are with the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: khchen@cn.nctu.edu.tw).
J.-M. Lin is with Vanguard International Semiconductor Corporation, Hsinchu 30077, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2013.2263040
Fig. 1. Conventional flyback converter.
flyback converter can operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), and critical conduction mode (CRM). Compared with the CCM, the CRM has the advantages of soft switching, fast transient response, smaller transformer size, and easier compensation for system’s stability [1]–[3]. The conventional current-mode pulse width modulation (PWM) control flyback converter is depicted in Fig. 1; an oscillator is used to trigger the periodical switching cycle [4]. Although constant frequency control is much easier to design, it is far from green power because of high switching power loss at light loads. Besides, large power loss is dissipated due to the ON–OFF operation of the power switch if high volt-age (HV) stress is across its drain and source terminals. Zero current detection (ZCD) is used to decide the turning-on tim-ing [5], [6], which ensures system operation in DCM or CRM. However, it suffers from large switching power loss caused by the nonoptimum turning-on mechanism which lacks consider-ing the output loadconsider-ing. Therefore, power efficiency is seriously decreased by extra switching power loss. For that reason, sev-eral turning-on control methods have been proposed to enhance power efficiency [7]–[15].
Quasiresonant (QC) control is one of the most popular meth-ods to reduce switching power loss at light loads [16], [17]. Owing to the LC resonant tank composed of the transformer’s inductance and the parasitic capacitance of the power MOSFET, the power MOSFET will be turned ON by the zero-voltage switching (ZVS) technique once the drain voltage resonates to the lowest value. Unfortunately, simply using the ZVS technique 0885-8993 © 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
Fig. 2. Proposed flyback converter with the DFS and the CCS techniques.
still results in low efficiency and high switching frequency at light loads. The switching frequency becomes high due to small on-time duty caused by light-loading conditions. The switch-ing power loss dominates the total power loss at light loads and further deteriorates the power conversion efficiency. To im-prove power conversion efficiency at light loads without being affected by the shrinking on-time length, the proposed dynamic frequency selector (DFS) technique is capable of adjusting off-time length according to the varied loading conditions. That is to say, the switching frequency is reduced with corresponding decreasing output loadings.
Moreover, the power dissipation at some passive components should be carefully considered to further reduce the standby power loss at light loads. Conventional startup circuit uses one diode followed by a high value resistor as the current source. However, diode and resistor cause serious leakage problem since they cannot be shut down after the startup period is done. Large leakage current results in low efficiency especially at light loads [18]. Thus, the proposed constant current startup (CCS) circuit replaces the diode with a depletion N-type MOSFET to generate the startup current. Thanks to the removal of the external passive components, the power consumption and the footprint area are able to be reduced effectively. Besides, the CCS circuit able to OFF the leakage path improves standby power efficiency. The aforementioned merits contribute to good power efficiency.
This paper is organized as follows. Two proposed techniques are described in Section II. The circuit implementations are illustrated in Section III. The system stability is analyzed in Section IV. Experimental results are shown in Section V. Finally, conclusions are made in Section VI.
II. SYSTEMOPERATION OF THEPROPOSEDFLYBACK CONVERTER
The proposed structure of the current-mode flyback converter is depicted in Fig. 2. Similar to conventional flyback converter, the power stage contains one transformer with three windings and one optocoupler functioning as isolation between the out-put stage and the inout-put stage [19]. The flyback converter uses transformer’s magnetizing inductance to store energy and then to transfer it to the output.
Fig. 3. Main operation of the proposed flyback converter.
Basically, switching power loss can be divided into two parts, conduction power loss in (1) and switching power loss in (2), in-cluding charging and discharging Coss, where Ipis the
primary-side current, Rds,on is the on-resistance of the power switch,
Cossis the gate-source parasitic capacitance of the power
MOS-FET, Vdsis the drain–source voltage, and fsw is switching
fre-quency
Pcon loss = Ip2Rds,on (1)
Psw loss = CossVds2fsw. (2)
At heavy loads, the proposed flyback converter operates in the CRM, which is similar to conventional flyback with the ZCD control. Thus, the switching power loss can be ignored and the total power loss is dominated by conduction power loss. On the other side, switching power loss gradually dominates the total power dissipation at light loads due to the nonzero value of Vds. Thus, it is more important to reduce Vdsand fsw to reduce
the switching power loss. The proposed flyback converter not only detects the resonant valley voltage to minimize power loss at Vds, but also optimizes the switching frequency according
to the output loading conditions. Thus, two parts of switching power loss can be effectively reduced.
Fig. 3 shows the main operation of the proposed flyback converter. The primary-side and secondary-side currents are Ip
and Is, respectively, which is in the shape of triangle waveform.
The voltage VC S, across the current sensing resistor RC S, is used
as a current-mode control signal when the power MOSFET turns ON. The feedback voltage VFB determined by the feedback
network composed of optocoupler and the TL431 working as an error amplifier proportional to the output loading. The on-time duty can be decided by the comparison results of VC S and
VFB. On the other hand, the off-time length is detected by the
valley voltage of Vdrainto achieve near-ZVS operation. To avoid
increasing the switching frequency when the input voltage or the loading is low, the DFS technique can select one of the valleys accordingly to change the off time.
A. Proposed DFS Technique
The operation of the DFS technique as depicted in Fig. 4 contain two modes, the valley selection mode and the Green mode. When the input voltage or the loading gradually becomes lower to some extent, the automatic voltage stabilizer (AVS) mode accordingly decreases the switching frequency to reduce
Fig. 4. (a) Operation of the DFS technique. (b) Switching frequency versus the loading current. (c) Subtle change of on time and off time along with the load changes. (d) Simulation results of efficiency and power consumption at different loads (VA C = 110 V).
switching power loss. In Fig. 4(a), the stored energy in the primary winding (Np) is transferred to the output when VG D
changes from high to low to turn OFF the power MOSFET. Due to Lenz’s law, Vdrainat the drain of power MOSFET jumps from
zero to Vin+nVout. At this moment, Ipbegins to decrease toward
zero. When Ip is down to zero, the stored charges in the drain
terminal of the power MOSFET starts to dash to the transformer side and then back to the drain side back and forth. Resonant phenomenon with a resonant frequency determined by CD Sand
LP starts and is reflected to the auxiliary side simultaneously.
To reduce switching power loss, the optimum turn-on timing occurs at the valley of Vdrain because the near ZVS will bring
low switching power loss. Put into another words, the valley voltage detection in the resonant effect is able to determine the next turn-on timing of the power MOSFET.
In the DFS technique, dynamic off-time control can be de-rived by the selection of the valley at different loads as illustrated in Fig. 4(b). At heavy loads, the conduction loss dominates the energy efficiency. That is why the first valley is the optimum choice to deliver energy to the output since the minimum off-time length can be achieved. Besides, the peak value of the inductor current is also reduced to help increase the overall effi-ciency. On the other hand, the switching power loss dominates the energy efficiency at light loads. Consequently, the off-time length is further extended by picking up the later valley ac-cording to the load conditions to reduce the switching power loss.
If the system does not have the AVS technique, the switching frequency will gradually increase along with the decrease of the load current owing to the decrease of both the on-time and off-time length. The reason is the selection of the valley cannot continuously change from one valley to the other valley owing the quantization error at the selection of valleys. If the valley selection is changed to the next one of the sequential number, the switching frequency will decrease immediately to further reduce the switching power loss. The instant decrease of the switching frequency contributed by the adaptive valley selection can greatly improve the power conversion efficiency.
When the load gradually decreases, the on-time period also becomes shorter as depicted in Fig. 4(c). It causes both switching frequency increases as expressed in (3). Owing to the decrease in the on-time period where one valley voltage is selected, the off-time period toff n in this case is determined
f1 < f2, where f1 = 1 ton1+ toff n f2 = 1 ton2+ toff n
, and ton1> ton2. (3)
Unfortunately, the switching power loss also increases. There-fore, the AVS technique is used to make the switching frequency modulated with the load condition for effectively improving ef-ficiency. That is to say, the next valley voltage, which determines the longer off time toff (n + 1), is selected to reduce the switching
frequency. As shown in (4), the new switching frequency f2 is smaller than the f1due to the increase of the off-time period
f1 > f2 where f2 =
1 ton2+ toff (n + 1)
. (4)
Besides, the duration between toff (n + 1)and toff n can be
pre-dicted by the resonant inductance and capacitance. Therefore, the boundary condition can be derived as shown in
(ton1− ton2) < (toff (n + 1)− toff n) = 1/2π
√ LC = 2π√LC. (5)
Fig. 5. Proposed CCS technique with the UVLO under different operation conditions.
In summary, the trend of the switching frequency is decreas-ing when loaddecreas-ing current decreases. Fig. 4(d) shows that the power conversion efficiency can be improved due to the re-duction of the switching power loss contributed by the DFS technique. Along with the decreasing load, the resonant ampli-tude becomes smaller because of the parasitic resistance at the resonant path. It may fail to detect the valley voltage due to the gradually decaying valley voltage. That is, the next on-time needs to be triggered by another mechanism for correction and safety operation. Thus, the Green mode is proposed to set the off time with a constant value of 500 μs for further improving efficiency at ultralight loads and to ensure the correct operation of the converter. Furthermore, the maximum load is limited by the predefined maximum on time for system protection.
B. Proposed CCS Technique and Power-on Sequence
In the design of flyback converters, the correct power-on se-quence can protect the device from damaging. The supply is provided by the auxiliary winding (Na) of the transformer as
depicted in Fig 2. Prior to the first switching of the controller, there is no power that can be delivered to auxiliary winding be-cause the output voltage is still lower than some extent. Thus, a low quiescent startup circuit is necessary to ensure the internal supply voltage, VD D H, high enough to make the converter work
correctly. Furthermore, the startup circuit is supposed to be shut down right after the end of the start-up procedure to further save power.
As depicted in Fig. 5, a constant startup current IH V is
de-signed to be around 1.2 mA to slowly ramp up VD D Hbefore the
end of the startup period. Constant charging current can pro-tect the ultrahigh voltage (UHV) device from breaking down by large startup current. Once the value of VD D H reaches the
expected internal voltage, the control authority of the converter is transferred to the switching control loop. The gate control signal VG Dcontrols the switch of the power MOSFET.
Simulta-neously, Vaat the auxiliary winding (Na), depicted in Fig. 2, is
charged to 16 V as an internal supply voltage for the controller. Before the switching control loop dominates, Vais clamped to
a lower level. Here, the under voltage lockout (UVLO) circuit monitors the value of VD D H. If VD D H is smaller than 10 V, the
switching control loop will be stopped to shut down the
sys-Fig. 6. Architecture of the proposed flyback convertor controller.
Fig. 7. Waveforms of the DFS in a switching period.
tem and wait for the autorecovery mechanism. In other words, the system tries to wake up to restart the CCS circuit in the autorecovery procedure once VD D His smaller than 8 V.
III. CIRCUITIMPLEMENTATION
The proposed flyback controller is depicted in Fig. 6 with three parts, LV part, HV part, and UHV part. The UHV part is the CCS circuit that offers the HV supply VD D Hwith a value of 16 V
for the HV driver to turn ON the external power MOSFET. The HV part is composed of the UVLO circuit and the preregulator. The preregulator functions as the internal power supply 5 V for the LV circuit. Basically, the LV part includes on-time and off-time control circuits to determine VG D. In addition, internal
LV bandgap can provide accurate reference voltage and biasing current to ensure a voltage with high quality for the control circuit.
A. DFS Circuit Design
The proposed DFS technique consists of two circuits. The AVS mode is in charge of all loads conditions with the excep-tion of ultralight-load status controlled by the Green mode. The waveforms of the DFS are depicted in Fig. 7. When the power MOSFET turns ON, the sink current ID E T is proportional to
the line voltage VACsince VD E T is a reflected voltage of VAC.
Fig. 8. (a) AVS circuit. (b) Load conditions sensor. (c) Inhibit time is con-trolled by VF B and the corresponding timing diagram.
ID E T is capable of generating corresponding volume of current
to compensate the power during the on-time period. The second one is the valley detection during the off-time period. During the off-time period, ID E T is inversely proportional to Vdrain
be-cause the source of the transistor M1clamps VD E T to be lower
than the reference VR EF1about one MOSFET threshold voltage
Vthas depicted in Fig. 8(a). The lower Vdrainin Fig. 2, the larger
the ID E T. Therefore, the valley sensing signal VS equal to the
product of ID E T and R1 compares with the reference VR EF2
to determine each single valley of off-time periods. The inhibit time is inversely proportional to the feedback voltage VFB. The
INHIB changes from low to high at the beginning of the off time.
Then, VAV Scan be set to high to turn on the power MOSFET by
the AVS circuit after the INHIB is triggered to low by the load sensor.
Besides, the INHIB in Fig. 8(a) is a load-dependent signal which indicates the corresponding minimum off-time length under a certain load condition. The lower the load, the longer the
INHIB. The valley detector utilizes the reference voltage VR EF1
and the transistor M1 whose source connected to VD E T from
the auxiliary winding to generate a current-dependent voltage. VD E T swings to a negative voltage while the power MOSFET’s
drain voltage has the resonance phenomenon and tends toward the valley. Therefore, the lower the drain voltage, the more the sourcing current flows from M1. VD E T is clamped around 0.3 V
if VR EF1is 1 V to avoid negative voltage seen by the chip from
the possible hazard of the latch-up issue. In the meanwhile, the sourcing current is mirrored to flow through R1to produce the
Fig. 9. (a) Green mode circuit. (b) Timing diagram of the Green mode control.
sensing voltage VS. To choose a suitable reference voltage helps
catch every single valley during the off time.
The load sensor depicted in Fig. 8(b) is able to convert the feedback voltage VFB to the time duration, INHIB, which
in-dicates load current information. When VPW M changes from
high to low, the current source starts to charge C from VFB to
VR EF4as shown in Fig. 8(c). Therefore, smaller VFB indicates
smaller output loading but longer inhibit time. VR EF3 is set to
determine the minimum off time. Once the inhibit time is over, the valley detection signal VD is allowed to trigger the upper
side flip–flop to set VAV Shigh. Besides, the unpredictable value
of parasitic resistances in the LC resonant path causes resonant amplitude decaying so much that it is hard to detect especially under light-load conditions which has longer inhibit time. In order to avoid the aforementioned situation, another path com-posed of the lower side flip–flop cascaded with a 9 μs delay circuit can set the maximum off time. That is to say, if the sys-tem cannot detect any valley voltages excluding the first valley voltage within 9 μs when the INHIB changes from high to low, VAV S is set to high for getting a maximum off time. Therefore,
if the off-time exceeds maximum setting length, the controller turns on power MOSFET to guarantee the next on-time in case of the decaying valley voltage goes as much as it could.
The proposed Green mode has two advantages. One is to avoid the undesired scenario happening when the valley voltage is decaying so much that it is hard to be detected if off time length is too long to some extent. The other advantage is to further improve the ultralight-load efficiency due to the greatly reduced switching power loss. Fig. 9 shows the Green mode circuit to determine whether the off time is longer than 40 μs or not. Once the off time is longer than 40 μs, the system will enter the Green mode and the switching frequency is down to 2 kHz. When VPW Mbecomes low, VC Fstarts to be charged until
the hysteretic inverter changes its state. The charging period is designed around 40 μs. Thus, if the off-time period is longer than 40 μs, the Green mode signal VG M will become high to
Fig. 10. CCS technique.
with the frequency of 2 kHz at the next switching period as shown in Fig. 9(b).
B. CCS Circuit and UVLO Design
To achieve the constant current from VH V, the converter needs
a startup circuit with the CCS technique as shown in Fig. 10. An ultrahigh-voltage depletion N-type MOSFET M N1is used with
its gate and source shorted to function as one current source. The transistors M2, M3, M4, and M5form a negative feedback in a
closed loop. M2 and M3 are used as a differential pair. M4 is
used as a level shifter to ensure that M5can be fully turned ON.
The transistors M4 and M5 form a negative feedback path to
ensure the constant HV startup current because nearly constant voltage across D1 is produced. IH V charges one capacitor to
slowly ramp up the voltage VD D H to the system operational
voltage set at the value of 16 V. Eventually, VE N signal comes
from the UVLO circuit to shut down the HV startup for further power reduction.
The UVLO circuit is utilized for IC’s startup and autorecovery protection by detecting the supply voltage VD D H. The startup
procedure using the CCS technique charges VD D Hto 16 V so that
chip starts to work. Autorecovery protection protects the system against short circuit at Vout, undesired open feedback loop, and
any other system malfunctions. If any of the aforementioned condition occurs, the gate signal out of the controller would be ceased and VD D H starts to decrease. Once VD D H reaches
10 V, the HV preregulator will be shut down and no power supply would be sent to the controller. Besides, the UVLO circuit provides a hysteresis space, i.e., from 10 to 8 V, which can extend the restarting time to avoid the possibility of burning down issues caused by high temperature of whole system. The hysteresis window is determined by the time that the system needs to cool down.
Fig. 11 shows the UVLO circuit that has an ability to monitor VD D Hand based on different conditions to shut down or switch
on the controller and the CCS circuit. VE N is the enabled signal
to switch on the controller. VD D BG is the power supply for
the HV preregulator. The stacking components include zener diodes and NPN BJTs to detect the 16 and 8 V. It means that as soon as VD D H is higher than one extent, the voltage across the
resistor R1 is designed to be higher than the threshold voltage
of the transistor M1. Thus, the transistors M1− M3 turn ON
and VE N becomes high to shut down the CCS circuit with a
quiescent current of near 0 mA for power saving. At the same time, the transistor M7 is turned ON and the drain voltage is
Fig. 11. Operation of the UVLO circuit.
clamped by the zener diode Z3. Thus, VD D BGis derived by two
base–emitter voltages of bipolar subtracted from the clamping voltage for the LV biasing circuit.
To compare 10 V voltage, the right-side circuit of the UVLO circuit consists of M8, R5, R6, Z3, and the CMP. It utilizes R5
and R6 to obtain the divided VD D H. And the divided voltage
compares with the voltage of Z3. Consequently, when VD D His
lower than 10 V, S1turns OFF and VD D BGis pulled to ground,
which shut down the chip. Another comparison voltage is al-ready prepared because the turning ON M2 causes the left-side
stacking voltage becomes 8 V noted as Vc1. If VD D Hdecreases
below 8 V, the UVLO is shut down and VE N is sent to the CCS
circuit to restart the startup procedure. After the UHV start-up procedure, the axillary winding side supplies power to the whole chip continuously. According to the ratio between the secondary side and the axillary side, VD D H from the axillary side is 16 V,
which is around 0.8 times Vout.
C. Soft Start
During the power-on period, the resonant valley voltage is too small to be detected. Therefore, it needs a soft start period modulated by the oscillator (OSC) circuit until the valley voltage is large enough. In Fig. 12(a), the soft start circuit includes a 4-bit up-counting counter which controls four current sources to build the soft start voltage VS T across the resistor R1 with a small
voltage step increment. The operational amplifier (OP) functions as the unit gain buffer. That is to say, VFB is elevated with a
growing voltage step trails along VS T as shown in Fig. 12(b).
Here, the OP, the transistor M1, and the compensation capacitor
C1 act like a two-stage OP. VPW M has a switching period of
30 μs in the beginning of soft start until the valley voltage can be detected. The corresponding current sense signal VC S tracks
the variation of VFB. The soft start happens when the internal
power supply 5 V is ready. VS S O is a signal to show whether
the soft start is over or not.
D. Power Compensation Circuit
Fig. 13 shows how the current limit signal VP C is inversely
Fig. 12. (a) Soft start circuit. (b) Soft start procedure.
Fig. 13. Power compensation circuit.
proportional to VAC, the controller must have VIN information
in every switching cycle. Observing Fig. 2, VIN is the root
mean square value of VAC and will be reflected to the auxiliary
side when the power MOSFET turns ON. Due to the polarity between primary winding and auxiliary winding, the higher the VIN, the more negative the VAU X. It results in larger sink
current of ID E T. The power compensation circuit also uses the
current ID E T mirrored from Fig. 7(a) to get the input voltage
information. Consequently, the increasing input ac voltage VAC
will lead the decreasing of current limit voltage VP C. Besides,
VP C is limited between VR EF1 and VR EF2. The two voltages
are determined by the input voltage range, the resistance of current sense, and the switching period. Finally, for ensuring that the output power can be controlled, it compares VP C and
the current sense voltage VC S to limit the output current. If the
overcurrent occurs, VO C P will be triggered to shut down the
power MOSFET.
Fig. 14. Level shifter and the driver circuit.
E. Level Shifter and Driver
The driver circuit is depicted in Fig. 14. The transistors M1–
M2 and M3–M4 form the level shift circuit to convert VPW M
from the lower internal supply voltage VD Dto the higher supply
voltage level VD D H. The dead-time circuit can avoid the
shoot-through current. The transistors M5and M6are responsible for
driving the external power MOSFET. The zener diodes, Z1−Z3,
clamp the upper driver voltage at 18 V to avoid damage on the gate oxide.
IV. SYSTEMSTABILITYANALYSIS
Fig. 15(a) shows an equivalent small signal model based on the architecture in Fig. 2. Basically, it consists of two parts, control-to-output transfer function GC O and output-to-control
transfer function GO C [20]–[24]. The output voltage Vout is
the product of the averaged secondary-side current Is avg and
the output impedance Zout which includes the output filter,
related parasitic resistor, and output resistor RL. As depicted in
Fig. 15(b), Is avg is the integral of the secondary-side current
Iswithin one switching cycle as shown in
Is avg = 1 2 · (tdis· Is pk) 1/f (V FB) . (6)
tdis is the discharging time of secondary-side current. Is pk
is the peak value of the secondary-side discharging current. 1/f(VFB) represents that the switching frequency f is the
func-tion of VFB. The switching period, the reciprocal of the
switch-ing frequency, can be approximated to a linear function in (7) controlled by the feedback voltage VFB in the valley selection
mode as depicted in Fig. 4(b) where K is a constant value f (VFB) = K· VFB+ C where Cis a constant value. (7)
Then, tdis, Is,pk, and toncan be expressed as
tdis = Is pk· LP Vout· N2 (8) Is pk = Vin LP · ton· N (9) ton = VFB· LP Vin · 1 RC S . (10)
Fig. 15. (a) Equivalent small signal model of the proposed flyback converter. (b) Waveforms of the flyback converter with the DFS technique. (c) Comparison of the derived frequency response and the measured frequency response.
Substituting (8)–(10) into (6), Is avgcan be expressed as the
function of the output voltage Vout, the feedback voltage VFB,
the inductor LP, and the sensing resistor RC S as shown in
Is avg=
(K· V3
FB+ C· VFB2 )· LP
2· Vout· R2C S
. (11)
The averaged secondary-side current is, in general, a nonlin-ear function of the converter voltages and currents. Linnonlin-earization at the quiescent operating point can derive the small ac current variation of the secondary side as expressed in
ˆ
Is avg = a1· ˆVFB+ a2· ˆVout where ⎛ ⎝a1 = ∂ Is a v g ∂ VF B = (3K·V2 F B+ 2C·VF B)·LP 2·Vo u t·R2C S a2 = ∂ I∂ Vso u ta v g = −(K ·V3 F B+ C·VF B2 )·LP 2·V2 o u t·R2C S ⎞ ⎠ . (12) The small ac current variation at the secondary side flowing through the impedance Zoutdetermines the perturbation of Vout
as expressed in ˆ
Vout= ˆIs avg· Zout=
a1· ˆVFB+ a2· ˆVout
· Zout. (13)
Coutand its equivalent series resistor (ESR) Resr contribute
one ESR zero at high frequencies. And the pole can be seen as the combination of Coutand the equivalent loading resistance
RL. As illustrated in Fig. 15(a), TL431 and optocoupler acting
like the error amplifier and voltage-to-current transconductance amplifier, respectively, in the feedback loop. Thus, the output-to-control transfer-function GO C(s) can be derived in
GO C(s) = ˆ VFB ˆ Vout =αRpull RC · (1 + sRf b1CC) sRf b1CC(1 + sRpullCF) . (15) Hence, the proportion integral compensator with a transfer function GO C(s) that contains two poles and one zero ωZ 1
can used as the compensator. One of the compensation poles is at origin and the other is at high frequencies. Besides, the compensation zero ωZ 1in GO C(s) should be close to the pole
ωP 2 in GC O(s) to achieve pole-zero cancellation by choosing
appropriate passive components. Thus, the pole in GO C(s) at
the origin becomes the dominant pole of the whole system. The high-frequency compensation pole ωP 1 in GO C(s) is used to
alleviate the effect of the high-frequency ESR zero ωZ 2 for
better high-frequency noise rejection. After the compensation, the system transfer function T (s) is shown in
T (s) = GC O(s)GO C(s) = αRpulla1 RC(1/RL − a2)· 1 + sCoutResr sRf b1CC(1 + sRpullCF) . (16) The bandwidth is designed about 3 kHz which is far away from the switching frequency as shown in Fig. 15(c).
V. EXPERIMENTALRESULTS
The proposed flyback converter with the DFS technique and the CCS circuit was implemented in 0.5 μm 500 V UHV process. The chip micrograph with an active area of 3.6 mm2 is shown
in Fig. 16(a). The prototype is shown in Fig. 16(b). The range of input ac source is 90–264 VACand Voutis 19 V. The primary
inductance of transformer is 700 μH. The winding ratio Lp:
Ls: Lais 35T: 5T: 4T. The error amplifier and optocoupler are
TL431 and PC817, respectively. Detailed design specifications are listed in Table I.
The estimated frequency response is consistent with the cal-culated frequency response as shown in Fig. 15(c). Fig. 17 shows ultrahigh-voltage startup mechanism provided by the CCS cir-cuit. IH V remains constant current of 1.2 mA until VD D H is
higher than 16 V. The autorecovery function provided by the CCS circuit with the UVLO is shown in Fig. 18 by shorting Voutto ground to trigger the restart protection. Fig. 5 shows the
Fig. 16. (a) Chip micrograph. (b) Prototype of the QR-PWM flyback converter. TABLE I
DESIGNSPECIFICATIONS
Fig. 17. Waveforms of the CCS circuit with the UVLO circuit. (at VA C =
110 V).
Fig. 18. Waveforms of the autorecovery function (at VA C= 110 V).
Fig. 19. Measurement results of the DFS under different load conditions (at
VA C = 110 V and Vo u t = 19 V). (a) IL O A D = 5 A. (b) IL O A D = 1 A.
(c) IL O A D= 100 mA.
The proposed DFS that operates with different loads is de-picted in Fig. 19. Fig. 19(a) shows the first valley turns on the power MOSFET at the heavy load of 5 A. The fifth valley is chosen to turn ON the power MOSFET at the load of 2 A in Fig. 19(b). Obviously, the decreased switching frequency can effectively improve the efficiency. Once the system has an ul-tralight load, the system enters the Green mode with an off time of 500 μs as shown in Fig. 19(c). Comparison of conversion ef-ficiency between conventional and proposed methods is shown in Fig. 20. The performances make great strides especially at light loads. The efficiency can achieve about 85% at light load of 5 W when VAC is 90 V, and peak efficiency is near 92% at
load of 80 W when VAC is 264 V.
The comparisons between the proposed flyback converter and prior arts are listed in Table II. The efficiency is improved es-pecially at light load because of the proposed DFS and CCS
Fig. 20. Power conversion efficiency of the proposed and conventional meth-ods with the input ac source VA C = 90 and 264 V.
methods. Consequently, the conversion efficiency is better than those of the prior arts.
VI. CONCLUSION
To achieve a high efficiency flyback converter with minimized external components, the proposed DFS technique dynamically chooses one suitable valley voltage in the resonance to extend the switching period. Therefore, the converter automatically switches to the DCM operation and thus reduces the switch-ing frequency for higher efficiency at light loads. Especially, the system operating in the Green mode can further reduce power loss at ultralight loads. Besides, the CCS circuit can improve efficiency since the leakage path of the startup circuit can be completely turned OFF. The test chip fabricated in VIS 0.5 μm 500 V UHV process occupies an active silicon area of 3.6 mm2.
The peak efficiency and the light-load efficiency are 92% and 85%, respectively.
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Yu-Chai Kang was born in Yilan, Taiwan. He re-ceived the B.S. degree from the Department of Elec-trical Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he is currently working to-ward the M.S. degree.
He is a Member of the Mixed-Signal and Power Management IC Laboratory, National Chiao Tung University. He is currently involved in low power en-ergy harvesting system and power management cir-cuit design. His research interests include the power management IC design, analog integrated circuits, and mixed signal IC design.
Chao-Chang Chiu received the B.S. degree from Fu Jen Catholic University, Taipei, Taiwan, in 2008, and the M.S. degree from the Department of Electrical Engineering, National Central University, Taoyuan, Taiwan, in 2010. He is currently working toward the Ph.D. degree at the Institute of Electrical Control En-gineering, National Chiao Tung University (NCTU), Hsinchu, Taiwan.
He is a Member of the Mixed-Signal and Power Management Integrated Circuit Laboratory, Institute of Electrical Control Engineering, NCTU. His cur-rent research interests include the power management integrated circuit designs and analog integrated circuit designs.
Moris Lin was born in Taipei, Taiwan. He received the B.S. degrees from Fu Jen Catholic University, Taipei, Taiwan, in 2007, and is currently working to-ward the M.S. degree in the Department of Electrical and Control Engineering, National Chiao Tung Uni-versity, Hsinchu, Taiwan.
He is a Faculty Member of the Mixed-Signal and Power Management IC Laboratory, Department of Electrical and Control Engineering, National Chiao Tung University. His current research interests in-clude power management integrated circuit design and analog integrated circuits.
Chih-Pu Yeh was born in Taipei, Taiwan, in 1987. He received the B.S and M.S. degrees from the De-partment of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2010 and 2012, respectively.
He is a Member of the Mixed-Signal and Power Management IC Laboratory, National Chiao Tung University. His research interests include the power management IC design.
Jinq-Min Lin received the B.S. degree in physics from National Taiwan University, Taipei, Taiwan, in 1981, and the M.S. and Ph.D. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 1983 and 1997, respectively.
From 1984 to 1989, he served the military RDSS service in ERSO/ITRI, Taiwan, as a Device and Test Engineer. From 1989 to 1994, he was a Project Leader of device and test function of ERSO/ITRI’s submi-cron program. In 1994, he joined Vanguard Interna-tional Semiconductor Corporation (VIS), Hsinchu, as a Manager of IT technology and Product Control Manager. He has been working on several generations of CMOS RF process development and PDK creation projects in VIS. He is currently a Department Manager in charge of high voltage/current device test methodology and power management IC/analog/RF test vehicles with high-voltage, high-current, and high-frequency operation. His research interests include RF integrated circuits, advanced technology test ve-hicles, and high power test methodology.
Ke-Horng Chen (M’04–SM’09) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a part-time IC De-signer at Philips, Taiwan. From 1998 to 2000, he was an Application Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Manager at ACARD, Ltd., where he was involved in designing power management ICs. He is currently a Professor in the Department of Electrical Engineering, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coauthor of more than 100 papers published in journals and conferences and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm, and driver designs of liquid crystal display TV, red, green, and blue color sequential backlight designs.
Dr. Chen has served as an Associate Editor of the IEEE TRANSACTIONS ON POWERELECTRONICSand IEEE TRANSACTIONS ONCIRCUITS ANDSYSTEMS— PARTII: EXPRESSBRIEFS. He also joins Editorial Board of Analog Integrated Circuits and Signal Processing from 2013. He is on the IEEE Circuits and Systems (CAS) VLSI Systems and Applications Technical Committee, and the IEEE CAS Power and Energy Circuits and Systems Technical Committee. He joins Society for Information Display and International Display Manufacturing Conference Technical Program Subcommittees. He is the Tutorial Co-chair of IEEE Asia Pacific Conference on Circuits and Systems (2012). He is the Tack Chair of Integrated Power Electronics of IEEE International Conference on Power Electronics and Drive Systems 2013. He is a Technical Program Co chair of IEEE International Future Energy Electronics Conference 2013.
