A Power Cloud System (PCS) for High Efficiency
and Enhanced Transient Response in SoC
Chun-Jen Shih, Kuan-Yu Chu, Yu-Huei Lee, Student Member, IEEE, Wei-Chung Chen, Student Member, IEEE,
Hsin-Yu Luo, and Ke-Horng Chen, Senior Member, IEEE
Abstract—Tradeoff between power efficiency and transient per-formance usually comes out during the design consideration of a power module. A configurable power supplying implementation named as the power cloud system (PCS) is proposed to handle different load conditions for simultaneously improving the power efficiency and the transient response in order to meet the system-on-chip (SoC) requirements. At heavy loads, the switching reg-ulator takes over the energy delivery scheme in the PCS with the fast transient technique. An auxiliary power unit, which acti-vates hybrid operation in both medium and light loads, can realize the low-dropout (LDO) regulator to provide a supplementary en-ergy immediately in transient duration and be the high-side power switches of the switching regulator to minimize the power loss. Be-sides, owing to its low quiescent current of an LDO regulator, it can directly operate under the ultralight-load condition. Therefore, the satisfactory power conversion efficiency and the load transient re-sponse can be derived over a wide load range, which will certainly meet the power requirement for different operated functions in the SoC. The chip was fabricated by a 0.25-μm CMOS process, and the experimental results show the improvements of 56% transient dip voltage and 25% transient recovery time in hybrid operation, as well as a peak efficiency of 94%.
Index Terms—Auxiliary power unit (APU), hybrid operation, power cloud system (PCS), power conversion efficiency, power module, system-on-chip (SoC), transient response.
I. INTRODUCTION
H
IGH-PERFORMANCE power management has been anessential part in today’s system-on-chip (SoC) integra-tion. The complex system operation needs the adequate power supply function to further enhance its performance. Thus, the correct operation function and the lengthened battery life can be achieved, especially in the portable electron device applications. In the common power distribution scheme of the SoC system, a power controller can indicate the demand of core voltage or
Manuscript received January 31, 2012; revised May 13, 2012; accepted June 22, 2012. Date of current version October 12, 2012. This work was supported in part by the National Science Council, Taiwan, under Grant NSC 101-2220-E-009-047, Grant NSC 101-2220-E-009-052, and Grant NSC 101-2622-E-009-004-CC2; in part by the Industrial Technology Research Institute (ITRI), Taiwan under Project B301AR2M50; and in part by the Metal Industries Research and Development Centre and Ministry of Economic Affairs, Taiwan, under Grant 101-EC-17-A-01-1010. Recommended for publication by Associate Editor Y.-F. Liu.
C.-J. Shih, K.-Y. Chu, Y.-H. Lee, W.-C. Chen, and K.-H. Chen are with the Institute of Electrical Control Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (e-mail: khchen@cn.nctu.edu.tw).
H.-Y. Luo is with the Metal Industries Research and Development Centre, Taiwan.
Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPEL.2012.2207917
Fig. 1. (a) Embedded power module in SoC. (b) Illustration of the energy demands provided by a power module for different system operation functions in SoC.
other energy requirements according to the different system op-eration scheme [1]–[3]. Dynamic voltage scaling (DVS) [4]–[6] is also a popular energy modulation scheme provided by a power module, which manages the power distribution according to the indication of the SoC system. Fig. 1 shows the illustration of the energy demand in SoC with the distinct operation functions and the required energy consumptions. The embedded power module in SoC, which is generally implemented through the switching regulators [7]–[12] or the low-dropout (LDO) regu-lators [13]–[15], can provide a regulated supply voltage. How-ever, the load current condition of the power module in the SoC would be varied rapidly. The high power conversion efficiency and the satisfactory load transient performance along with the wide load range are considered as the critical design issues. The inductor-based switching regulator has the capability to drive the large load current with good power conversion efficiency, but derives the efficiency deterioration at light loads and the slow load transient responses. The LDO regulator can provide the rapid transient response; nevertheless, it is hard to extend its load current range and will carry out the poor power con-version efficiency. In addition, the voltage recovery reaction is obtained after the occurrence of load current variation in conven-tional power module implementation. Hence, the resultant slow
Fig. 2. Idea illustration of the PCS. (a) Relationships between the different supply mechanisms for achieving a proper power module for the SoC system. (b) PCS operation under different load conditions.
transient response and the large voltage dip will be derived, which might cause the incorrect function in the SoC and needs to be minimized.
As the trend of advanced power consideration, the system processor can determine the energy demand and send the energy requests to the power module by a master power controller. Thus, the proposed power module for SoC applications is implemented as the power cloud system (PCS) as shown in Fig. 2, which can vary the structure of the power module according to the different power demand as well as the load current conditions in the SoC system. Fig. 2(a) indicates the relationship between the different supply mechanisms in the PCS, which are directed by the master power controller in the SoC. The core processor in the SoC is mainly supplied by the switching regulator or the LDO regulator with a regulated VD D core voltage to guarantee its correct function. However, to obtain high power conversion efficiency and good load transient response in the power module, the supply mechanism should be effectively organized according to variable load conditions. There are some existing functional power clouds, which can be reorganized as the tradeoff between power conversion efficiency and transient response over a wide load range. Specially, the implementation of auxiliary power unit (APU) can help strengthen the driving capability of the switching regulator, as well as enhance load transient response through the realization of the LDO regulator [16].
The illustration of PCS operation with the different load con-ditions is shown in Fig. 2(b). When the SoC requires larger energy, the PSC will provide higher driving current through the pure switching regulator operation to guarantee the power conversion efficiency. In addition, the APU is activated to be-have as a switching regulator at this instant condition. The fast transient technique, which regards the unobvious power
con-Fig. 3. Architecture of the proposed PCS.
sumption compared to the high current supply at the output, is also utilized to speed up the load transient response and derive the small transient dip voltage. On the other hand, the hybrid operation is activated at both medium and light loads. That is, the APU acts as the switching regulator in steady state, whereas it can be realized as the LDO regulator during the load tran-sient period since the LDO regulator equips the larger loop bandwidth compared to that of the general switching regulator design. That is, the utilization of fast transient technique may be inappropriate due to it apparent current consumption. As a result, the issues of power conversion efficiency and load tran-sient response can be taken into consideration simultaneously. As the load decreases, the LDO regulator, which is achieved by the APU only, takes over the complete supply function in the PCS at ultralight loads to retain the regulated output voltage. The small power consumption in the LDO can maintain the effi-ciency since the power loss consumed by a switching regulator grows into a relatively high portion at ultralight loads. That is to say, the PCS can determine which of the small power clouds need to be included at one specific load condition through the demand from the SoC, so as to guarantees the power conversion efficiency and the operation of load transient response over a wide load range.
This paper is organized as follows. The proposed PCS op-eration is illustrated in Section II. System stability analysis is described in Section III. Circuit implementations and experi-mental results are shown in Sections IV and V, respectively. Finally, a conclusion is made in Section VI.
II. OPERATION OF THEPCS
Fig. 3 shows the architecture of the proposed PCS. To prop-erly regulate the output voltage Voutfor supplying the SoC, the control loops recognized as the switching control loop and the linear control loop can realize the distinct energy supply topolo-gies according to different system requirements. The switch-ing regulator contains the high-side power switch MP and the
low-side power switch MN to deliver energy from the battery input VIN to Vout with the utilization of off-chip inductor. Be-sides, the APU can serve as the high-side power switch MA PU, which is operated in parallel with MP to enhance the driving ca-pability of a switching regulator at heavy loads, or regard as the pass device in the linear regulator to strengthen the load transient response and to assure the energy driving function at ultralight loads. That is, the PCS achieves the proper power module re-alization in the SoC, which is derived under the demand. As a result, the energy on-the-fly function is deservedly carried out that depicts the advantages of power module integration in the SoC.
A. High Power Demand in SoC (Heavy-Load Condition)
When the SoC activates the operation such as the high-speed data transmission or the complex signal processing as shown in Fig. 1, the power module will receive the request of high power demand. Thus, the PCS will form the switching regulator owing to its high driving capability. As shown in Fig. 4(a), a current-mode buck operation is achieved through the switching control loop at heavy loads. By referring the detailed control circuits illustrated in Fig. 3, the error amplifier EA1, which is imple-mented with the high gain structure by using the cascode output stage, can maintain the high loop gain for good output voltage regulation and can generate the error signal VEA 1 for deciding duty cycle. The current sensing mechanism helps achieve the current-mode control while the system stability can be guar-antee by the proportional integral (PI) compensation, which is achieved by compensation resistance RC and compensation ca-pacitance CC. The fast transient technique is also implemented to dynamically adjust the system compensation scheme [17] in order to accelerate the load transient response in the current-mode buck converter operation. The PWM generator and driver produce the control signals of VG P and VG N to drive the MP and the MN, respectively. The zero current adjusting (ZCA) circuit can eliminate the negative inductor current by compen-sating the effect of nonideal offset and the propagation delay. In addition, the MOSFET MA PUof APU, which is set in parallel with MP in Fig. 4(a), works as a part of high-side power switch under the heavy-load condition It can enhance the driving capa-bility through the enlarged power switch size to minimize the conduction loss in power stage.
B. Regular Energy Requirement in SoC (Medium- and Light-Load Conditions)
To enhance the transient operation and derive the good power conversion efficiency at both medium and light loads, the PCS enables the hybrid operation for the power module as shown in Fig. 4(b). In steady state, the APU can act as the high-side power switch of a buck converter to minimize power loss. The gate drive voltage of MA PU is connected to the driving signal
VG P that activates the pure switching regulator operation with the step-down function. However, the transient response of a switching regulator is still restricted by the switching control loop and the off-chip inductor. To properly enhance the transient response for minimizing the drop voltage and shortening the
Fig. 4. Proposed PCS operation under the different load conditions for the SoC. (a) Heavy-load condition. (b) Medium- or light-load conditions. (c) Ultralight-load condition.
recovery time, the linear control loop with APU can realize the goal thought the utilization of the LDO regulator. It can carry out the superior transient operation during the load transient period owing to its larger system bandwidth compared to switching regulators, which typically limit the system bandwidth within only 10–20% of switching frequency. That is, the APU will be the power switch along with MP of a buck converter in steady state, and acts as the pass device of LDO when the load transient occurs with the hybrid operation.
The hybrid operation exhibits through the indication of hy-brid setting circuit after receiving the demand of increased load from the power controller in SoC. The control signal VPM Scan
inform MA PU to behave as a linear regulator and wait for the load variation before the coming of step-up load transient. Con-sequently, the transient dip voltage can be alleviated and the transient response time can be shortened. As depicted in Fig. 3, the error amplifier EA2 and the low-output-impedance (LOI) buffer are used to modulate the gate control signal VPL for the pass device MA PUin order to derive the adequate system loop gain and to ensure the system stability. Moreover, the current
IM C can help move the load current driving from the LDO reg-ulator to the switching regreg-ulator at the end of the load transient period. That is, the replica current IM C, which is proportional to the current flowing through MA PU, will charge the compen-sation capacitance CC in the switching control loop and raise the voltage level of VEA 1for increasing the driving capability of a buck converter. Thus, the load driving provided by the LDO regulator will be decreased so as to enhance the power conver-sion efficiency. When the output voltage is regulated to its rated value, the APU will be switched back and thereby being the power switch for the pure buck operation. VS, which is propor-tional to the current flowing through MA PUin the LDO, can be used to end the LDO regulator operation as well as the transient response with the hybrid setting circuit. As a result, this hybrid operation can guarantee an improved transient response with a low dip voltage as well as the decreased transient recovery time, and more specifically, can properly handle the upcoming load variation in the SoC. In steady state, the APU can also help enhance the driving capability and the power conversion efficiency.
C. Silent Mode Operation in SoC (Ultralight-Load Condition)
The silent mode operation is the commonly used methodolo-gies in the SoC to minimize the power dissipation. The power consumption will be decreased below 1 mA [1] in the silent mode, which is improper to utilize the switching regulator as the power module due to its deserved power loss. Thus, the LDO regulator becomes a good candidate at ultralight loads. As shown in Fig. 4(c), MA PU behaves as a pass device of LDO to regulate the output voltage along with the linear control loop that monitors the output load condition and generates the gate control signal VPL for MA PU. Therefore, not only the output voltage regulation can be ensured, but also the power conver-sion efficiency at ultralight loads can be guarantees by the PCS controlled power module.
III. STABILITYANALYSIS OF THEHYBRID
OPERATION IN THEPCS
The proposed PCS forms the different supply mechanism ac-cording to the different load conditions. The switching regulator in the PCS is implemented with the current-mode buck con-verter, which generates a load-dependent system pole at output. The PI compensator can be utilized to stabilize its operation by inserting a pair of compensation pole and zero [17]–[19]. However, the hybrid operation is activated under both medium-and light-load conditions with an upcoming load transient re-sponse. That is, the switching regulator and the LDO regulator simultaneously supply power to the SoC system. Thus, the
sta-Fig. 5. Equivalent small-signal model of the hybrid operation in the proposed PCS.
bility of the hybrid operation needs to be carefully considered to guarantee the smooth load transient response.
Fig. 5 shows the small-signal illustration of the hybrid oper-ation in the PCS. By breaking up the feedback loop, the system loop gain can be derived to demonstrate the system stability. The error amplifier in the switching control loop provides the transconductance Gm , SW and the output resistance Roto ensure the high dc voltage gain. The current sensing implementation, which conveys the inductor current information into the con-troller, can be modeled as the sensing resistance RIS. Fm 1and
Fm 2 are the transferring coefficients of the analog-to-digital conversion for determining the operated duty cycle in the buck converter. In addition, the transfer function of the PI compensa-tion with the error amplifier is illustrated in
vc vf b Sw itching = Gm ,SWRo 1 + sCCRC 1 + sCC(RC + Ro) = Av ,SW 1 + (s/ωz) 1 + (s/ωp) . (1)
CC and RC generate the compensation pole ωpand the com-pensation zero ωz, which is regarded as the system dominant pole and is used to extend the system bandwidth by canceling the effect of system load-dependent pole at output, respectively, in the pure buck converter operation. The loop gain of the switch-ing buck converter can be shown as
LSW(s) = vf b vf b Sw itching = RF 2 RF 1+ RF 2 ×Gm ,SWRo(1+sCCRC) 1+sCC(RC+Ro) RL(1+sCLRESR) RI S(1+sCLRL) . (2)
In addition, the LDO regulator in the proposed PCS is im-plemented with an inserted buffer stage that aims to guaran-tee stable operation. The error amplifier in the linear control loop can monitor the output voltage variation by generating the
transconductance Gm , LR. The LOI buffer stage carries out the output resistance Ro2and the parasitic gate capacitance Cp1 to separate the nondominant poles. The APU forms as the pass transistor in the LDO regulator to provide the transconductance
Gm , A PU, which varies according to the driving condition of the LDO regulator. The loop gain of the LDO regulator is shown in
LLR(s) = vf b vf b Linear = RF 2 RF 1+ RF 2 × Gm ,LRRo1Gm ,A PURL(1+sCLRESR) (1+sCp1Ro1)(1+sCp2Ro2)(1+sCLRL) . (3) Through the combination of the switching control loop and the linear control loop, the hybrid operation in the PCS can be activated. With the sensing mechanism to generate the current
IM C shown in Fig. 3 for transferring the current from the LDO regulator to the switching buck converter, the signal path with the transconductance Gm , A PU/K needs to be included in the stability analysis of the hybrid operation. The transfer function of the feedback node to the control signal of the switching buck converter is depicted in vc vf b H ybrid = Gm ,SWRo (1 + sCCRC) 1 + sCC(RC + Ro) + Gm ,LRRo1(Gm ,A PU/K)Ro3 (1 + sCp1Ro1)(1 + sCp2Ro2)(1 + sCCRo3) . (4) The factor K is the current sensing ratio between the current of the LDO regulator and IM C. Therefore, the transfer function of the dual loop integration is shown in (5), at the bottom of this
page, and thus the loop gain of the PCS in hybrid operation is illustrated in (6), shown at the bottom of this page.
The dc voltage gain in the hybrid operation is contributed by both the switching loop and the linear loop. The illustration of the poles and zeros in the hybrid operation is shown in
LH B(s) = vf b vf b = RF 2 RF 1+ RF 2 × RL RI S Gm ,SWRo+ Gm ,LRRo1 × Gm ,A PU K Ro3+ Gm ,A PURI S × 1 + s ωz 1 1 + s ωz 2 1 + s ωE S R 1 +ωs p 1 + ωs p s 1 +ωs p a 1 +ωs p h 1 1 +ωs p h 2 . (7) The pole ωpgenerated by the PI compensator is located at the low-frequency region as the system dominate pole. The com-pensation zeros, ωz 1 and ωz 2, can be used to cancel the effect of output load-dependent system pole ωpsand the nondominate pole ωpa at the sensing path of the current IM C. Fig. 6 shows the frequency response of the hybrid operation in the PCS. The system bandwidth can be enlarged in the hybrid operation, so as to minimize the voltage drop at the output node. With the change of K, the locations of the compensation zeros are varied. That is, compared with the pure buck operation, the different utiliza-tion of K results in the distinct system phase margin, which affects the system stability. The utilization of a smaller factor of
K indicates the larger of the sensing current IM C, and thereby the worse of the system phase margin. In addition, the non-dominant poles, ωph1and ωph2, which are carried out from the LOI buffer in the LDO regulator, are put at high frequency, so the system phase margin will not be deteriorated. As a result, the stable hybrid operation can be guaranteed that achieves the
vout vf b H ybrid = ⎡ ⎢ ⎢ ⎢ ⎢ ⎣ Gm ,SWRo(1 + sCCRC) 1 + sCC(RC + Ro) + Gm ,LRRo1 Gm , A P U K Ro3 (1 + sCp1Ro1)(1 + sCp2Ro2)(1 + sCCRo3) RL(1 + sCLRESR) RI S(1 + sCLRL) + Gm ,LRRo1Gm ,A PURL(1 + sCLRESR) (1 + sCp1Ro1)(1 + sCp2Ro2)(1 + sCLRL) ⎤ ⎥ ⎥ ⎥ ⎥ ⎦ ≈ (1 + sCLRESR) ⎡ ⎣ RL RI S Gm ,SWRo(1 + sCCRC)(1 + sCCRo3) + Gm ,LRRo1 Gm ,A PU K Ro3(1 + sCCRo) + Gm ,LRRo1Gm ,A PURL(1 + sCCRo)(1 + sCCRo3) ⎤ ⎦ (1 + sCLRL)(1 + sCCRo)(1 + sCCRo3)(1 + sCp1Ro1)(1 + sCp2Ro2) (5) LH B(s) = vf b vf b ≈ RF 2 RF 1+ RF 2 × RL RI S Gm ,SWRo+ Gm ,LRRo1 Gm ,A PU K Ro3+ Gm ,A PURI S × (1 + sCLRESR) ⎡ ⎢ ⎢ ⎢ ⎢ ⎣ 1 + sGm ,SWRoCC(RC+ Ro3) + Gm ,LRRo1 Gm , A P U K Ro3CCRo+ Gm ,LRRo1Gm ,A PURI SCC(RC+ Ro3) Gm ,SWRo+ Gm ,LRRo1Gm , A P UK Ro3+ Gm ,LRRo1Gm ,A PURI S + s2Gm ,SWRoCCRCCCRo3+ Gm ,LRRo1Gm ,A PURI SCCRoCCRo3 Gm ,SWRo+ Gm ,LRRo1Gm , A P UK Ro3+ Gm ,LRRo1Gm ,A PURI S ⎤ ⎥ ⎥ ⎥ ⎥ ⎦ (1 + sCLRL)(1 + sCCRo)(1 + sCCRo3)(1 + sCp1Ro1)(1 + sCp2Ro2) (6)
Fig. 6. Simulated frequency response of the proposed PCS in the hybrid operation (IL o a d= 200 mA).
Fig. 7. (a) Schematic of the LDO regulator in the PCS. (b) Loop gain of the LDO regulator.
enhanced transient response for providing a satisfactory supply in the SoC.
IV. CIRCUITIMPLEMENTATION
A. LDO Regulator With the LOI Buffer
The LDO regulator in the PCS can be activated under both hybrid operation and ultralight-load conditions. Fig. 7(a) shows the schematic of the LDO regulator, which contains the linear control loop and the pass device MA PU as depicted in Fig. 3. EA2 provides the transconductance gm 1 and the output resis-tance of Ro1 in Fig. 7(b). However, due to the use of a large off-chip filter capacitor CL, the loop dominate pole must be put at the output node. A low-frequency nondominate pole, which would appear at the gate of the pass device VPLwithout the LOI buffer, will degrade the loop stability. Thus, the proposed LOI buffer is designed to generate a small output resistance Ro2for
separating the nondominate pole as the separate high-frequency poles to obtain the satisfactory loop phase margin.
The LOI buffer also helps enhance the slew rate of the error amplifier and the system bandwidth due to its small input gate capacitance compared to the pass transistor. In the conventional design, using a bipolar transistor reduces the output impedance of a buffer stage to guarantee the system stability [14]. Nev-ertheless, the additional cost is required owing to the NPN bipolar utilization. The proposed LOI buffer constitutes a super source follower structure [20] through the utilization of double shunt feedback loops, which are formed through MU 1–MU 2 and MU 1–MU 3–MU 4, that can effectively reduce the output re-sistance Ro2 derived at the gate of pass device VPL as shown in
Ro2 ≈
1
gm U 1gm U 2roU 1+ gm U 1gm U 3gm U 4roU 1roU 4
. (8) Here, gm U 1–gm U 4and roU 1–roU 4are the transconductance and the intrinsic resistance of MU 1–MU 4, respectively. The im-plementation is similar to the flipped voltage follower struc-ture [20], so Ro2can be noticeably decreased without requiring high current consumption or a large aspect ratio of MU 1. The loop gain of the LDO regulator is derived in (9) from the de-piction of Fig. 7(b). gm 1and gm , A PUare the transconductances of EA2and MA PU, respectively. Ro, passis the equivalent resis-tance of a pass device while RL represents the load resistance at the output. Cp1 and Cp2 are the parasitic capacitances de-rived at nodes VEA 2 and VPL, respectively. The loop stability can be assured since the nondominate poles can be put at high frequencies through the proposed LOI buffer
LLD O(s) = vf b vf b ≈ RF 2 RF 1+ RF 2 × gm 1Ro1gm ,A PURoL(1 + sCLRESR) (1 + sCp1Ro1)(1 + sCp2Ro2)(1 + sCLRoL) where RoL = RL||Ro,pass||(RF 1 + RF 2). (9)
B. Hybrid Setting Circuit
Fig. 8 shows the hybrid setting circuit, which generates the control signals Vsw 1, Vsw 2, and Sel to realize the supply mecha-nism in the PCS through the indication of two-bit signal VPM S from the SoC. As shown in Fig. 8(a), the hybrid operation oc-curs when the PCS receives the positive trigger of VPM S[0] along with the setting on VPM S[1]. The APU will behave as the pass device for the LDO regulator, and thereby waiting for the upcoming load transient response. However, to enhance the power efficiency in the PCS, the LDO regulator should be shut down in steady state excepting for the ultralight-load condi-tion. That is, when the sensing signal VS, which conveys the current information of the pass device in the LDO, becomes smaller than a predefined reference voltage VR L, the APU will be switched back as the power switch for the buck converter. Furthermore, the offset-canceled (OFC) comparator, which con-tains the two-stage amplifier with two-phase operation and is used to guarantee this handover operation at the end of load transient response, is shown in Fig. 8(b). Phase 1 only activates
Fig. 8. (a) Schematic of the hybrid setting circuit. (b) Schematic of the OFC comparator and its brief operation.
with the pure switching regulator operation, while phase 2 is en-abled when hybrid operation occurs. The first stage is regarded as the preamplifier to amplify the realistic voltage difference of the effective input signals.
Two flying capacitors, C1and C2, can be used to record the offset voltage, which is resulted from the realistic mismatch after the chip manufacturing. Fortunately, the offset voltage can be canceled though these stored charges in phase 2. The second stage is then be implemented with a well-known com-parator structure to determine the optimal handover point at the end of hybrid operation. Therefore, the hybrid operation can be ended; nevertheless, it guarantees the high efficiency operation in steady state since the switching regulator can handle all of the energy delivery for outputs and is waiting for the next hy-brid activation. Moreover, the pure buck operation and the LDO operation in the PCS are activated at heavy loads and ultralight loads, respectively. These operations are indicated by the sig-nal VPM S[0] when VPM S[1] is fixed to low. Summaries of the proposed hybrid setting circuit are listed in the attached table of Fig. 8(a).
C. ZCA Circuit
To properly guarantee the power conversion efficiency un-der the steady-state light-load condition, the discontinuous-conduction-mode (DCM) operation can be realized along with the pulse frequency modulation (PFM) to obtain the reduced power loss in the buck converter. That is, for preventing the
Fig. 9. (a) Schematic of the proposed ZCA circuit. (b) Time diagram of the up-counting operation. (c) Time diagram of the down-counting operation.
occurrence of inversed inductor current, the low-side power switch needs to be turned OFF once the inductor current de-creases to zero. In the prior implementation of zero current detection [21]–[23], a simple comparator is used to determine the operation by directly modulating the voltage variations of switching node VX. However, the offset voltage of a comparator and the propagation delay of a driver in power stage will post-pone the turned-off operation on the low-side power switch, which results in the negative inductor current and the degra-dation of power conversion efficiency at light loads. Thus, to derive the optimal operation of zero current detection in the PCS, the proposed ZCA circuit is shown in Fig. 9(a). By mon-itoring the voltage variation on switching node VX, the output of the comparator will trigger the up/down counter so that the reference voltage level VR ZC generated by a resistor string can be adjusted to track the optimal zero current switching point.
If the zero current detection is activated too early, the low-side power switch will be disabled with a positive inductor current. That is, the parasitic diode of the low-side power switch will be turned ON automatically to conduct the inductor current as shown in Fig. 9(b). VP and VN are the control signals for power switches in the switching control loop generated by the PWM generator in Fig. 3. VX can be pulled to a negative volt-age value with a conductive drop voltvolt-age of a parasitic diode, which is typically about 0.7 V. When the output of comparator
VD T sets a positive trigger, which represents the detection of zero inductor current during the low-side power switch turn-on period, ZC will be enabled to turn OFF the low-side power switch by VN Z. Besides, the appearance of negative voltage on
VX leads the comparator to output a negative trigger to set the up/down counter through UD. As a result, the up-counting can be activated at the beginning of a next switching period, so as to raise the reference voltage VR ZC for delaying the timing of
Fig. 10. Measured load transient response in the PCS with the load step from 100 to 400 mA. (a) Pure buck operation. (b) Hybrid operation.
Fig. 11. Measured ZCA operation in the PCS operated buck converter. (a) With a 10-mA load current. (b) With a 40-mA load current.
zero current detection. On the other hand, when the occurrence of zero inductor current detection is late, the reversed inductor current would appear even to deteriorate the power conversion efficiency as shown in Fig. 9(c). VX will be raised after the low-side power MOSFET is turned OFF. That is, VD Tcan have no longer to send a trigger voltage for the up/down counter, so the down-counting operation will be realized. As a result, the operation of zero current detection in the switching regulator can be automatically adjusted, so as to eliminate the negative inductor current and compensate the effect of comparator offset as well as the propagation delay of a driver.
V. EXPERIMENTALRESULTS
The proposed PCS for achieving the power module integra-tion in SoC was fabricated in a 0.25-μm CMOS process. The off-chip inductor and the output filter capacitor are 4.7 μH and 4.7 μF, respectively. The switching frequency of a buck con-verter is 1 MHz. The nominal output voltage is 1.8 V with the battery input voltage range of 2.7–4.3 V. The maximum load cur-rent is about 600 mA. Fig. 10 shows the measured load transient response in the proposed PCS. When the load current changes from 100 to 400 mA, the PCS with the pure switching regulator operation derives the output voltage drop of 80 mV and the re-covery time of 20 μs shown in Fig. 10(a). That is, the APU in the power stage continuously behaves as a part of the high-side power switch for a buck converter. However, the performance of transient response is restricted by the system compensation im-plementations, which are the essential design consideration for guaranteeing the system stability. The load transient response
with the hybrid operation in the PCS is shown in Fig. 10(b). The output voltage drop can be reduced to 35 mV with the transient recovery time of 15 μs. The APU can act as the pass device in the LDO regulator when it receives the demand of the upcom-ing load increasupcom-ing from the SoC. The larger system bandwidth can be derived in hybrid operation to immediately handle extra energy request so that the load transient response can be im-proved. That is, the transient voltage drop can be reduced by 56% and the transient recovery time is improved by 25%. The load regulation is about 0.015 mV/mA because of the satisfac-tory dc voltage gain in the hybrid operation. Furthermore, the hybrid operation is changed back to the pure buck operation at the end of load transient response that can enhance the power conversion efficiency in steady state.
Fig. 11 shows the measured ZCA operation. The DCM oper-ation is activated in a buck converter to maintain the light-load efficiency. The proposed ZCA operation can track the response of the switching node VX after the low-side power switch is turned OFF, and automatically adjust the detection level to de-rive the optimal zero current detection operation. Fig. 11(a) shows the PCS operated buck converter with 10-mA load cur-rent. The variation on the last bit of the up/down counter Q0in a ZCA circuit demonstrates the auto adjusting operation through the response of VX. Thus, the effect of the propagation delay in a driver can be compensated so that the negative inductor current will no longer be derived. The 40-mA load current con-dition of the DCM operation in a buck converter is depicted in Fig. 11(b). The automatic zero inductor adjusting mechanism is still activated to eliminate the occurrence of negative inductor current. Consequently, the proposed ZCA circuit in the PCS can
TABLE I
DESIGNSPECIFICATION OF THEPROPOSEDPCSINSOC
Fig. 12. Measured LDO regulator in the PCS with the load variation between 1 and 70 mA.
Fig. 13. Power conversion efficiency of the proposed PCS power module.
further strengthen the light-load operation in the power module, and thereby improving the light-load efficiency.
Fig. 12 shows the measured LDO regulator operation in the PCS. The output derives a 38-mV voltage drop with the step-up load variation from 1 to 70 mA. The transient recovery time is about 5 μs. The output voltage overshoot is derived as 30 mV with the 5 μs transient settling time when the load changes from 70 to 1 mA. It can demonstrate the stable operation in the LDO regulator since the LOI buffer can move the nondominate poles to high frequencies without causing the phase deterioration. The load transient response is about 0.055 mV/mA. Fig. 13 shows the measured power conversion efficiency of the proposed PCS. With the different supply mechanism according to the distinct
Fig. 14. Current consumption of the distinct power cloud units in the PCS.
Fig. 15. Chip micrograph.
load conditions, the power conversion efficiency can be kept within a relatively high value. Moreover, the hybrid operation can enhance the load transient response but will degrade the efficiency in steady state owing to the switchable APU. The current consumptions of the distinct power cloud units in the PCS are depicted in Fig. 14. It can help further demonstrate the operation in the PCS with the different output load conditions. Fig. 15 shows the chip micrograph with a 1.65 mm2active sili-con area including embedded power switches and the APU. The detailed design specifications are listed in Table I.
VI. CONCLUSION
The PCS is proposed to be the appropriate power module for the SoC. The different power cloud units will form the distinct supply mechanism in the PCS through the power demand from the SoC. When the PCS receives large energy requirements,
the pure switching regulator operation is activated to provide sufficient energy driving capability with high power conversion efficiency. The hybrid operation is realized under medium-load or light-load conditions to utilize the APU to carry out both LDO regulator function to enhance the load transient response and the pure buck operation for guaranteeing efficiency. Besides, the LDO regulator will take over the full energy delivery scheme in the PCS when the SoC enters in the silent mode, which can effectively reduce current consumption but maintain the output voltage regulation. The hybrid setting circuit and the ZCA circuit can also help strengthen the performance of the PCS. The chip was fabricated in a 0.25-μm CMOS process. Experimental results demonstrate that the 56% load transient dip voltage is derived with an improvement of 25% transient recovery time that both the transient response and power conversion efficiency can be ensured at the same time, and the 94% peak efficiency.
REFERENCES
[1] I. Doms, P. Merken, C. Van Hoof, and R. P. Mertens, “Capacitive power management circuit for micropower thermoelectric generators with a 1.4 μA controller,” IEEE J. Solid-State Circuits, vol. 44, no. 10, pp. 2824– 2833, Oct. 2009.
[2] Y.-H. Lee, S.-C. Huang, S.-W. Wang, W.-C. Wu, P.-C. Huang, H.-H. Ho, Y.-T. Lai, and K.-H. Chen, “Power-tracking embedded buck-boost con-verter with fast dynamic voltage scaling for SoC system,” IEEE Trans.
Power Electron., vol. 27, no. 3, pp. 1271–1282, Mar. 2012.
[3] G. Patounakis, Y. W. Li, and K. L. Shepard, “Afully integrated on-chip DC–DC conversion and power management system,” IEEE J. Solid-State
Circuits, vol. 39, no. 3, pp. 443–451, Mar. 2004.
[4] M. E. Sinangil, N. Verma, and A. P. Chandrakasan, “A reconfigurable 8T Ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS,” IEEE
J. Solid-State Circuits, vol. 44, no. 11, pp. 3163–3173, Nov. 2009.
[5] S. Das, D. Roberts, S. Lee, S. Pant, D. Blaauw, T. Austin, K. Flautner, and T. Mudge, “A self-tuning DVS processor using delay-error detection and correction,” IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 792–804, Apr. 2006.
[6] Y.-H. Lee, Y.-Y. Yang, K.-H. Chen, Y.-H. Lin, S.-J. Wang, K.-L. Zheng, P.-F. Chen, C.-Y. Hsieh, Y.-Z. Ke, Y.-K. Chen, and C.-C. Huang, “A DVS embedded power management for high efficiency integrated SoC in UWB system,” IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2227–2238, Nov. 2010.
[7] H.-W. Huang, K.-H. Chen, and S.-Y. Kuo, “Dithering skip modulation, width and dead time controllers in highly efficient DC–DC converters for system-on-chip applications,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2451–2465, Nov. 2007.
[8] M. D. Mulligan, B. Broach, and T. H. Lee, “A 3MHz low-voltage buck converter with improved light load efficiency,” in Proc. IEEE Int.
Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2007, pp. 528–529.
[9] H. Jia, J. Lu, X. Wang, K. Padmanabhan, and Z. J. Shen, “Integration of a monolithic buck converter power IC and bondwire inductors with ferrite epoxy glob cores,” IEEE Trans. Power Electron., vol. 26, no. 6, pp. 1627–1630, Jun. 2011.
[10] W. Yan, W. Li, and R. Liu, “A noise-shaped buck DC–DC converter with improved light-load efficiency and fast transient response,” IEEE Trans.
Power Electron., vol. 26, no. 12, pp. 3908–3924, Dec. 2011.
[11] S. S. Kudva and R. Harjani, “Fully-integrated on-chip DC–DC converter with a 450× output range,” IEEE J. Solid-State Circuits, vol. 46, no. 8, pp. 1940–1951, Aug. 2011.
[12] H. Nam, Y. Ahn, and J. Roh, “5-V buck converter using 3.3-V standard CMOS process with adaptive power transistor driver increasing efficiency and maximum load capacity,” IEEE Trans. Power Electron., vol. 27, no. 1, pp. 463–471, Jan. 2012.
[13] R. J. Milliken, J. Silva-Mart´ınez, and E. Sanchez-Sinencio, “Full on-chip CMOS low-dropout voltage regulator,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 54, no. 9, pp. 1879–1890, Sep. 2007.
[14] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced low-quiescent current low-dropout regulator with buffer impedance attenu-ation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732–1742, Aug. 2007.
[15] C.-H. Lin, K.-H. Chen, and H.-W. Huang, “Low-dropout regulators with adaptively reference control and dynamic push-pull technique for enhanc-ing transient performance,” IEEE Trans. Power Electron., vol. 24, no. 4, pp. 1016–1022, Apr. 2009.
[16] C.-J. Shih, K.-Y. Chu, Y.-H. Lee, and K.-H. Chen, “Hybrid buck-linear (HBL) technique for enhanced dip voltage and transient response in load-preparation buck (LPB) converter,” in Proc. IEEE Eur. Solid-State Circuits
Conf., Sep. 2011, pp. 431–434.
[17] C.-Y. Hsieh and K.-H. Chen, “Adaptive pole-zero position (APZP) tech-nique of regulated power supply for improving SNR,” IEEE Trans. Power
Electron., vol. 23, no. 6, pp. 2949–2963, Nov. 2008.
[18] K.-H. Chen, C.-J. Chang, and T.-H. Liu, “Bidirectional current-mode capacitor multipliers for on-chip compensation,” IEEE Trans. Power
Electron., vol. 23, no. 1, pp. 180–188, Jan. 2008.
[19] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics. Norwell, MA: Kluwer, 2001.
[20] R. G. Carvajal, J. Ramirez-Angulo, A. J. Lopez-Martin, A. Torralba, J. A. G. Galan, A. Carlosena, and F. M. Chavero, “The flipped voltage follower: A useful cell for low-voltage low-power circuit design,” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 52, no. 7, pp. 1276–1291, Jul.
2005.
[21] J. A. Abu Qahouq, “Control scheme for sensorless operation and detection of CCM and DCM operation modes in synchronous switching power converters,” IEEE Trans. Power Electronics, vol. 25, no. 10, pp. 2489– 2495, Oct. 2010.
[22] F.-F. Ma, W.-Z. Chen, and J.-C. Wu, “A monolithic current-mode buck converter with advanced control and protection circuits,” IEEE Trans.
Power Electronics, vol. 22, no. 5, pp. 1836–1846, Sep. 2007.
[23] E. J. Carlson, K. Strunz, and B. P. Otis, “A 20mV input boost converter with efficient digital control for thermoelectric energy harvesting,” IEEE
J. Solid-State Circuits, vol. 45, no. 4, pp. 741–750, Apr. 2010.
Chun-Jen Shih was born in Taoyuan, Taiwan. He received the B.S. and M.S. degrees in electrical and control engineering from National Chiao Tung University, Hsinchu, Taiwan, in 2009 and 2011, respectively.
He is a Member of the Mixed Signal and Power IC Laboratory, Institute of Electrical Control Engineer-ing, National Chiao Tung University. His research interests include the power management IC design and analog integrated circuits.
Kuan-Yu Chu received the B.S. degree from the De-partment of Electrical and Control Engineering, Na-tional Chiao Tung University, Hsinchu, Taiwan, in 2009. He is currently working toward the Master’s degree at the Department of Electrical and Control Engineering, National Chiao Tung University.
He is a Member of the Mixed Signal and Power Management IC Laboratory, Department of Electri-cal and Control Engineering, National Chiao Tung University. His research interests include power man-agement IC design and analog integrated circuits.
Yu-Huei Lee (S’09) was born in Taipei, Taiwan. He received the B.S. and M.S. degrees from the Depart-ment of Electrical and Control Engineering, National Chiao Tung University, Hsinchu, Taiwan, in 2007 and 2009, respectively. He is currently working toward the Ph.D. degree in the Institute of Electrical Control Engineering, National Chiao Tung University.
He is a Faculty Member of the Mixed Signal and Power IC Laboratory, Institute of Electrical Control Engineering, National Chiao Tung University. His current research interests include the power manage-ment integrated circuit design, light-emitting diode driver IC design, and analog integrated circuits.
Wei-Chung Chen (S’12) was born in Yunlin, Taiwan. He received the B.S. degree from the Department of Electrical Engineering, National Sun Yat-Sen Uni-versity, Kaohsiung City, Taiwan, and the M.S. degree from National Chiao Tung University, Hsinchu, Tai-wan, in 2010 and 2012, respectively. He is currently working toward the Ph.D. degree in the Institute of Electrical and Computer Engineering, National Chiao Tung University.
He is a Member of the Mixed-Signal and Power Management IC Laboratory, Institute of Electrical and Computer Engineering, National Chiao Tung University. His research in-terests include the power management IC design, analog integrated circuits, and mixed signal IC design.
Hsin-Yu Luo received the B.S. degree from Chung Yuan Christian University, Taoyuan County, Taiwan, and the M.S. degree from National Central Univer-sity, Taiwan, in 2009 and 2011, respectively, both in electronic engineering.
In 2011, she joined Metal Industries Research and Development Centre as an Engineer. Her interests in-clude power management circuit designs and analog integrated circuit designs.
Ke-Horng Chen (M’04–SM’09) received the B.S., M.S., and Ph.D. degrees in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1994, 1996, and 2003, respectively.
From 1996 to 1998, he was a Part-Time IC Designer at Philips, Taipei. From 1998 to 2000, he was an Application Engineer at Avanti, Ltd., Taiwan. From 2000 to 2003, he was a Project Man-ager at ACARD, Ltd., where he was involved in de-signing power management ICs. He is currently a Professor in the Department of Electrical Engineer-ing, National Chiao Tung University, Hsinchu, Taiwan, where he organized a Mixed-Signal and Power Management IC Laboratory. He is the author or coau-thor of more than 80 papers published in journals and conferences, and also holds several patents. His current research interests include power management ICs, mixed-signal circuit designs, display algorithm and driver designs of liquid crystal display TV, red, green, and blue color sequential backlight designs for optically compensated bend panels, and low-voltage circuit designs.
Dr. Chen has served as an Associate Editor of the IEEE TRANSACTIONS ON POWERELECTRONICSand the IEEE TRANSACTIONS ONCIRCUITS ANDSYSTEMS II. He is on the IEEE Circuits and Systems (CAS) VLSI Systems and Applica-tions Technical Committee, and the IEEE CAS Power and Energy Circuits and Systems Technical Committee.
