經由非線性分析與功率消耗分析求致
經由非線性分析與功率消耗分析求致
經由非線性分析與功率消耗分析求致 Sigma-Delta
經由非線性分析與功率消耗分析求致
Modulator ADC 之設計最佳化
之設計最佳化
之設計最佳化
之設計最佳化
計劃 計劃 計劃 計劃編號編號編號編號: 96-2221-E-009-225-MY3 計劃 計劃 計劃 計劃主持人主持人主持人主持人: 陳福川陳福川陳福川陳福川 計劃 計劃 計劃 計劃執行單位執行單位執行單位執行單位: 交通大學交通大學交通大學交通大學 電控系電控系電控系電控系 摘要 摘要 摘要 摘要 在第一年計畫中,我們的主要目標是經由非 線性的分析去獲得非線性失真模型,為了考慮到 非線性的對於積分三角數位類比轉換器的影響, 我們分析了關鍵幾個主要在積分三角數位類比 轉換器中的非線性失真來源,也建立了其相關的 非線性失真模型,也為了達到在不同規格下可以 獲得精確的電路功率消耗,在這篇論文中,也提供 了精確的離散時間積分三角數位類比轉換器的 功率消耗模型,在最後最佳化的過程中我們導入 了非線性失真模型,功率消耗模型和雜訊功率模 型,綜合了三個模型我們將可以設計出最佳化的 設計規格以在最小的功率消耗下達成設計者所 需要的 SNDR 解析度. AbstractDuring the first year of the project, our main goal is in deriving the distortion models caused by nonlinearity. In order to consider the nonlinear influences in Σ∆ modulator, this report provides the discussions about several dominating nonlinear sources in Σ∆ modulator, and built their distortion power models. In order to obtain the accurate power consumptions for different specifications, this report offers a model to estimate power consumption for discrete-time single-loop Σ∆ modulator. By integrating the distortion power forms, accurate power consumption models and the noise power models into the optimization work, these optimal design specifications can make the performance of Σ∆ modulator achieve the required
SNDR while minimizing power consumption.
Keywords：ADC, Sigma Delta modulator, SDM
I. INTRODUCTION
Σ∆ ADC is very popular for many applications, and in order to decrease the time-cost for practical circuit design, it’s important to know the circuit specifications before circuit design. There is so
many issues and software which offer the synthesis environments to obtain the optimal specifications [2-5]. In general, the synthesis ways for Σ∆ modulator can be categorized mainly as that first. transistor-level simulation synthesis second, macromodel-simulation synthesis and third b e h a v i o r a l - s i m u l a t i o n s y n t h e s i s . T h e transistor-level synthesis has a highest accuracy, but it’s too slow to allow efficient performance space exploration. Behavior- simulation synthesis has a better speed and acceptable accuracy, so this synthesis method is often employed by designers. Our proposed optimization method not only has acceptable accurate, but also faster than Behavior- simulation synthesis. [1] built the dominating noise p o w e r f o r m s a n d o b t a i n e d t h e o p t i m a l specifications for the required SNR. In addition to the noise power forms in [1], this paper involved the dominating nonlinear distortion power forms into optimization since low-distortion is an i mport ant f act or i n man y appl i cat i on s of anal og-to-di gital conver sion; for i nst ance, HDTV( High Definition Television), STB(Set-Top Box) and high- quality digital camera, etc.
The dominated discussion about nonlinear distortion sources and accurate power consumption model are presented in section Ⅱ and section Ⅲ respectively. Conclusion is presented in section Ⅳ.
II. NONLINEAR DISTORTION MODELS The nonlinear distortions in Σ∆ modulator are categorized into six parts in this section, there are four kinds of distortions related to integrators, which are settling distortion, nonlinear finite OTA gain distortion, nonlinear capacitance distortion and nonlinear switch- resistance distortion. Besides the above nonlinearities, DAC distortion and quantization distortion are discussed in this section. Although there are so many distortion sources in Σ∆ modulator, fortunately, due to the developments of process techniques and circuit design, so we only consider the nonlinearities of settling distortion, nonlinear finite OTA gain
distortion and DAC distortion in the optimization job, and the relative techniques are introduced after.
A. Settling Distortion
Settling distortion is the sole distortion which can be significantly affected by op-amp slew rate (SR) and gain-bandwidth (GBW). There was a great effort in [9] to model settling distortion. However the result in [9] reached a wrong conclusion, and it showed little insight about how SR and GBW are quantitatively related to settling distortion. Consider the integrator operates in the integration phase, there are two settling conditions depending on the absolute value of S V. 1. Linear settling ⋅ ⋅ < 2 1 1 τ SR a VS
We can represent integrator output voltage during the nth integration interval as
), 1 ( ) ( ) ( 2 ) 2 ( 1 τ T nT t S o ot V nT T aV e V + − − − + − = nT−T <t<nT 2 (1) where a1 is the gain of the first stage integrator.
S
V
is the difference between feedback and input signal.
T is the sampling period. τ is the time constant 2 in the integration phase [1].
2. Partial slewing < ⋅ ⋅SR VS a1 2 1 τ ) 2 ( ) ( ) (t V nT T SR t0 nT T Vo = o − + ⋅ − + ( ) 0 0 1 )(1 ), 2 ( 2 0 t t e T nT t SR V a t t S − > + − ⋅ − + − − τ (2)
where
t
0 is the time instant whenO
V rate
becomes less than SR. The full slewing case is not considered here because it is not significant. Note that (1) and (2) at end of each integration interval can be rewritten as L S S O O nT V nT T aV e V V V ( )= ( − )+ 1 (1−β⋅ )), ≤ L S S L S O O e V V V V V a T nT V nT V VsVL > ⋅ − + − = ( ) 1 , ) ( 1 β (3) where and 2 1. ) 1 ) 2 ( ( 2 a SR V e L T τ β τ = = − + Let > − ≤ − = L S V V S L L S S i V V e V V a V V e a V g L S ); 1 ( ; ) 1 ( ) ( 1 1 β β (4)
which is the integrator gain. Assume that gi(v) can be approximated by ) ( ) ( 4 5 2 3 1 1 v v a v p = ⋅α +α +α (5) we further analyze the 3rd and 5th harmonic powers as follows: = 4 2 1 log 20 ) ( 3 3 3 VS Settling A dB HD α
=20logα3−60logOSR+30.095 (6)
15 . 48 log 100 log 20 ) ( 5 dB = 5 − OSR+ HD Settling α
From (6) we can see that OSR can effectively influence settling harmonic powers. The (7) reveals that α3 and α are functions of T, GBW, R, 5 CS
and SR.
TableⅠ Minimum SR and GBW required w. r. t. OSR
B. Nonlinear Finite OTA Gain Distortion
An ideal OTA with infinite gain doesn’t introduce any noise or distortion. Practical OTAs not only have the characteristics of finite DC gain, but also the gain is nonlinear.
A typical OTA’s configuration schematic considering nonlinear DC gain. In this figure Rout of
the output-stage transistors are functions of output voltage Vo. Hence, the nonlinearity of the gain is
manifested by its dependency on amplifier output voltage Vo. This nonlinear gain introduces error
components as distortions in the Σ∆ modulator output spectrum.
In order to model the nonlinear DC gain AV, we
tried various combination of Ao and VOS to create a
set of representative curves for the family of nonlinear DC gain curves. It trying to obtain a model for the family of nonlinear curves, we focus on OTAs under the 0.18µm process. The model we arrive at is of the form
) 1 ( ) ( 4 4 2 2 0 o o o V V A qV qV A = + + 2 2 . 1 03 . 0 0 2 (0.443 ) 2 1 os V A q =− ⋅ ⋅ (7) 4 2 . 1 03 . 0 0 4 (0.443 ) 24 1 os V A q =− ⋅ ⋅ (8) The next work is to obtain the expressions to estimate harmonic distortions introduced by integrators with a nonlinear-finite-DC-gain OTA.
The final expression can be derived as
OSR HD3(dB) SR
)
/
(
V
µ
s
(MHz) GBW 8 20logα
3 -24 ≥500 ≥380 16 20logα
3 -42 ≥200 ≥180 32 20logα
3 -60 ≥120 ≥70 50 20logα
3 -72 ≥110 ≥60 64 20logα
3 -78 ≥100 ≥50 96 20logα
3 -89 ≥90 ≥ 40] ) ( ) [( 1 { 2 2 0 2 + − + − − + + + + ⋅ ≅ − o o o o I S o o V V V V A q C C V V 2 2 3 4 0 4[( +) ( +) − ( +) ( −) + + + Vo Vo Vo Vo Vo A q S o o o V V V V + ⋅ + + − − ]} ) ( ) ( 3 4 (9) In (9) the nonlinear term is
− + + − + − + + + + + ⋅ o o o o o o o I S V V V A q V V V V A q C C 4 3 0 4 2 2 0 2(( ) ( ) ) (( ) ( ) [ s o o o o o V V v V V V + + ⋅ + + − + − − )] ) ( ) ( ) ( ) ( 2 2 3 4 (10) In order to build a mathematical expression related to input signal magnitude for estimating the distortion caused by nonlinear OTA gain, ±
o V and
S
V must be expressed as functions of A . In in
single-loop second-order Σ∆ modulator, when a signal Sin(wnT) apply to modulator input and quantization noise is not considered, VS can be represented as ) ) 2 ( sin( ) sin( ) (nT A wnT A wn T VS = in − in −
(
wnT)
OSR Ain )) sin 2 cos( 1 [( − ⋅ = π(
)
] cos ) 2 sin( wnT OSR ⋅ − π (11) The output signal of the first integrator can be represented as [11] ) ) 2 1 ( sin(w n T A Vo = in ± ± ⋅ ⋅ ± ≅ ) cos( ) 2 sin( ) sin( wnT OSR wnT Ain π (12) Substituting (11) and (12) into (10), the harmonic distortion formulas are) 3 cos( ) 3 sin( 3 A 3_1 wnT A 3_2 wnT HD NFDCG= HD + HD (13) ) 5 cos( ) 5 sin( 5 A 5_1 wnT A 5_2 wnT HD NFDCG = HD + HD (14) V V dB A OS 1 1 . 55 0 = = Theoretic (dB) SIMULINK (dB) Ain = 0.2V OSR = 24 HD3NFDCG=-137.1 HD3NFDCG =-139.2 Ain = 0.2V OSR = 60 HD3NFDCG =-145 HD3NFDCG =-148 Ain = 0.2V OSR = 100 HD3NFDCG=-149.5 HD3NFDCG=-152.1 Ain = 0.5V OSR = 24 113.2 -3NFDCG= HD 165.3 -5NFDCG_A= HD 143.1 -5NFDCG_B= HD 115 -3NFDCG = HD 147.7 -5NFDCG= HD Ain = 0.5V OSR = 60 121.2 -3NFDCG = HD 173.2 -5NFDCG_A= HD 151 -5NFDCG_B= HD 123.6 -3NFDCG = HD 156 -5NFDCG = HD Ain = 0.5V OSR = 100 HD3NFDCG =-125.6 HD3NFDCG =-127.1 177.6 -5NFDCG_A= HD 155.9 -5NFDCG_B= HD 158 -5NFDCG= HD
TABLE Ⅱ. Estimation results of theory and behavior simulation where )] 2 cos( 1 [ 4 3 { 0 3 2 1 _ 3 OSR A A q C C A in I S HD π − ⋅ ⋅ ⋅ − = )) 2 cos( 1 ( 16 5 [ 4 5 OSR A q ⋅ in − − π + ))]} 2 cos( 1 ( ) ( sin 8 1 2 OSR OSR π π − ⋅ − ) 2 sin( 4 3 { 0 3 2 2 _ 3 OSR A A q C C A in I S HD π ⋅ ⋅ ⋅ − = 4 5 [ ) 2 sin( 4⋅ ⋅ 5 − + Ain OSR q π )]} ( sin 8 1 ) 2 sin( 16 5 2 OSR OSR π π + + ) 2 ( sin 8 1 16 5 [ 2 0 5 4 1 _ 5 OSR A A q C C A in I S HD ⋅ ⋅ + ⋅ ⋅ = π ))] 2 cos( 1 ( OSR π − ⋅ ) 2 ( sin 8 1 16 5 [ 2 0 5 4 2 _ 5 OSR A A q C C A in I S HD ⋅ ⋅ + ⋅ ⋅ = π )] 2 sin( OSR π ⋅ (15) The power of the 3rd and 5th harmonic distortions are 2 ) ( log 10 ) ( 3 2 2 _ 3 2 1 _ 3 HD HD NFDCG A A dB HD = + 2 ) ( log 10 ) ( 5 2 2 _ 5 2 1 _ 5 HD HD NFDCG A A dB HD = + (16)
Using behavior simulation for two cases to verify the above distortion models, the simulation based on a second-order Σ∆ ADC with input bandwidth 0.1 MHz,
A
0=
55
.
1
dB and VOS=1V . The simulation results are listed in TABLE Ⅱ. In the table, HD3NFDCG represents
Fig. 1. Output spectrum of a second-order Σ∆
modulator with harmonic distortion
the power of the 3rd harmonic distortion,
5NFDCG_ A
HD and HD5NFDCG_ B represent the
powers of the 5th harmonic distortions,
5NFDCG_ A
HD employ (7) and (8) to estimate q2 and q4, the original nonlinear coefficientsq2 and
4
q are employed in HD5NFDCG_ B . The two tables
show that HD5NFDCG_ A and simulation results for SIMULINK are not close, because it is (8) difficultly approach to q4 closely. It is clearly observe that HD5NFDCG_ B and simulation results for
SIMULINK are closer. Although HD5NFDCG_ A is not accurate, the power of HD5 can be neglected since it is too small and usually covered by noise floor. Fig. 1 shows the simulation results based on
0
A
=52.7dB, V =1.38V, OSR=16 and OS Ain=0.7V. In TABLE Ⅱ, HD5NFDCG is too small and covered by noise floor whenA
in=0.2V.
Fig. 2 Simulation results of DAC harmonic distortion
C. Multi-bit DAC Distortion
Any noise or distortion in the DAC response will directly appear at the output without benefiting from loop shaping. Since DAC distortion is related to component mismatch which is random in nature, the
purpose of this subsection is to create a model to estimate average distortion power once the random property in component mismatch is determined.
Expressing the harmonics powers as their expected values, one obtains
2 2 125 . 0 | log 20 ] 2 [HD DAC cap a Ain E ≅ ∆ ⋅ − | 0003255 . 0 010415 . 0 a4Ain4 − a6Ain6 + 5 5 3 3 00130208 . 0 02083 . 0 log 20 ] 3 [HD DAC cap a Ain a Ain E ≅ ∆ ⋅− + 4 4 002604 . 0 | log 20 ] 4 [HD DAC cap a Ain E ≅ ∆ ⋅
| 00013021 . 0 a6Ain6 −
Simulation sees as Fig.2
D. Quantization Distortion
The quantization operation is inherently nonlinear because the quantizer error is determined from the quantizer input signal. For convenience, we usually model the quantizer as a linear model and approximate the quantization noise as a white noise. This approximation is made when the quantization error has the following properties, which we refer to collectively as the “input-independent additive white noise approximation” [15]:
Property 1.
ε
n is statistically independent of the input signal orε
n is uncorrelated with the input signal.Property 2.
ε
n is uniformly distributed in ]2 , 2 [−∆ ∆ .
Property 3.
ε
n is an independent identically distributedFig. 3. PSD of second-order Σ∆ modulator with 5 quantization levels
sequence or
ε
n has a flat power spectral density. whereε
n is the error sequence and ∆ is the distance between output levels. Therefore, the quantization error from Σ∆ modulators is typically not white.For dc, inputs the quantization error is periodic, generating idle channel tones or pattern noise. For
0 -50 -100 -150 -200 -250 4 10 5 10 6 10 P o w er D en si ty (d B ) Frequency (Hz) 0
ac
Fig. 16. Normalized C-V curves (△C/C) of MIM capacitors with single HfO2(12nm), single
) 4 (
2 nm
SiO and HfO2/ SiO2 stack. inputs, the quantization error is also periodic, containing components harmonically related to the input frequency and amplitude. One can view this effect as a time-domain distortion and therefore argue that the converter actually has less resolution than rms measurements. From the properties described above, one can see that multi-bit quantizers are closer to the linear model than single-bit ones and the time-domain distortions of multi-bit quantizers can be ignored, as shown in Fig. 3. From Fig. 3, we can see that the quantization noise is almost white and harmonic distortion is unapparent, hence only the quantization noise is involved in final optimization.
E. Nonlinear Capacitance Distortion
Recently metal-insulator-metal(MIM) capacitor structure is the most popular capacitor fabrication in integrated circuits, which are widely used in analog, mixed-signal and RF circuits [16]. Due to MIM capacitors in integrate circuits occupy a large portion of chip area, hence the high-K dielectrics into MIM capacitors is highly expected in near future [17]. The stability of MIM capacitances are affected by three factors, which are bias voltage, operation frequency and temperature. Harmonic distortions occur at modulator output spectrum, while these nonlinearities appear at integrators in Σ∆ modulators. Fortunately, there are several popular high-K dielectric materials studied to substitute the conventional SiO2 and Si3N4, which are Ta2O5 , HfO5 and . They suppress these nonlinearities effectively [18]. In addition to the above mentioned three materials, [19] provides a multi-layered dielectric, which is HfO2−SiO2
stacked dielectric. Fig. 16 shows the capacitance variation versus bias voltage can be reduced by employing HfO2−SiO2, the capacitance versus bias
voltage is the most stable while
) 4 ( / ) 12 ( 2 2 nm SiO nm
HfO is employed. Fig. 3 shows that capacitance is increased follow the rise of temperature. This structure dielectric also offers an excellent improvement to reduce the impact of temperature for HfO5 . Due to the existing
technique of capacitors fabrication exhibits excellent linearity, hence the distortion cause by nonlinear capacitance in Σ∆ modulators can be neglected reasonable.
Fig.3 . Normalized capacitance vs. temperature
(a) (b) Fig. 4. (a) A simple sample and hold circuit.
(b). The bootstrapped switch
F. Nonlinear Switch Resistance Distortion
In Σ∆ modulators, the MOS switches in integrators introduce harmonic distortion since the resistances of the MOS switches depends on the voltages across the terminals. Fig. 4(a) shows a simple sample and hold circuit for NMOS [x], and its resistance is given by
(
gs tn)
OX n on V V W L C R − = µ 1 (17) where Vtn=Vt0+γ(
2φF +VSB − 2φF)
. shows that the resistance varies with Vin and thebody effect (VSB ) also contribute nonlinearity, especially in low voltage. There several techniques for improving this nonlinearity were proposed [20], [21] and [22]. [20] mention a new sample-and-hold circuit, which is shown in Fig. 4(b). In order to
avoid that the resistance variation follows by Vin, this bootstrapped structure can fix V in gs Vdd,
hence the resistance of the switch can be given by
(
dd tn)
OX n on V V W L C R − = µ 1 (18)For the second nonlinear factor V , [21], [22] SB
and [23] also proposed several techniques to improve its effects. According to the above discussion, due to there are several existed methods to reduce this nonlinear phenomenon effectively, hence we don’t involve the distortion into final optimization.
III. POWER CONSUMPTION ESTIMATION The power consumption can be derived into the analog part and the digital part. The analog power consumption is mainly from OTAs of integrators, quantizer, and DAC. The digital power consumption is mainly from CMOS switches and clock generator.
Table Ⅵ
k
OTA for three common OTA structures The total power consumption of integrators in Σ∆ modulator can be presented asΣ∆ Σ∆ =V ⋅k ⋅f ⋅ ⋅C ⋅V ⋅k
POW _OTA DD OTA cl2
π
L2 reff (19)where,
f
cl2 is the GBW of the OTAs,A common DAC branch in Σ∆ modulator is If the sampling period and integration period are both assumed to be T∕2, the power consumption of an unit capacitor C in the multi-bit DAC is u
s S ref Cs DAC k V C f POW =2⋅ ⋅ 2⋅ ⋅ (20) where
k
Cs is the ratio of the summation of CS inall stages to the CS in the first stage.
For quantizer power consumption, [24] offers an good accuracy model as
) 838 . 4 1525 . 0 ( S min 2 10 ) f ( + × − + × × = DD B B Quantizer f L V POW (21)
where Lmin is the minimum channel length of the technology associated. According to the above discussions, the total analog power consumption of
Σ∆ modulator is
Quantizer DAC
OTA
ana POW POW POW
POW log = + + (22)
The digital power consumption is mainly from
the clock generator The average dynamic power consumption of a CMOS inverter gate can be written as 2 DD Logic S dynamic f C V POW = ⋅ ⋅
where CLogic is the loading capacitors of CMOS logic gates. Assuming a clock generator has NC
CMOS inverters and all inverters have identical loading capacitance of CLogic, then the dynamic power consumption of clock generator is approximately 2 DD Logic S C CLOCK N f C V POW ≅ ⋅ ⋅ ⋅ (23) Another important source of the digital power dissipation is from CMOS transmission gates in the switched-capacitor circuits.
The power consumption for all the transmission gates is 2 DD gate S Switch N f C V POW = ⋅ ⋅ ⋅ (24) Finally, the total digital power consumption is
Switch CLOCK
digital POW POW
POW = + (25) The total power consumption is
digital ana
total POW POW
POW = log+ (26)
IV. CONCLUSIONS
Entering the nonlinear distortion power models into optimization which are not offered in [1] is the main contribution of this work. By combining these distortion power models with the noise power models in Appendix into optimization, the optimal design specifications are obtained. All the nonlinearity power also can be obtained after an complete optimization, and the dominating nonlinearity power can be reduced by adjusting the design specifications. Fourth, our optimization method can be hundreds of times faster than existing behavioral simulation based approaches.
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