原子層沉積高介電係數氧化鋁閘極介電層之三五族元件電物性研究

國 立 交 通 大 學

電子工程學系 電子研究所

碩 士 論 文

原子層沉積高介電係數氧化鋁閘極介電層之

三五族元件電物性研究

Electrical and physical characteristics of III-V devices with

atomic-layer-deposited Al

2

O

3

high-κ gate dielectric

研

究

生 : 江欣哲

指 導 教 授 : 簡昭欣 博士

原子層沉積高介電係數氧化鋁閘極介電層之三五族元件電

物性研究

Electrical and physical characteristics of III-V devices

with atomic-layer-deposited Al

2

O

3

high-κ gate dielectric

研 究 生：江欣哲 Student : Hsin-Che Chiang

指導教授：簡昭欣 博士

Advisor : Dr. Chao-Hsin Chien

國 立 交 通 大 學

電子工程學系 電子研究所碩士班

碩 士 論 文

A Thesis

Submitted to Department of Electronics Engineering

& Institute of Electronics

College of Electrical and Computer Engineering

National Chiao Tung University

In Partial Fulfillment of the Requirements

For the Degree of Master

In

Electronics Engineering

September 2008

Hsinchu, Taiwan, Republic of China

原子層沉積高介電係數氧化鋁閘極介電層之

三五族元件電物性研究

學生：江欣哲 指導教授

：

簡昭欣 博士

國 立 交 通 大 學

電子工程學系 電子研究所 碩士班

摘 要

在這篇文獻中,我們已經最佳化利用硫鈍化處理的方式處理砷化鎵表面,並且成功 地使 Dit 值下降到 5E12cm-2 eV-1 。一開始的時候,我們利用 XPS 方式去分析 Ga2p3 和 As2p3 在不同的硫鈍化處理下成份變化情形,我們發現到當我們把硫化濃度和溫度提高時,砷 化鎵表面的氧化物會被有效的抑制;同時,我們也觀察到利用硫化氨配合丁醇的方式對 於表面氧化物抑制確實比傳統硫化氨配合水來的有效。在另一方面,我們也同時去研究 反應頻率的表現在其他三五族砷化銦和砷化銻。對於較小能矽材料來說,相對的它的反 應頻率也就越快。對於這篇研究說,利用不同硫化處理的方式在這兩種材料似乎對於氧 化物和基板介面並沒有太大改善。針對電容研究的情形,我們最後使用硫化氨加丁醇方 式去製作出砷化鎵場效應電晶體來。 此外,我們也使用不同合金材料去做一些歐姆接觸方面的研究,基本上我們是以金-鍺為基底分別鍍上鎳、鍺、金材料,接著利用快速退火的方式達到較低的毆姆接觸。我 們發現,當溫度越高時,表面的粗操度也就越大,對於阻值會有一定的影響。 最後,我們综合前面的結果在半絕緣的基版上面製作金半場效應電晶體和金氧半場 效應電晶體。我們已經成功低將電子遷移率提升到 460cm2 V-1 S-1 ,相對來說還是比較低的 值,可能是因為表面蝕刻後粗操度和高濃度摻雜後庫倫散射所造成。因此,我們可以推論 出硫化氨加丁醇鈍化方式在表面形成保護層,以及利用氧化物退火的方式去完成較好品

質的場效應電晶體。再之後我們利用超高真空化學氣相沉積的方式去沉積矽鍺緩衝層， 利用這種方式使三五族長在矽的基板上去降低材料成本，我們認為這將是未來應用上重 要結構,並且對於後矽時代高遷移率量產上會有所幫助。

Electrical and physical characteristics of III-V devices with

atomic-layer-deposited Al

2

O

3

high-κ gate dielectric

Student：Hsin-Che Chiang Advisors：Dr.

Chao-Hsin Chien

Department of Electronics Engineering and Institute of Electronics

National Chiao Tung University

ABSTRACT

In this thesis, we had optimized the sulfide treatment on GaAs surface and also eliminate the surface state to 5E12 (cm-2eV-1) successfully. In the beginning, we analyzed the component of Ga 2p3 and As 2p3 photoemission spectra with different sulfide passivation. We found the oxide decrease due to increasing sulfur concentration and process temperature; and we found this solution did result in superior electrical characteristics than the conventional (NH4)2S solution (H2O). On the other hand, we also fabricated the

Pt/ALD-Al2O3/InSb InAs capacitors to discuss the minority response. The smaller band gap

resulted in high transition frequency. Interface density of InSb and InAs were not changeable with any surface treatment in this study. We choose the better condition: (NH4)2S+C4H9OH at

60 °C to fabricate GaAs nMOSFET.

In addition, we also tried different alloy metal material to form S/D ohmic contact. The most common approach to the formation of AuGe-based ohmic contacts is to evaporate layers of Ni, Ge, and Au metals onto the GaAs sample followed by annealing. Obviously, the higher the temperature used, the rougher the top surface and metal-substrate interface was observed.

Finally, we had fabricated MESFET and MOSFET on semi-insulator substrate. The electronic mobility we extracted is 460 cm2V-1S-1; the lower mobility was due to rough surface and Column scattering. Therefore, we conclude that the high quality MOSFET can be achieved integrating (NH4)2S+C4H9OH and dielectric annealing process. Finally, we grew

heavy-doped channel on Si substrate, which can be considered as the potential structure of novel device for metal-oxide-semiconductor field effect transistor application.

誌 謝

兩年的日子說長不長,說短不短,研究所兩年中我想最感謝的是我的指導教授簡昭 欣博士,在實驗上讓我有充足的資源可以發揮,並且教導我們正確的研究方法以及嚴謹 的態度去探討問題,還有每次meeting都能喝到上等的台灣茶,遇到這樣的好老師,是我 們學生的福氣。 其次我要最感謝的是兆欽學長,學長對於研究的執著以及熱忱,都是我學習的目標, 還有時間規劃和做事效率,我只能忘其項背跟隨你的腳步,這兩年來遇到很多無法理解 的現象,也是和你一一討論而終於豁然開朗,最後還有榮幸到日本去參加conference,我 只能說,學長,你真的太照顧我了。明瑞學長和志彥學長,謝謝你們在NDL的幫忙以及 meeting上的建議,讓我在報告上面更有信心。世璋學長,雖然很久沒見到面,不過咖啡的 日子還有明信片,都讓我在小小碩一的時候生活添加許多樂趣。 接下來是實驗室畢業的學長,阿國和熊哥,在我碩一懵懵懂懂的時候就帶我train 各式不同的機台,以及實驗上該注意的事項,有了你們的幫助,往後的實驗讓我順利不 少。小劉,有了你的加入,讓我們實驗室增加不少風采,少了你的感覺,我還真的有點不太 習慣。家豪學長,你現在已經是實驗室的支柱了,也謝謝學長教我L-EDIT和在實驗上提供 我ㄧ些寶貴的建議,讓我收益不少,也祝福你往日的實驗也能夠順利。阿壘和漢堡神偷妍 心,常常受到你們的照顧,還有去你們Lab吃東西和用機台,以後回來再喝你們的喜酒 喔!stone,你讓我見識到強者的威力,也希望你工作能順利。儀科中心的志忠學長,沒有 你大力協助,我想我們的實驗很難有所突破,往後的學弟也麻煩你了。蕭副、劉帥、李博、 文浩、大致傑、小智傑學長,也謝謝你門在實驗上的建議,讓我可以學到一些不同領域的 東西。貴儀的黃繡吟小姐和NDL沈奕玲小姐,謝謝你們XPS和AES上的幫助,讓這篇論文更 有可看性。中科院的至宏學長,謝謝你在最後提供MBE磊晶的片子,沒有你鼎力相助,我想 現在還只是個半成品。 實驗室的好伙伴,效諭(rain)和胖虎(冏),前者是殺人於無形,功力高深莫測,後者 是誹聞製造機,時常都會有新歡出現,實驗室有我們三個好像話題增加了不少,我想沒有

你們我大概會很無聊吧!胖哥,也希望你的黑珍珠能夠順利長大。阿倫和弘森,有了你們, 讓我們總是有話題可以討論,搞不好在軍中又可以聚聚囉!宇彥和阿飛,今後也要堅持自 己所選的路,也住你們在往後不管是學業或工作都能順利。學弟宗佑,III-V的發揚光大 就靠你了,我相信你可以的,政庭、耀昇、大鳥和小猪,實驗室就交給你們把持住了!老高, 謝謝你總是在我寂寞的時候介紹許多女生給我,讓我見識到什麼是真男人。阿威,你這個 跟我生活一起兩年的好朋友,讓我見識到impossible is nothing,也祝你能早日脫離水 生火熱的日子。三平,打牌以後還是要找我喔!趙天生group學長學弟,籃球場上奔跑的日 子是我難以忘懷的!阿杰,國軍online後我們一定會再見的;校長實驗室的塞哥、師傅、 Joner、吱吱、勾勾揚和陶淵明,無塵室的日子是我ㄧ輩子難忘的回憶。還有心卉學姊, 你的照顧讓我備受溫暖,怡誠學長,日本妹就靠你了。 大學的好朋友博文、老許、馬保、信雄、佩真、小龜、吉拉、老柯、春薇、阿炮、 阿腿以及五家的學長姊們,回台北的日子有你們陪伴真好! 最後,我想感謝我的家人,江錦發先生和吳瓊珠小姐,不果是精神方面或者是物質 方面,都讓我無後顧之憂,老哥明晏,也在我這個任性的弟弟下包容我不少。誌謝的最後, 我想謝謝妳,謝謝妳讓我懂得珍惜,讓我成長不少。謹以此篇論文獻給所有幫助過我的人, 謝謝你們。 江欣哲 於 新竹國立交通大學 2008 年 9 月

Contents

Abstract (Chinese) --- i

Abstract (English) --- iii

Acknowledgments --- v Contents --- vii Table Captions ---x Figure Captions --- xi

Chapter 1

Introduction

1-1 General Background --- 1 1-2 Motivation --- 2

1-3 Organization of This Thesis --- 5

References---8

Chapter 2

Improved electrical characteristics of ALD-

Al

2

O

3

/III-V MOS capacitors with sulfide treatment

2-1 Introduction --- 9

2-3 Results and Discussion --- 12

2-3-1 Wet cleaning on GaAs ---12

2-3-2 Surface treatment on GaAs ---14

2-3-3 Surface roughness of sulfide GaAs --- 15

2-3-4 Electrical and material characteristics of MOSCAP --- 16

2-3-5 InAs and InSb MOSCAP characteristics ---18

2-4 Summary --- 21

References ---23

Chapter 3

Alloyed Source/Drain Ohmic Contact on GaAs

3-1 Introduction --- 44

3-2 Experimental Procedures --- 45

3-3 Results and Discussion --- 45

3-4 Summary --- 49

References---50

Chapter 4

Electrical characteristics of GaAs MESFET&MOSFET with

atomic-layer-deposited Al

2

O

3

dielectric

4-1 Introduction - --- 59

4-2-1 Device structure (MESFET) --- 60

4-2-2 Device structure (MOSFET) --- 61

4-3 Results and Discussions --- 62

4-3-1 Electrical characteristics of GaAs MESFET ---63

4-3-2 Effective channel thickness and depletion width calculation --- 64

4-3-3

Electrical characteristics of depletion mode GaAs nMOSFET --- 65

4-4 Summary --- 68

References---70

Chapter 5

Conclusions and Suggestions

5-1 Conclusions --- 91

5-2 Future work --- 92

Table Captions

Chapter 2

Table 2-1 Wet cleaning process of GaAs in this study ---13

Chapter 4

Table 4-1 The effective channel layer thickness and depletion width were prepared in this study. (gate length=25um, gate width=100um)---65

Chapter 5

Figure Captions

Chapter 1

Fig. 1-1 Predicted band offsets on GaAs with different high-k materials

--- 4 Fig. 1-2 All of the novel deposit thin film technique comparison--- 4

Chapter 2

Fig. 2-1 Atomic layer deposition (ALD) mechanism --- 24 Fig. 2-2 Pt/Al2O3/n-GaAsMOSCAP process flow --- 25

Fig. 2-3 XPS spectrum Ga2p3 As2p3 As3d after different concentration of dilute

ammonia.---26 Fig. 2-4 (a) Multi-frequency C-V characteristics of MOS capacitors (Pt/Al2O3/GaAs)

with 1% and 10% concentration of dilute ammonia. (b) Multi-frequency C-V characteristics of MOS capacitors (Pt/Al2O3/GaAs) with post deposit

annealing at 600 oC in the O2 ambient.---27

Fig. 2-5 J-V characteristics of Pt/Al2O3/GaAs MOS capacitor with 1% and 10%

concentration of dilute ammonia. The Al2O3 was deposited by ALD (300 oC, 60

cycles).---28 Fig. 2-6 G-V characteristics of Pt/Al2O3/GaAs MOS capacitor with and without 600 oC

O2 annealing. The Al2O3 was deposited by ALD (300 oC, 60 cycles). ---28

Fig. 2-7 (a) XPS spectrum Ga 2p3 after different cleaning processes of Table II---29 (b) XPS spectrum As 2p3 after different cleaning processes of Table III---30

Fig. 2-8 (a) XPS spectrum Ga 3d with different surface treatment after ALD process (b) XPS spectrum As 3d with different surface treatment after ALD process----31 Fig. 2-9 (a) surface morphology (b) surface roughness after sulfide treatment---32 Fig. 2-10 The C-V(10kHz) curves of Pt/Al2O3/GaAs MOS capacitors with

(NH4)2S+C4H9OH treatments. The Al2O3 was deposited by ALD (300 oC, 60

cycs.) ---33 Fig. 2-11 Capacitances of an MOS capacitors for various bias conditions---33 Fig. 2-12 J-V characteristics of Pt/Al2O3/GaAs MOS capacitor (NH4)2S+C4H9OH with and

without 600 oC O2 PDA. The Al2O3 was deposited by ALD (300oC, 60 cycles)--34

Fig. 2-13 (a) C-V(10kHz) curves of Pt/Al2O3/GaAs MOS capacitors with (NH4)2S+H2O

(b). J-V characteristics of Pt/Al2O3/GaAs MOS capacitor (NH4)2S+H2O with and

without 600oC O2 PDA. The Al2O3 was deposited by ALD (300 oC, 60 cycles)-35

Fig. 2-14 (a) Multi-frequency C-V characteristics of MOS capacitors (Pt/Al2O3/GaAs) with

(NH4)2S+C4H9OH and H20 at 60 oC (b) Multi-frequency C-V characteristics of

MOS capacitors (Pt/Al2O3/GaAs) with (NH4)2S+C4H9OH and H20 at 60 oC with

600 oC O2 PDA ---36

Fig. 2-15 (a) ΔC and ΔV versus different IPLs with (NH4)2S+C4H9OHby ALD (b) ΔC and

ΔV versus different IPLs with (NH4)2S+H2O by ALD (300 oC, 60cycs)--- 37

Fig. 2-16 Dit versus different IPLs for MOS capacitors Pt/Al2O3/GaAs made by ALD----38

Fig. 2-17 (a) Comparison of Jg versus CET or EOT characteristics in this work with

other’s published data. (b) The HRTEM images of Al2O3 film by ALD 60 cycles

on GaAs. The sulfide treatment was (NH4)2S+C4H9OH---39

Fig. 2-18 Pt/Al2O3/InSb normalize C-V curves are recorded at 100kHz with different

Fig. 2-19 (a). Pt/Al2O3/InSb C-V curves are recorded at 100kHz with different treatment

(b). Pt/Al2O3/InSb Room temperature J-V curves are recorded with different

surface treatment(c) Multi-frequency C-V characteristics of MOS capacitors

(Pt/Al2O3/InSb) with different Si capping thickness.---41

(c) Multi-frequency C-V characteristics of MOS capacitors (Pt/Al2O3/InSb) with different Si capping thickness.---42

Fig. 2-20 Jg vs. CET for MOS capacitors (Pt/Al2O3/III-V) made by ALD (100 oC and 200 oC) ---43

Fig. 2-21 Dit vs different surface treatment characteristics of Pt/Al2O3/III-V MOS capacitor made by ALD (60cycles) at 100 oC and 300 oC---43

Chapter 3

Fig. 3-1 Transfer length method test structure (Z=50um W=100um)---53

Fig. 3-2 Depletion-type contacts to n-type substrates with increasing doping concentrations. The electron flow is schematically indicated by the electron and their arrows (a) Thermionic emission (b) Thermionic/Field emission (c) Field emission---53

Fig. 3-3 The specific contact resistuvity of alloy AuGeNi annealing at (a)350 oC (b) 400 oC (c)450 oC, respectively. ---54

Fig. 3-4 The specific contact resistivity as a function of anneal time with AuGeNi---55

Fig. 3-5 AES depth profiling of AuGeNi at (a) 350 oC (b) 400 oC (c) 450 oC---56

Fig. 3-6 AFM surface morphology of AuGeNi at (a) as dep. (b) 400 oC---57

Fig. 3-7 SEM surface morphology of AuGeNi at (a) as dep. (b) 400 oC (c) 450 oC (d) 500 oC---58

Fig. 3-9 The specific contact resistivity of various materials at different temperatures

---59

Chapter 4

Fig. 4-1 Wet etching rate as a function of etching times for GaAs---72

Fig. 4-2 The Scanning electron microscope of Mesa etching isolation ---72

Fig. 4-3 Fabricated GaAs MESFET process flow---73

Fig. 4-4 Fabricated GaAs MOSFET process flow---74

Fig. 4-5 The HRTEM images of GaAs MOSFET---75

Fig. 4-6 Schottky breakdown field as function of gate bias with and with not treatments ---75

Fig. 4-7 (a) Drain current versus drain bias as a function of gate bias for a 25um x100 um MESFET(b) Schottky characteristics with and without 400 oC 10 min forming gas annealing---76

Fig. 4-8 S/D ohmic contact with and with not 400 oC 10 min forming gas annealing--77

Fig. 4-9 Drain current and transconductance versus gate bias as a function of gate bias for a 25um x100 um MESFET.---77

Fig. 4-10 Drain current versus drain bias as a function of drain bias for a 25um x100um MESFET with and without forming gas annealing.---78

Fig. 4-11 SIMS analysis for (a) lower doping (b) high doping GaAs channel was grown semi-insulator substrate---79

Fig. 4-12 Fig. 4-12 (a) The capacitance as a function of reverse gate bias with 10umX100um (b) The measure channel concentration as a function of depletion width---80

Annealing---81 Fig. 4-14 The trapping window with and without 600 oC annealing in O2 ambient---81

Fig. 4-15 Characteristics of the specific contact resistance (a) without and (b)with high doping capping layer.---82 Fig. 4-16 (a) Drain current as a function of gate bias with doping layer (Nd=4E17cm-3)

(b) Drain current as a function of drain bias with sulfur passivation---83 Fig. 4-17 (a) Case I(Nd=5E18cm-3) for (a) Id-Vg (b) Id-Vd DC electric characteristics---85

(b) Case II (Nd=6E16cm-3) for (a) Id-Vg (b) Id-Vd DC electric characteristics

Fig. 4-18 Weibull distribution of Al2O3 physical thickness with and without gate etching

---86 Fig. 4-19 (a) Drain current as a function of gate bias with and without (NH4)2S+C4H9OH

surface passivation (b) Drain current as a function of drain bias without surface passivation.---87 Fig. 4-20 (a) Id-Vg (b) Id-Vd electronic characteristics with (NH4)2S+C4H9OH surface

treatment---88 Fig. 4-21 The peak of electron mobility we extract with and without sulfur passuvation-89 Fig. 4-22 The HRTEM images of Al2O3 film by ALD 120 cycles on GaAs MOSFET---89

Fig. 4-23 The transconductance as a function of Vg-Vt for GaAs MESFET and MOSFET

---90

Chapter 5

Fig. 5-1 The structure of growing GaAs on Si substrate with SiGe buffer layer---93 Fig. 5-2 The HRTEM image of growing GaAs on Si substrate with Ge buffer layer----93

temperature(c)Multi-frequency (d) Hysteresis with two epi substrate (i) Si (ii) Ge (e) The capacitance of 10kHz frequency of Pt/Al2O3/epi-GaAs with different

annealing ---94 Fig. 5-4 The leakage current with two different epi substrate (i) GaAs/Ge sub. (ii) GaAs/Ge/Si sub---95 Fig. 5-5 Surface morphology of (a)MOCVD-epi GaAs (b)bulk GaAs substrate---96

Chapter 1

Introduction

1-1 General Background

Today, the electronic products pursue not only the higher speed, better performance, and huger packing density, but also less power consumption and lower cost. For market requirements, the scale of Si device’s dimension was the major issue in the past. Until now, the feature sizes of conventional Si MOSFET’s have approximated to its physical limits. Shrinking the channel length and/or the dielectric thickness can’t perform the excellent switching ratio, high driving capability, low leakage current, and acceptable reliability. For the excellent performances, novel device structures and materials must be investigated. The GaAs device applications have become very critical due to the requirement for global communication industrial growth.

GaAs metal-oxide-semiconductor field transistors (MOSFET) with high electron mobility in the semiconductor have application in high-speed electronic devices. Furthermore, semi-insulating substrates not available in silicon, is necessary to reduce the RC time delay between high-speed signal line in dense GaAs circuit. For both microwave and digital applications, GaAs MOSFET technology promises the advantages of low-power consumption

and circuit simplicity. Realization of the above devices depends on achievement of a low interfacial state density (Dit) existed between the gate dielectric and GaAs.

Si technology with its devices of 90nm gate length in production and 50 nm or smaller in research and development, and with SiO2 gate oxide thickness close to quantum tunneling

limit of 1.0 nm, has called for alternative high-k gate dielectrics. However, Coulomb scattering from charge trapping and the phonon issue related to high-k gate dielectric have resulted the degradation in channel mobility. In general, choices of suitable gate dielectric in MOSFETs will require (a) that the oxide does not react with the semiconductor, and (b) that the band offset of the oxide on the semiconductor is required to have over 1eV [1] to inhibit leakage. The band offset of various gate dielectrics, including HfO2, Al2O3, Gd2O3, Si3N4 and

SiO2 [2~15] on III-V semiconductors such as GaAs, InAs, GaSb and GaN have been

calculated using the method of charge neutrality levels. Here, we showed the band offset of GaAs in Fig 1-1.

1-2 Motivation

III-V compound semiconductors offer the advantages of high electron mobility rich band gap engineering, low power consumption [16-19] and high breakdown fields and thus are expected to outperform Si in certain metal-oxide-semiconductor (MOS) applications such as high-speed and high power devices. In contrast to the present commercially available III-V

metal-semiconductor field transistors (MESFETs) and high electron mobility transistors (HEMTs), which exhibit small forward gate voltages limited by the Schottky barrier heights, the III-V MOSFETs feature a much larger logic swing which gives a greater flexibility for digital integrated circuit (IC) designs and higher current gain cutoff frequency.

One key challenge in the III-V technology is to identify thermodynamically stable insulators on the III-V’s that give a low Dit and low gate leakage (Jg). The intensive efforts in

questing for such competitive insulator/III-V systems have finally yielded fruitful results with the discovery of high-k dielectric Ga2O3-Gd2O3 [20, 21] mixture or Gd2O3 [22, 23] on gallium

arsenic (GaAs) and atomic layer deposition (ALD) Al2O3 [24-32] on GaAs, in which the

reduced values in Dit and Jg have been demonstrated. The employment of ALD-Al2O3 as a

gate dielectric layer, along with an implantation, followed by rapid thermal annealing (RTA) for activation process, have led to the demonstration of the first inversion-channel n-GaAs MOSFETs. On the other hand, we also displayed the advantages and disadvantages by using ALD and compared it with other PVD & CVD in Fig. 1-2. As can be seen, it indeed played an important role in fabricating the novel structure in the future. In Chapter 2 we further showed ALD growth principle in details.

Fig 1-1 Predicted band offsets on GaAs with different high-k materials

1-3 Organization of the Thesis

In Chapter 2, we developed the cleaning processes of GaAs substrates at first; different surface treatments were tested. During cleaning, it is important to suppress GaAs native oxides and As layer. Accordingly, we examined the chemical ratio after different cleaning processes by performing ex-situ XPS measurements. Subsequently, we deposited ALD-Al2O3

as dielectric film to fabricate MOS capacitors and examine the impact of interface quality on the electrical characteristics; the capacitance-voltage (C−V) and gate leakage current (I−V) characteristics were studied. In addition, InAs and InSb MOS capacitors were also discussed. In Chapter 3, we optimized the alloy condition for ohmic contact formed on GaAs. Three different materials, AuGeNi, PdGe, and PtIn, were tested and we extracted the respective specific contact resistance. We also undertook the physical analyses, including Atomic Force Microscopy (AFM), Scanning Electron Microscopy (SEM) and Auger Depth Profiling, respectively. In Chapter 4, we fabricated the GaAs MESFET and MOSFET structures on semi-insulating GaAs and discussed their Id-Vg and Id–Vd electric characteristics. We also

determined the electronic mobility with different surface treatments.

In the end of this thesis, chapter 5, we deposited GaAs thin film on Si substrate with Ge/SiGe buffer layer. The C-V and I-V curves were analyzed and surface performance was improved by sulfur chemical treatment. Finally, we gave the conclusions and suggestions for future work.

References

[1] J. Robertsona_ , B. Falabretti “Band offsets of high K gate oxides on III-V semiconductors.” J. Appl. Phys. 100, (2006) 014111.

[2] S. J. Lee, H. F. Luan, W. P. Bai, C. H. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “High-quality ultrathin CVD HfO

2 gate stack with poly-Si gate electrode,” in

IEDM Tech. Dig., 2000, pp. 31-34.

[3] C. H. Lee, H. F. Luan, W. P. Bai, S. J. Lee, T. S. Jeon, Y. Senzaki, D. Roberts, and D. L. Kwong, “MOS characteristics of ultra thin rapid thermal CVD ZrO

2 and Zr silicate gate

dielectrics,” in IEDM Tech. Dig., 2000, pp. 27-30.

[4] C. O. Chui, H. Kim, D. Chi, B. B. Triplett, P. C. McIntyre, and K. C. Saraswat, “A sub-400°C germanium MOSFET technology with high-k dielectric and metal gate,” in IEDM Tech. Dig., 2002, pp. 437-440.

[5] W. P. Bai, N. Lu, J. Liu, A. Ramirez, D. L. Kwong, D. Wristers, A. Ritenour, L. Lee, and D. Antoniadis, “Ge MOS characteristics with CVD HfO

2 gate dielectrics and TaN gate

electrode,” in VLSI Symp. Tech. Dig., 2003, pp. 121-122.

[6] A. Ritenour, S. Yu, M. L. Lee, N. Lu,W. Bai, A. Pitera, E. A. Fitzgerald, D. L. Kwong, and D. A. Antoniadis, “Epitaxial strained germanium p-MOSFETs with HfO

2 gate

dielectric and TaN gate electrode,” in IEDM Tech. Dig., 2003, pp. 433-436.

[7] C. O. Chui, H. Kim, P. C. McIntyre, and K. C. Saraswat, “A germanium NMOSFET process integrating metal gate and improved high-k dielectrics,” in IEDM Tech. Dig., 2003, pp. 437-440.

[8] K. Kita, M. Sasagawa, K. Tomida, K. Kyuno, and A. Toriumi, “Oxidation-induced damages on germanium MIS capacitors with HfO

[9] J. J. Chen, N. A. Bojarczuk, H. Shang, M. Copel, J. B. Hannon, J. Karasinski, E. Preisler, S. K. Banerjee, and S. Guha, “Ultrathin Al2O3 and HfO2 gate dielectrics on

surface-nitrided Ge,” in IEEE Trans. Electron Devices, vol. 51, no. 11, Nov. 2004, pp. 1441-1447.

[10] D. S. Yu, C. H. Huang, A. Chin, C. Zhu, M. F. Li, B. J. Cho, and D. L. Kwong, “Al

2O3-Ge-on-insulator n- and p-MOSFETs with fully NiSi and NiGe dual gates,” in

IEEE Electron Device Lett., vol. 25, 2004, pp. 138-140.

[11] A. Chin, Y. H. Wu, S. B. Chen, C. C. Liao, and W. J. Chen, “High quality La2O3 and

Al2O3 gate dielectrics with equivalent oxide thickness 5-10 Å,” in VLSI Symposium

Technical Digest, 2000, pp. 16.

[12] C. H. Lee et al., “MOS devices with high quality ultra thin CVD ZrO2 gate dielectrics

and self-aligned TaN and TaN/Poly-Si gate electrodes,” in VLSI Tech. Dig., 2001, pp. 137-138.

[13] B. H. Lee, R. Choi, L. Kang, S. Gopalan, R. Nieh, K. Onishi, Y. Jeon, W-J. Qi, C. Kang, and J. C. Lee, “Characteristics of TaN gate MOSFET with ultrathin hafnium oxide (8–12Å),” in IEDM Tech. Dig., 2000, pp. 39-42.

[14] S. J. Lee et al., “Performance and reliability of ultra thin CVD HfO2 gate dielectrics with

dual poly-Si gate electrodes,” in VLSI Tech. Dig., 2001, pp. 133-134.

[15] G D. Wilk, and R. M. Wallace, “Hafnium and zirconium silicates for advanced gate dielectrics,” in J. Appl. Phys., vol. 87, 2000, pp. 484-492.

[16] M. Hong, J. Kwo, A. R. Kortan, J. P. Mannaerts, and A. M. Sergent, Science 283, 1897 (1999)

[17] K. Iiyama, Y. Kita, Y. Ohta, M. Nasuno, S. Takamiya, K. Higashimine, and N. Ohtsuka, IEEE Trans. Electron Devices 49, 1856 (2002)

[19] P. D. Ye, G. D. Wilk, J. Kwo, B. Yang, H. J. L. Gossmann, M. Frei, S. N. G. Chu, J. P. Mannaerts, M. Sergent, M. Hong, K. K. Ng, and J. Bude, IEEE Electron Device Lett. 24, 209 (2003)

[20] M. Hong, M. Passlackm, J. P. Mannaerts, J. Kwo, S. N. G. Chu, N. Moriya, S. Y. Hou, and V. J. Fratello, J. Vac. Sci. Technol. B 14, 2297 (1996)

[21] J. Kwo, D. W. Murphy, M. Hong, R. L. Opila, J. P. Mannaerts, A. M. Sergent, and R. L. Masaitis, Appl. Phys. Lett. 75, 1116 (1999)

[22] M. Passlack, M. Hong, and J. P. Mannaerts, Appl. Phys. Lett. 68, 1099 (1996)

[23] B. Yang, P. D. Ye, J. Kwo, M. R. Frei, H. J. L. Gossnann, J. P. Mannaerts, M. Sergent , M. Hong, K. Ng, and J. Bude, J. Cryst. Growth 251, 837 (2003)

[24] Yang WS, Kim YK, Yang SY, Choi JH, Park HS, Lee SI, et al. Surf. Coat. Tech. 2000; 131:79

[25] Higashi GS, Fleming CG. Appl. Phys. Lett. 1989; 55:1963-5. [26] Fan J, SugiokaK, Toyoda K. Jpn J. Appl. Phys. 1991; 30:L1139-41

[27] Kattelus H, Ylilammi M, Saarilahti J, Antson J, Lindfors S. Thin Solid Films 1993; 225:296

[28] Lin HC, Ye PD, Wilk GD. Appl. Phys. Lett. 2005; 87:182904

Chapter 2

Improved electrical characteristics of ALD-

Al

2

O

3

/III-V MOS capacitors with sulfide

treatment

2-1 Introduction

Recently, GaAs materials are used widely in such applications as optoelectronic devices, photodiodes, high electron-mobility transistors (HEMT), and other high-frequency devices. In attempts to obtain superior performance rivaling or exceeding that of transistors on traditional Si-based substrates, various high-k gate dielectrics have been examined on high-mobility III-V substrates, especially GaAs- and InSb-based compound materials. Studies into competitive insulators on compound semiconductors and efficient passivation methods have been performed for more than four decades; the poor quality of the insulator-substrate interface has been the foremost obstacle hindering the realization of III-V metal oxide semiconductor MOS devices. In addition to SiO2 and Si3N4, atomic-layer-deposited ALD

Al2O3, Gd(Ga)O3, and HfO2 high-k dielectrics are also potential candidates for use on GaAs

substrates. Surface sulfide treatment and the use of ultrathin Si or Ge interfacial passivation layers are both practical techniques for improving electrical characteristics. The passivation of

GaAs surfaces with Na2S [1] or ammonium sulfide (NH4)2S [2] prior to deposition of the gate

dielectric has been reviewed comprehensively; the improvement in the device performance depends strongly on the sulfide treatment procedure. The in-situ deposition of several Si or Ge monolayers [3.4] on GaAs can reduce the Dit to approximately 1010–1011 cm−2 eV−1; this

passivation technique has received renewed interest in recent years., Subsequent thermal annealing can further improve the quality of insulator films deposited on GaAs. Meanwhile, during high temperature processing it is important to inhibit the loss of As within the GaAs substrate and also suppress the formation and subsequent incorporation of native oxides; these processes lead directly to electrical deterioration in GaAs MOS capacitors. The impact of rapid thermal annealing on the properties of various high-k/GaAs structures has been studied previously; the gas used in the annealing process influences the thermochemical mechanism as well as the interfacial quality. Nevertheless, correlations between these thermal reactions and the MOS performance have not been established in detail. In this study, we examined the material and electrical characteristics of ALD-Al2O3 thin films deposited on an

(NH4)2S-treated GaAs surface and then monitored the impact of thermal annealing

processing.

As mentioned in chapter 1, there are more defects on the interface between high-k materials and GaAs substrate. Thus, we should find a suitable deposition system to decrease these defects on the dielectric interface, achieving to obtain the high-quality dielectric film on

GaAs; ALD-Al2O3 is just what we want. As it is well known, Al2O3 is a widely used

insulating material for gate dielectrics, tunneling barriers and protection coatings due to its excellent dielectric properties, strong adhesion to dissimilar materials, and its exceptional thermal and chemical stabilities. Besides, Al2O3 has a high band gap (~ 9 eV), a high

breakdown electric field (5-30 MV/cm), high permittivity (8.6-10), high thermal stability (up to at least 1000oC), and remains amorphous under typical processing conditions. The leakage current observed in ultrathin Al2O3 on GaAs is equivalent to or lower than that of the

state-of-the-art SiO2 on Si. The breakdown electric field of Al2O3 film thicker than 50 Å can

be up to ~ 10 MV/cm; this value is near the bulk breakdown electric field for SiO2.

ALD is an ultrathin film deposition technique based on sequences of self-limiting surface reactions, which enables thickness control on the atomic scale. ALD deposition mechanism is like chemical vapor deposition (CVD). We introduce the unique feature of the step-by-step deposition in ALD by using a general example of Al2O3 film deposition. It is well known that

Al2O3 films can be grown by using alternating pulses of Al(CH3)3 (TMA, the aluminum

precursor) and H2O (the oxygen precursor) in the presence of N2 carrier gas flow. Its

mechanism procedures for one deposition cycle are illustrated in Fig. 2-1. At first, TMA is fed into the reactor and react with the OH bond on the GaAs substrate. Second, the reactor is purged with pure N2 gas to clean out residual TMA. Third, H2O is purged into the reactor and

residual H2O.

2-2 Experimental Procedures

MOSCAP structures were fabricated on high Si-doped (n-type, ~ 1x 1018 cm-3) GaAs (100) substrates. At first, the GaAs was rinsed in the diluted NH4OH (1%) solution for 1min.

And then, we performed (NH4)2S chemical treatment in combination with either H2O or

C4H9OH solution on GaAs surface prior to high-k deposition. Surface chemistry was analyzed

by employing x-ray photoelectron spectroscopy (XPS) that Al Kα is used as an excitation source. The Al2O3 gate dielectric was then deposited by ALD at 300 °C, followed by post

deposition annealing (PDA) at 600 °C for 30 s in an O2 ambient. Sputtered Pt dots about 700

Å were patterned as circular gate electrodes through the specific shadow mask with the Al for backside contact. The complete process flow was shown in Fig. 2-2. The C−V and I−V curves on Pt/Al2O3/GaAs MOS capacitors were measured using an HP4284 and Keithley 4200,

respectively.

2-3 Results and Discussions

2-3-1 Wet cleaning on GaAs

In the beginning, we chose different wet cleaning processes (WCPs) to eliminate native oxide such as Ga2Ox and As2O3. Table.1 shows these WCPs used in the study.

10% 10%--1min1min 1min 1min WCP2 WCP2 1min 1min 1min 1min WCP1 WCP1 NH NH₄₄OHOH ACE ACE clean clean 1% 1%- -10% 10%--1min1min 1min 1min WCP2 WCP2 1% 1%--1min1min 1min 1min WCP1 WCP1 NH NH₄₄OHOH ACE ACE clean clean

Table .1 Wet cleaning process of GaAs in this study

Here, NH4OH with different concentrations were explored. Fig. 2-3 displays the

core-level spectra of As 2p3, As 3d, Ga 2p3, and Ga 3d for GaAs substrates after WCPs, respectively. The binding energies of As2O3, As-As (called As layer), and GaAs substrate are

1326 eV, 1324.6 eV, and 1322.9 eV in As 2p3 spectrum, respectively. As seen, GaAs after WCP1 displays less As2O3 and As2O5 components than that after WCP2. Besides, the more

the NH4OH concentration used in GaAs clean, the more the As-rich surface was.

Subsequently, an ALD-Al2O3 gate dielectric was deposited at 300 °C to decompose surface

As-oxides because of the breaking of As-O bonding at 150~250 °C. Characteristics of Pt/Al2O3/GaAs MOS capacitors after different NH4OH WCPs with and without PDA at 600

°C for 30 sec in O2 ambient are plotted in Figs. 2-4 (a) and (b). We found that the annealed

Al2O3/GaAs MOS capacitors with 1%-NH4OH showed higher accumulation capacitance than

that with 10%-NH4OH. Fig. 2-5 displays the gate leakage current without (control) and with

PDA (both of WCP1 and WCP2). It was found that the 10%-NH4OH WCP, relative to the 1%

corresponding G-V characteristic with and without PDA. As we mentioned earlier, WCP with higher NH4OH concentration caused the onset of more As2OX, which is the origin of higher

gate leakage current. According to the chemical reaction: As2O3 + GaAs → Ga2O3 + 4As (△

G=-270 KJmol-1 at 300oC), we suggested that the lower As oxides existed close to the dielectric interface should accompany with the reduced formation of the metallic As by-product after thermal processing, thus, a lower leakage current was characterized. We also found that gate leakage increased after 600 °C PDA for 30 s in O2 ambient. The result can be

attributed to the thermal process providing more driving energy to accelerate the chemical reaction.

2-3-2

Surface treatment on GaAs

Figures 2-7 (a) and (b) display As2p3 and Ga2p3 photoemission spectra with different surface sulfur treatments; the composition ratios were summarized in Table II and Table III. It was observed that both kinds of native oxides, especially for As2Ox (x=3, 5), were

obviously reduced with using (NH4)2S solutions; moreover, the sulfide solution dissolved in

C4H9OH is more effective as compared to that dissolved in H2O. The values of

As2Ox/Astot(As-As/Astot) were 97.8%(30.1%) for GaAs surface with deionized water (DIW)

rinse only; its value can be reduced to 52.6%(22.6%) and 38.8%(20.1%) for the sulfide solution (H2O) [5-9]and the sulfide solution (C4H9OH) treatments, respectively.Increasing

the concentration of the sulfide solution (C4H9OH) can further eliminate the formation of As

oxides. Furthermore, we found that an increase in sulfide treatment temperature could reduce more As oxides on the surface. On the other hand, raising the sulfide concentration caused the formation of more Ga-S bonding with a decrease in As-S bonding; this can be attributed to the fact that the As-S bond was decomposed around 300 °C, and it might transform to stable Ga-S and metallic (The Gibber free energy was (-166 kJmol-1) at room temperature). Figs. 2-8(a) and (b) display the core-level spectra of Ga 3d and As 3d for GaAs substrate after ALD process, respectively. We found that the GaAs surface through sulfur treatment can return the ratio of Ga to As equal to 1, i.e., the stoichiometric GaAs, due to the effective reduction of surface GaAs defects

2-3-3 Surface roughness of sulfide GaAs

Figure 2-9 (a) shows the variation of GaAs surface roughness after the diluted NH4OH/D.I.W.(1%) cleaning with four sulfide conditions of (a) without (b) 1% C4H9OH

RT (c) 10% C4H9OH (d) 10% C4H9OH, 60oC. The surface roughness decreased from

0.284 to 0.232 nm as sulfide concentration and temperature increased. All the variations of surface roughness after different treatment were summarized in Fig. 2-8 (b), and the GaAs surface roughness indeed became smooth with (NH4)2S-C4H9OH treatment.

2-3-4 Electrical and material characteristics of MOSCAP

Fig. 2-10 shows 10 kHz C-V characteristics of Pt/Al2O3/GaAs MOS capacitor different

surface treatments. If the sulfur concentration increased to 10%, the higher capacitance we obtained on both accumulation and depletion regions. After the sulfur temperature was increased to 60 oC, this property was obtained emphatically. The reason could be probably attributed to an increase in either the interface state or the bulk trap density. Fig. 2-11 shows a simple device circuit biased in different conditions. It according to the following equation,

_C

_it

_{= q D}

_it

_A

_(2.1) We thus calculated the value of Cit approximately close to 100 pF. The value is closed to Cd .

In other words, the more the Dit is, the various the capacitance is. From the Jg characteristics

shown in Fig. 2-12, we observed that GaAs capacitors through 10% sulfide-C4H9OH

treatment actually possessed the higher thermal stability due to the smaller amounts of the As-As species and As oxides. According to two chemical reaction: One was As2O3 + GaAs →

Ga2O3 + 4As, The other was As2S3 + 3GaAs → 3GaS + 5As, we suggested that the lower As

oxides and As-S components existed close to the dielectric interface should accompany with the reduced formation of the metallic As by-product after thermal processing; therefore, a lower leakage current was characterized as well. As-S chemical bonds were broken at a relatively low temperature, approximately 150-250 oC, whereas adsorption of sulfur from the surface, through breaking Ga-S bonds occurs above 500 oC. At 300 oC ALD process, only

Ga-S bonds remained stable, whereas As-S bonds were possibly reduced into the metallic As. The Al2O3/GaAs after sulfur+H2O pretreatment showed the similar electrical characteristic as

sulfur+C4H9OH we mentioned earlier. C-V and J-V characteristics were shown in Fig.2-13 (a)

and (b), respectively. Figs. 2-14 (a) and (b) displayed the multi-frequency C-V curves after different sulfide treatments before and after PDA. Figs. 2-15 (a) and (b) displayed the calculated results of the frequency dispersion in these GaAs capacitors. We employed the variation of ΔC and ΔV values to examine the interface quality [10]. Here, the equations of ΔC and ΔV are reproduced as below

(@1 kHz) (@100 kHz) (@1 kHz) C C C C − Δ = (2.2) ΔV = V( @ 100 kHz C ) - V( @ 1 kHz C )_{FB FB} (2.3) where 1 1 1 FB ox DL C =C +C , (2.4)

CDL=1066 pF for GaAs, and Cox=1 kHz Cmax. From Fig. 2-15, we would find thatΔC andΔV

were lowed after passivation, especially with thermal sulfur treatment .In other words, Dit was

improved by passivation. It was observed that the sample subject to sulfide solution (C4H9OH)

revealed the smaller △C/△V than that with sulfide solution (H2O).The values of the △C

and △V were 17-20% and 0.9-1.4 V for the as-deposited sample and we can improve these two values to 17-14% and 0.6-0.7 V by using 10% sulfide solution (C4H9OH) . In Fig 2-15.,

we studied the variation of density of state (Dit) using single-frequency method [11], and

(2.5) 2 max max (2 / )( / ) [( / ) (1 / ) ] it ox m ox qA G D G C C C ω ω ≈ + − 2

where Gmax was the maximum conductance in the G-V plot with it’s corresponding

capacitance (Cm) . The Dit showed the decreasing with sulfide temperature and the input of

NH4OH solution. The lowest density state by wet chemical and sulfur passivation GaAs in

this work had reduced to 8.5x1012

cm

-2 eV-1.

The corresponding ALD-Al2O3/GaAs MOS capacitors after optimizing surface

treatment showed the comparable insulating properties with respect to HfSiOx dielectrics

reported on n-GaAs in Fig. 2-16(a). The value of leakage current was about 10-7 A/cm2 at CET=3.8 nm in our study. From the TEM image in Fig. 2-16(b), the physical thickness was 62 A, corresponding to the dielectric constant of ca. 6.9 for the deposited Al2O3 film by

using Eq. (2.6). 2 phy r s

t

CET

io

ε

=

ε

_(2.6)

2-3-5 InAs and InSb MOSCAP characteristics

The material parameters of GaAs, InAs, and InSb are listed in Table III. Though simple equation calculations, we can determine the minority carrier response time (τ) and transition frequency (ftran). Here, τ = C d/Ginv is defined, where Cd is the depletion

capacitance and Ginv is the conductance measured in inversion. Using the data of diffusion

concentration Nd = 1E17 cm-3 for InAs, while the Ldiff = ~10 um, τd ~ 5x 10-4 s, ni = 2E16

cm-3, Nd = 1E17 cm-3 for InSb. The values of Ginv were about 3 x 10-2 and 4 x 10-3 S/cm2 at

RT for InAs and InSb, respectively. Also, from the equation Cd =εr/Wd, whereεr is

material dielectric constant and Wd is the maximum depletion width in inversion. We can

estimate that the values of Cd are ca. 33 and 62 nF/cm2 for InAs and InSb, respectively.

Accordingly, the values of τ are calculated to be ca. 5 and 7 μs for InAs and InSb, which were more than three orders of magnitude shorter than the value obtained in Si MIS capacitors. This large difference can be understood due to the result of τ~ 1/Ginv ~1/ni

around RT as well as the lower energy gap, where ni values in InAs and InSb materials are

more than five orders of magnitude higher with respect to the conventional Si (1.5E10 cm−3). Due to the short minority response time in InAs and InSb, an inversion layer is formed fast in response to an external ac signal at the gate, so that a high capacitance, equal to Cox is

formed even at high frequencies i.e., 1 kHz. This is clearly observed in Fig. 2-17 where room temperature C-V curves are recorded at several frequencies. The response time τ also determines the transition frequency ftran. ~ (2πτ)-1(Cd/Cox), at which the capacitance in

inversion achieves the half of oxide capacitance Cox, marking the transition from low

frequency to high frequency behavior. We calculated the corresponding values of ftran. are

380 and 8500 kHz for InAs and InSb two materials, which is consistent with the experimental observations in C-V curves. Our calculation results indeed showed that the

high ni value in InAs and InSb is a good source of minority carriers for building-up of the

inversion layer fast. We also use different IPL such as sulfur treatment and Si passivation layer to eliminate native oxides in InAs and InSb. We found that the Si passivation was better than sulfur treatment in improving electrical characteristics. Figs. 2-18 (a)-(c) display the C-V and I-V characteristics, respectively, it was not efficient to reduce native oxides on both III-V materials, especially for InAs. In general, we assigned Fermi-level pinning and gate leakage to the resultant As-riched surface. However, we tried to deposit different Si passivation layer thickness to improve this phenomenon; unfortunately, the result was out of expectation. We summarize the leakage current characteristics versus the CET of these In-based MOS capacitors in Fig. 2-19. It was found that the higher the deposited temperature was employed, the severer degradation the surface occurred in both InAs and InSb. Finally, we still used the single frequency conductance method to calculate the Dit

value as the results displayed in Fig. 2-20. Obviously, it showed that these passivation methods were only suitable in GaAs MOS capacitor rather than In-based ones, in other words, it is essential to explore other passivation solutions to reduce the order of Dit as well

as the surface quality after dielectric deposition. In conclusions, it is believed that Fermi level pinning and gate leakage will be two main challenges in In-based substrates.

2-4 Summary

We systematically investigated the surface treatment effects on the electrical and material characteristics of GaAs MOS capacitors with ALD-Al2O3 gate dielectric. The sulfidization

pretreatment diminished the formation of GaAs native oxides and elemental As coverage close to dielectric interface, thus improving the effect of Fermi level pinning on the Al2O3/GaAs capacitors. The sulfidized GaAs samples displayed not only smaller frequency

dispersion with higher oxide capacitance but also decreased Dit, and Jg, respectively. Post

thermal annealing of GaAs MOSCAP can alleviate the charge trapping behavior, and decrease the amount of metallic As and the value of Dit. it is believed that Fermi level pinning and gate

leakage will be two main challenges in In-based substrates. On the other hand, we calculated t he corresponding values of ftran. are 380 and 8500 kHz for InAs and InSb MOSCAPs,

consistent with the experimental observations in C-V curves. It also reflects that a high ni

value is a good source of minority carriers for building-up of the inversion layer fast in these two lower band-gap materials. We also found the passivation methods used in GaAs MOSCAP are not suitable in InAs and InSb MOSCAPs. So that, it is essential to explore other passivation solutions to improve the dielectric/InAs(Sb) interface quality. In conclusions, we believed that Fermi level pinning and gate leakage will be two main challenges in In-based substrate.

References

[1] V. N. Bessolov, E V. Konenkova, M V. Lebedeva) , J. Vac. Sci. Technol. B, 14( 1996). [2] V.N. Bessolovy, M.V. Lebedevy, N. M. Binhz, M. Friedrichz , D. T. Zahnz” Sulphide

passivation of GaAs: the role of the sulphur chemical activity.” Semicond. Sci. Technol.

13 (1998) 611–614.

[3] Hyoung-Sub Kim, Injo Ok, Manhong Zhang, Tackhwi Lee, Feng Zhu, Lu Yu, and Jack C. Lee, Appl. Phys. Lett. 89, (2006) 222903

[4] Hyoung-Sub Kim, Injo Ok, Manhong Zhang, Changhwan Choi, Tackhwi Lee, Feng Zhu, Gaurav Thareja, Lu Yu, and Jack C. Lee, Appl. Phys. Lett. 88, (2006)252906

[5] J. F. Fan, H. Oigawa, and Y. Nannichi, Jpn. J. Appl. Phys., Part 1 27, L1331 (1998) [6] H. Sugahara, M. Oshima, H. Oigawa, H. Shigekawa, and Y. Nannichi, J. Appl. Phys. 69,

4349 (1991)

[7] N. Yokoi, H. Andoh, and M. Takai, Appl. Phys. Lett. 64, 2578 (1994)

[8] X. Y. Hou, W. Z. Cai, Z. Q. He, P. H. Hao, Z. S. Li, X. M. Ding, and X. Wang, Appl. Phys. Lett. 60, 2252 (1992)

[9] A. Jaouad, V. Aimez, C. Aktik, K. Bellatreche, and A. Souifi, J. Vac. Sci. Technol. A 22, 1027 (2004)

[10] W. P. Li, X. W. Wang, Y. X. Liu, S. I. Shim, and T. P. Ma, Appl. Phys. Lett. 90, 193503 (2007)

~ MOSCAP Process Flow ~

Al

n-GaAs (ND=1E18cm-3)

Cleaning： ACE + NH4OH(aq.) ~

IPL (NH4)2S + C4H9OH (NH4)2S + H2O IPL： Al2O3 Al2O3：ALD at 300oC-60cys Post anneal O2 600oC 30S Pt Pt：70 nm by sputtering Back contact Al 300 nm

1124 1122 1120 1118 1116 1114 1112 GaO P hoto e lec tron inten s ity (arb . units )

Binding Energy (eV)

1% NH4OH 10% NH4OH Ga2p3 GaAs Ga₂O₃ 48 46 44 42 40 38 36 P h o to e le c tr on int e n s it y (a rb. un it s ) As₂O₃ 1% NH₄OH 10% NH4OH

Binding Energy (eV)

As3d GaAs 1332 1330 1328 1326 1324 1322 1320 1318 1316 As₂O₃ Intensit y (a.u.)

Binding Energy (eV)

1% NH₄OH 10% NH₄OH

As2p3

As₂O₅

-2 -1 0 1 2 3 4 100 150 200 250 300 350 400 100K 10K 1K AI2O3-300OC-60cys/GaAs C apacita nce (p F)

Gate voltage V_g (volt)

solid - NH₄OH-1%

open - NH₄OH-10%

Fig. 2-4 (a) Multi-frequency C-V characteristics of MOS capacitors (Pt/Al2O3/GaAs) with 1%

and 10% concentration of dilute ammonia. The Al2O3 was deposited by ALD (300 oC,

60 cycles) -2 -1 0 1 2 3 100 150 200 250 300 350 400 450 500 solid - NH₄OH-1%

Fig. 2-4 (b) Multi-frequency C-V characteristics of MOS capacitors (Pt/Al2O3/GaAs) with

post deposit annealing at 600 oC in the O2 ambient. (ALD ,300 oC, 60 cycs).

open - NH₄OH-10% AI₂O₃-300OC-60cys-PDA O₂ / GaAs Capa citan ce (p F)

Gate voltage V_g (volt)

100K

10K 1K

0 1 2 3 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 NH 4OH-10% NH 4OH-1%

solid - w/o PDA open - with PDA O₂

300oC-AI₂O₃( 60cys) / GaAs Leak age cur re nt dens ity J g (A /c m 2 ) Gate voltage V_g (V)

Fig 2-5 J-V characteristics of Pt/Al2O3/GaAs MOS capacitor with 1% and 10%

concentration of dilute ammonia. The Al2O3 was deposited by ALD (300 oC, 60 cycles).

-2 -1 0 1 2 3 10-8 10-7 10-6 10-5 10-4 Gm (S) 300oC-AI₂O₃( 60cys)/GaAs Gate voltage V_g (V) as dep. O₂ 600oC PDA

Fig. 2-6 G-V characteristics of Pt/Al2O3/GaAs MOS capacitor with and without 600 oC O2

26.4% 26.4% 22.7% 22.7% 24.6% 24.6% 25.1% 25.1% 7.1% 7.1% 7.3% 7.3% 10.9% 10.9% 13.9% 13.9% 1%Sulf.(H 1%Sulf.(H22O)O) 1%Sulf.(C

1%Sulf.(C44HH99OH)OH)

10% 10%--(C(C44HH99OH)OH) 10%(C 10%(C4₄HH99OH)OH)-- 6060ooCC 25.8% 25.8% --NH NH₄4OH onlyOH only 54.3% 54.3%

--D.I water only

D.I water only

Ga

Ga₂₂OO_xxrr/Ga/Ga_totaltotal

Ga

Ga--S/GaS/Ga_totaltotal condition condition 26.4% 26.4% 22.7% 22.7% 24.6% 24.6% 25.1% 25.1% 7.1% 7.1% 7.3% 7.3% 10.9% 10.9% 13.9% 13.9% 1%Sulf.(H 1%Sulf.(H22O)O) 1%Sulf.(C

1%Sulf.(C44HH99OH)OH)

10% 10%--(C(C44HH99OH)OH) 10%(C 10%(C4₄HH99OH)OH)-- 6060ooCC 25.8% 25.8% --NH NH₄4OH onlyOH only 54.3% 54.3%

--D.I water only

D.I water only

Ga

Ga₂₂OO_xxrr/Ga/Ga_totaltotal

Ga

Ga--S/GaS/Ga_totaltotal condition condition 1122 1120 1118 1116 1114 1122 1120 1118 1116 1114 1122 1120 1118 1116 1114 GaS GaAs Ga₂O₃ 10%Sulf.(C₄H₉OH+60oC) 10%Sulf.(C₄H₉OH) 1%Sulf.(C₄H₉OH)

Fig. 2-7 (a) XPS spectrum Ga 2p3 after different cleaning processes of Table II.

1122 1120 1118 1116 1114 1122 1120 1118 1116 1114 1122 1120 1118 1116 1114 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 ₁₈ 19 20 21 Ga₂O₃ GaO 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 GaAs

Binding Energy (eV)

D.I only

NH₄OH only

1%Sulf.(H₂O)

Table II. Chemical ratio by XPS spectra of Ga 2p3 corresponding to different cleaning processes and sulfur treatment.

1330 1328 1326 1324 1322 1320 1318

1330 1328 1326 1324 1322 1320 1318

1330 1328 1326 1324 1322 1320 1318

As₂O₅

As₂O₃As-As _GaAs

Binding Energy (eV)

1330 1328 1326 1324 1322 1320 1318 1330 1328 1326 1324 1322 1320 1318 1330 1328 1326 1324 1322 1320 1318 As-S As₂O₅ As₂O₃ As-As GaAs

Fig. 2-7 (b) XPS spectrum As 2p3 after different cleaning processes of Table III.

52.6% 52.6% 38.8% 38.8% 23.2 % 23.2 % 14.2 % 14.2 % 18.9% 18.9% 17.8% 17.8% 16.3% 16.3% 15.7% 15.7% 22.6% 22.6% 20.1% 20.1% 13.9% 13.9% 17.1% 17.1% 1%Sulf.(H 1%Sulf.(H₂2O)O) 1%Sulf.(C

1%Sulf.(C44HH99OH)OH)

10%Sulf.(C

10%Sulf.(C₄4HH99OH)OH)

10%Sulf.(C 10%Sulf.(C₄4HH99OHOH -- 6060oo_CC 73.4% 73.4% --23.5% 23.5% NH NH₄4OH onlyOH only 97.8% 97.8% --30.1% 30.1%

D.I water only

D.I water only

As

As₂₂OO_33rr/As/As_toto

tal tal

As

As--SS_rr/As/As_totaltotal As

As-

-As/ As/AsAs_totaltotal

condition condition 52.6% 52.6% 38.8% 38.8% 23.2 % 23.2 % 14.2 % 14.2 % 18.9% 18.9% 17.8% 17.8% 16.3% 16.3% 15.7% 15.7% 22.6% 22.6% 20.1% 20.1% 13.9% 13.9% 17.1% 17.1% 1%Sulf.(H 1%Sulf.(H₂2O)O) 1%Sulf.(C

1%Sulf.(C44HH99OH)OH)

10%Sulf.(C

10%Sulf.(C₄4HH99OH)OH)

10%Sulf.(C 10%Sulf.(C₄4HH99OHOH -- 6060oo_CC 73.4% 73.4% --23.5% 23.5% NH NH₄4OH onlyOH only 97.8% 97.8% --30.1% 30.1%

D.I water only

D.I water only

As

As₂₂OO_33rr/As/As_toto

tal tal

As

As--SS_rr/As/As_totaltotal As

As-

-As/ As/AsAs_totaltotal

condition condition

Table III. Chemical ratio by XPS spectra of As 2p3 corresponding to different cleaning processes and sulfur treatment.

32 30 28 26 24 22 20 18 16 GaAs NH4OH only 1%-C4 10%-C4 1%-C4-60oC 10%-C4-60oC In tensity (a .u.)

Binding Energy (eV)

Ga 3d

overlap with O 2s

Fig. 2-8 (a) XPS spectrum Ga 3d with different surface treatment after ALD process

48 46 44 42 40 38 In te n s ity (a .u .)

Binding Energy (eV)

NH₄OH only 1%-C4 10%-C4 1%-C4-60oC 10%-C4-60oC As 3d GaAs As₂O_x

NH

₄

OH-only

NH

₄

OH-only

_1%-C

4

H

9

OH

1%-C

₄

H

₉

OH

10%-C

₄

H

₉

OH

10%-C

₄

H

₉

OH

10%-C

10%-C

₄₄

H

H

₉₉

OH-60

OH-60

oo

C

C

NH4OH 1%-C4 10%-C4 1%C4-60C 10%C4-60C 0.10 0.15 0.20 0.25 0.30 0.35 0.40 S u rf ace r o ughness R m s (n m)

C

ox

C

_D

_G

_inv

_=G

_gr

_+G

_diff

C

inv

Inversion

C

ox

C

_D

_G

_inv

_=G

_gr

_+G

_diff

C

inv

C

ox

C

_D

_G

_inv

_=G

_gr

_+G

_diff

C

inv

Inversion

-2 -1 0 1 2 3 100 150 200 250 300 350 400 450

open - with PDA 600OC 30S close - w/o annealing

Pt/AI₂O₃/IPL(Sulf.+C₄H₉OH)/GaAs

Cap acitan ce (p F) Gate voltage V_g (V) freq.=10k

Fig. 2-11 Capacitances of an MOS capacitors for various bias conditions

1%, RT

10%, RT

10%, 60oC

Fig. 2-10 The C-V(10kHz) curves of Pt/Al2O3/GaAs MOS capacitors with

(NH4)2S+C4H9OH treatments. The Al2O3 was deposited by ALD (300 oC, 60

cycs.).

C

_OX

C

_D

C

_it

C

_OX

C

_D

C

_it

Depletion

0 1 2 3 10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1

100 Pt/AI2O3/IPL(Sulf.+C4H9OH)/GaAs

Fig. 2-12 J-V characteristics of Pt/Al2O3/GaAs MOS capacitor (NH4)2S+C4H9OH with and

without 600 oC O2 PDA. The Al2O3 was deposited by ALD (300 oC, 60 cycles)

1%, RT 10%, RT 10%, 60oC L e ak ag e cu rr e n t d e n s it y Jg (A/ c m 2 ) Gate voltage V_g (V) open - with PDA 600OC 30S