應用類比電路設計及覆晶封裝技術於毫米波高速電子遷移率電晶體之收發機

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國立交通大學

電信工程學系

博士論文

應用類比電路設計及覆晶封裝技術

於毫米波高速電子遷移率電晶體之

收發機

Millimeter-Wave HEMT Transceiver

With Analog Circuit Design Approach

and Flip-Chip Technology

研究生：蘇珍儀

指導教授：孟慶宗

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應用類比電路設計及覆晶封裝技術於毫米

波高速電子遷移率電晶體之收發機

Millimeter-Wave HEMT Transceiver With

Analog Circuit Design Approach and

Flip-Chip Technology

研究生：蘇珍儀

Student:

Jen-Yi

Su

指導教授：孟慶宗博士 Advisor:

Dr.

Chinchun

Meng

國立交通大學

電信工程學系

博士論文

A Dissertation

Submitted to Institute of Communication Engineering

College of Electrical and Computer Engineering

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of Doctor of Philosophy

in

Communication Engineering

Hsinchu, Taiwan

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i

應用類比電路設計及覆晶封裝技術於毫米波高

速電子遷移率電晶體之收發機

學生:蘇珍儀指導教授:孟慶宗博士

Abstract (Chinese)

國立交通大學

電信工程學系博士班

摘

要

在本論文中，是以 0.15 微毫米砷化鎵(GaAs)假晶格高速電子遷移電晶體（pHEMT）及變形晶格高速電子遷移電晶體(mHEMT)來設計毫米波頻段的類比積體電路與單晶微波積體電路。這些砷化鎵的技術具有高崩潰電壓，截止頻率，低雜訊，高輸出功率和半絕緣基板的優點。除此，高頻電路的封裝技術也很重要，在此採用覆晶封裝技術來驗證V 頻段的放大器在封裝前後有一樣的特性。在第二章中，使用0.15 微毫米砷化鎵 pHEMT 來提出設計在 Ku 跟 Ka 頻帶的三種吉伯特混頻器。由於半絕緣的砷化鎵基版，微波被動元件具低損耗而且多重相位濾波器可以操作在較高的頻段。利用高精確的氮化鉭薄膜式電阻可設計多重相位濾波器而產生完美的正交相位。因此，我們所提出的15 GHz 單頻帶升頻器具有63 dB 的單邊頻帶消除比率，另一個 34 GHz 次諧波正交輸出的降頻器可達到小於0.4 dB 的振幅與 1˚相位的誤差，且超過 50 dB 的本端振盪源（LO）洩漏壓制。再者，提出40 GHz 次諧波堆疊式-LO 電路使用補償式技術來解決延遲時間的問題而且比較我們之前所發表論文可以減少電晶體數量。

在第三章比較 Q 頻帶 0.15 微毫米 PHEMT 及 mHEMT 的次諧波堆疊式-LO 升頻器在增益，隔絕度及線性度上的差異。一般來說，0.15 微毫米 mHEMT 的

元件比pHEMT 具有較高的轉導和截止頻率。所以在設計主動吉伯特混頻器，使

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Abstract (Chinese) ii 製程來設計Q 頻帶的次諧波堆疊式-LO 升頻器，經量測分別有-7.1 dB 及-0.2 dB 的轉換增益。pHEMT 的升頻器有-12 dBm 的輸出三階截止點和-24 dBm 的輸出 1dB 壓縮點，此時 mHEMT 線性度改善有 4 dB 在於輸出 1dB 壓縮點與輸出三階截止點的差值。在第四章節展現 V 頻帶的共平面波導-微帶線-共平面波導兩級放大器結合覆晶封裝技術。為了配合覆晶封裝的結構，輸入與輸出端則設計共平面波導，而中間級則採用微帶傳輸線來減少晶片面積。在這兩級放大器著重是在第一級利用電晶體當作共平面波導轉換成微帶線，及在第二級利用電晶體將微帶線轉換成共平面波導。共平面波導-微帶線-共平面波導轉換的兩級放大器在 53 GHz 有 14.8 dB 的增益，10 dB 及 22 dB 的輸入及輸出反射係數。經過覆晶封裝後的量測放大器特性也跟沒有覆晶封裝前幾乎差不多。在第 5 章節說明使用 mHEMT 製程設計一個 60 GHz 單晶微波積體電路接收機。接收機包括一個LO 倍頻串，60 GHz 鏡像消除二極體混頻器及一個 60GHz 的三級低雜訊放大器。LO 倍頻串的形成是採用一個乘三器及一個三級的回授放大器。而 60GHz 的鏡像消除混頻器則採用對稱式的次諧波二極體混頻器且結合了IF 及三倍 LO 頻率的正交分合波器。這 60 GHz mHEMT 接收機有 5 dB 的轉換增益，7 dB 的雜訊指數和 22 dB 的鏡像消除比率。且有-24 dBm 的輸入 1dB 壓縮點和-16 dBm 的輸入三階截止點。第六章節報告用 pHEMT 製程設計在 Ka 頻帶正交輸出除二的米勒除頻器。架構是基於一個正向回授的迴路，包含了一個馬爾尚巴倫，兩個乘法器和LC 槽濾波器。除頻器使用單邊頻帶升頻器來驗證正交輸出的精確度。可達到35 dB 的旁波帶消除比率。最小的輸入靈敏度是2.7 dBm，可除的頻寬從 32 到 36 GHz 比率是12％。關鍵字：補償、降頻器、多重相位濾波器、假晶格高速電子遷移率電晶體、正交、

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1.1 Advantages of HEMT Technology

iii

單邊頻帶、次諧波、升頻器、變形晶格高速電子遷移率電晶體、共平面波導管、覆晶封裝、微帶線、60 GHz、單晶片、砷化鎵、完全整合、鏡像消除、接收機、單晶微波積體電路、混頻器、除二、馬爾尚巴倫、米勒除頻器、乘法器。

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v

Millimeter-Wave HEMT Transceiver With

Analog Circuit Design Approach and Flip-Chip

Technology

Student: Jen-Yi Su Advisor: Chinchun Meng

Department of Communication Engineering

National Chiao Tung University

Abstract (English)

In this dissertation, all analog integrated circuits and monolithic microwave integrated circuits (MMICs) are demonstrated using 0.15-m pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) technologies. These GaAs-based technologies have the advantages of a high breakdown voltage, cutoff frequency, low noise figure, higher output power, and semi-insulating substrate. Furthermore, a package technique is an important key for high-frequency circuits. The flip-chip technique is demonstrated that the performances of V-band amplifiers with and without flip-chip are almost the same.

In Chapter 2, three kinds of Ka/Ku-band Gilbert mixers are demonstrated using pHEMT technology. Thanks to the semi-insulating GaAs substrate, microwave passive components have a low-loss feature, and polyphase filters work up to higher frequencies. Highly accurate Tantalum Nitride (TaN) thin film resistors utilized in polyphase filters result in perfect quadrature operation. Therefore, our proposed single-sideband up-converter operates at 15 GHz with a 63-dB sideband rejection ratio, and another 34-GHz I/Q subharmonic down-converter reaches < 0.4-dB

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Abstract (English)

vi

magnitude and < 1° phase errors. More than 50-dB LO leakage suppression is achieved in the I/Q subharmonic mixer. On the other hand, a 40-GHz stacked-LO subharmonic mixer with a novel compensation technique is also proposed and demonstrated to improve LO speed and reduce the amount of transistors as compared to the previous work.

Chapter 3 makes a comparison between Q-band 0.15 μm pHEMT and mHEMT stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 μm mHEMT device has a higher transconductance and cutoff frequency than a 0.15 μm pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of -7.1 dB and -0.2 dB, respectively. The pHEMT upconversion mixer has an OIP3 of -12 dBm and an OP1dB of -24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the OIP3 and OP1dB.

In Chapter 4, the V-band coplanar waveguide (CPW)-microstrip line (MS)-CPW two-stage amplifier with the flip-chip bonding technique is demonstrated. The CPW is used at input and output ports for flip-chip assemblies and the MS transmission line is employed in the interstage to reduce chip size. This two-stage amplifier employs transistors as the CPW-MS transition and the MS-CPW transition in the first stage and the second stage, respectively. The CPW-MS-CPW two-stage amplifier has a gain of 14.8 dB, input return loss of 10 dB and output return loss of 22 dB at 53.5 GHz. After the flip-chip bonding, the measured performances have almost the same value.

A 60 GHz single-chip receiver MMIC using 0.15-μm mHEMT technology is demonstrated in Chapter 5. The receiver consists of an LO multiplier chain, a 60 GHz

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Abstract (English)

vii

three-stage low noise amplifier, and 60 GHz image rejection diode mixer. The LO chain is formed with a tripler and a 28 GHz three-stage feedback amplifier. Furthermore, the 60 GHz image rejection mixer is a symmetrical subharmonic diode mixer and integrated with IF and 3 × LOquadrature hybrids. The mHEMT receiver has the conversion gain of 4 dB, the noise figure of 7.0 dB, and the image rejection ratio of 22 dB at 60 GHz. The -24 dBm IP1dB and -16 dBm IIP3 are measured.

Chapter 6 reports a Ka-band quadrature-output divide-by-two Miller divider using the 0.15-μm pHEMT technology. The circuit topology consists of one Marchand balun, two active multipliers and LC-tank filters with a positive feedback loop. The divider includes a single side-band (SSB) up-converter to verify the quadrature accuracy of the divider’s outputs. A 35-dB side-band rejection ratio is achieved. The minimum input sensitivity equals 2.7 dBm. The stable division from 32 to 36 GHz in a bandwidth of 12 % can be obtained.

Keywords: Compensation, down-converter, polyphase filter, pseudomorphic high electron mobility transistor (pHEMT), quadrature, single sideband (SSB), subharmonic, up-converter, metamorphic high electron mobility transistor (mHEMT), coplanar waveguide (CPW), flip-chip, microstrip line (MS), 60 GHz, single-chip, GaAs, fully integrated, image rejection, receiver (RX), MMIC, mixer, divide-by-two, Marchand balun, Miller divider, multiplier.

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ix

Acknowledgements

最重要的是要感謝父親蘇寬及母親蔣秀卿小姐，及兄姐等親人給

予我一路上的扶持與鼓勵，讓我更有信心繼續支持下去直到完成博士

學位。

很感謝我的指導老師孟慶宗教授，孟教授不論在學業或研究上都

惠我良多，使我一次比一次進步，孟教授給予我機會磨練自己，眾多

的訓練及教誨使我能有今天的成就與學術上的貢獻。

謝謝材料系張翼教授的科專計畫，讓我們生活上不至於困乏，且

提供設備及下線機會。另外也謝謝國家晶片系統設計中心提供晶片實

作機會，還有國家奈米元件實驗室高頻技術中心黃國威博士提供我們

完善且舒適的量測環境，及優秀量測團隊：佳松學長、書毓、汶德、

國祥和小鄧等人提供專業協助。

博士班的成員：宗翰、聖哲、宏儒、及金詳，謝謝你們陪我走過

這些日子，當我遇到困難時候，你們總是能提供我專業的意見，這段

漫長艱辛的路只有你們知道。曾經參與科專的主要優秀成員，從慶

鴻、智凱、家宏、約停、揚鮮、大維及泰麟學弟，這

6 年的計畫如果

沒有你們的努力與配合，也不會今天豐碩的成果。雖然這一路上走來

很辛苦，但是我相信這在人生的道路上可以增強自己的心智。還有實

驗室的金釵學妹們，宜蓁、雅惠、宜珊、欣怡及嘉苓，謝謝你們陪我

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Acknowledgements x

分享不能說的心事。最貼心及帶給我歡笑的學弟柏誼、冠璋、勝文、

宇文、樺輿、熙良及忠佑，生活多了你們才能忘記痛苦且帶來歡樂。

曾經為了資格考所組的讀書會成員：順子、憲宏及繼禾，很感恩你們

一路上對我不論是生活上或是課業上的關心及照顧。另外很感謝助理

小薔，你總是在我有麻煩時候都助我一臂之力，分享心事。謝謝我身

邊曾經出現過的人，不管是訓練我的或是關心我的，因為有了你們，

才有今天成長茁壯的我，謝謝大家。

蘇珍儀

NCTU, April 2009

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xi

List of Figures

Chapter 1

Fig. 1-1 Profile of a GaAs-based HEMT structure. ...2

Fig. 1-2 Millimeter-wave atmosphere absorption...4

Fig. 1-3 (a) Block diagram and (b) chip photograph of the 77-GHz transceiver MMIC (2.0mm × 3.0mm) [Siemens, MTT 1998]. ...5

Fig. 1-4 Circuit block diagrams of (a) Tx and (b) Rx chips at 60 GHz [Herbert, JSSC 2005, 2007]. ...6

Fig. 1-5 (a)The pHEMT transmitter chip measures 5.0 mm × 3.5 mm and (b) the pHEMT receiver chip is 5.7 mm × 5.0 mm [Herbert, JSSC 2005]...6

Fig. 1-6 Sizes of (a) the mHEMT transmitter chip and (b) the mHEMT receiver chip are 4.0 mm × 3.0 mm and 5.5 mm× 3.0 mm, respectively [Herbert, JSSC 2007].7 Fig. 1-7 Flip-chip bonding profile of MMIC chip on a carrier. ...8

Chapter 2

Fig. 2-1 Two-section RC-CR polyphase filter structure. ...14

Fig. 2-2 Magnitude and phase errors of the two-section polyphase filter by Monte Carlo simulations with resistance and capacitance variations. ...14

Fig. 2-3 Rejection ratio of Si- and GaAs-based polyphase filters by Monte Carlo simulations. ...16

Fig. 2-4 Differential quadrature generator consists of (a) one coupler with two baluns or (b) one balun with two couplers...17

Fig. 2-5 Time-delay (θ) compensation analysis for the compensated stacked-LO subharmonic mixer...19

Fig. 2-6 Time-delay-compensated LO multipliers [35]. ...19

Fig. 2-7 Simple block diagram of a Ka-band system...21

Fig. 2-8 Block diagram of an SSB up-converter...24

Fig. 2-9 Circuit topology of a 15-GHz SSB up-conversion mixer using depletion mode AlGaAs/InGaAs pHEMT technology. ...24

Fig. 2-10 Micrograph of a 15-GHz pHEMT SSB Gilbert up-converter. ...26

Fig. 2-11 SSB suppression performance of the pHEMT SSB Gilbert up-converter. 63-dB sideband rejection is achieved. ...26

Fig. 2-12 Measured and simulated RF output return loss and measured conversion gain of the pHEMT SSB Gilbert up-converter. ...27

Fig. 2-13 Power performance of the pHEMT SSB Gilbert up-converter when IF1=0.18 GHz and IF2=0.28 GHz. ...28 Fig. 2-14 Micrograph of the 34-GHz pHEMT double-quadrature subharmonic

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List of Figures

xiv

Gilbert mixer. ...29 Fig. 2-15 Schematic of the 34-GHz I/Q subharmonic down-conversion mixer. ...29 Fig. 2-16 IF output waveforms of the 34-GHz I/Q subharmonic down-converter...30 Fig. 2-17 Measured phase error and output difference of the 34-GHz I/Q

subharmonic down-converter...31 Fig. 2-18 Measured and simulated RF input return loss and measured noise figure of the 34-GHz pHEMT leveled-LO subharmonic Gilbert down-converter. ...32 Fig. 2-19 Power performance of the I/Q subharmonic Gilbert down-converter when

RF1=34.1 GHz and RF2=34.16 GHz...32 Fig. 2-20 Schematic of the 40-GHz pHEMT stacked-LO subharmonic Gilbert

down-conversion mixer with a time-delay compensation technique...33 Fig. 2-21 Micrograph of the 40-GHz pHEMT compensated stacked-LO

subharmonic Gilbert down-conversion mixer...34 Fig. 2-22 Measured conversion gain and noise figure of the 40-GHz pHEMT

stacked-LO subharmonic down-converter. ...35 Fig. 2-23 Power performance of the 40-GHz compensated stacked-LO Gilbert

down-converter when RF1=40.101 GHz and RF2=40.201 GHz...35

Chapter 3

Fig. 3-1 Measured drain-to-source current (Ids) and tranconductance (gm) with respect to gate-to-source voltage for both pHEMT and mHEMT. ...38 Fig. 3-2 The stacked-LO subharmonic Gilbert upconverter. ...39 Fig. 3-3 Micrographs of (a) mHEMT and (b) pHEMT Gilbert upconverters...40 Fig. 3-4 Measured conversion gain of the pHEMT and mHEMT Gilbert

upconverters when the LO frequency is fixed at 20/19 GHz, respectively. ...41 Fig. 3-5 Measured output performances of pHEMT and mHEMT upconverters

when IF1=100 MHz and IF2=150 MHz . ...41 Fig. 3-6 Measured LO-to-RF and 2LO-to-RF isolations of pHEMT and mHEMT

upconverters...41

Chapter 4

Fig. 4-1 The CPW-MS transition by pHEMT with via holes at the source terminals. ...46 Fig. 4-2 Loss versus frequency for various ground widths with signal width of 20

um, length of 200 um and slot spacing of 17 um...47 Fig. 4-3 Characteristic impedance versus frequency for various ground widths with

signal width of 20 um, length of 200 um and slot spacing of 17 um...48 Fig. 4-4 Gain curves of the MS-MS, CPW-MS, MS-CPW and CPW-CPW one-stage

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List of Figures

xv

amplifiers with the same impedance matching...49 Fig. 4-5 The V-band CPW-MS-CPW two-stage pHEMT amplifier. ...50 Fig. 4-6 Die photo of the CPW-MS-CPW two-stage pHEMT amplifier. ...51 Fig. 4-7 Flip-chip photograph of the CPW-MS-CPW two-stage pHEMT amplifier.

...51 Fig. 4-8 (a)S11 & S21 (b) S12 & S22 of the simulation (without flip-chip bonding) and

measurement (with and without flip-chip bonding) CPW-MS-CPW two-stage pHEMT amplifiers. ...53

Chapter 5

Fig. 5-1 Fully integrated 60 GHz receiver. ...56 Fig. 5-2 LO multiplier chain consists of a tripler and a three-stage amplifier...57 Fig. 5-3 Schematic of an image rejection mixer and analysis of a quadrature hybrid.

...58 Fig. 5-4 60 GHz three-stage low noise amplifier with finite-ground coplanar

waveguide (FGCPW) input matching network...59 Fig. 5-5 Micrograph of the 60 GHz mHEMT receiver. ...60 Fig. 5-6 Flip-chip photo of the 60 GHz mHEMT receiver. ...60 Fig. 5-7 Measured conversion gain, noise figure and image rejection ratio versus RF frequencies when IF = 4.2 GHz before and after flip-chip bonding...60 Fig. 5-8 Measured conversion gain and image rejection ratio versus IF frequencies

when LO = 9.3 GHz before and after flip-chip bonding. ...61 Fig. 5-9 Linearity performances of the 60GHz mHEMT receiver with and without

flip-chip while the RF1=60 GHz and RF2=60.01GHz. ...62 Fig. 5-10 LO-IF and 3LO-IF isolations before and after flip-chip bonding. ...62

Chapter 6

Fig. 6-1 Block diagram of the quadrature-output regenerative frequency divider and its input and output waveforms...66 Fig. 6-2 Circuit topology of the quadrature-output regenerative frequency divider

using a depletion mode AlGaAs/InGaAs pHEMT technology. ...67 Fig. 6-3 Micrograph of the 32~36 GHz pHEMT analog cascode regenerative

frequency divider with the single side-band up-converter test. ...68 Fig. 6-4 Input sensitivity of the Miller frequency divider...69 Fig. 6-5 Output spectrum of the divide-by-two Miller frequency divider. ...70 Fig. 6-6 Measured side-band rejection ratio of the 32~36 GHz pHEMT

quadrature-output divider...70 Fig. 6-7 Phase noise performance of the Ka-band pHEMT divider with a 35-GHz

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List of Figures

xvi

source input...70

Appendix A

Fig. A-1 Symbols for (a) quadrature coupler and (b) back-to back coupled-line Marchand balun. ...82 Fig. A-2 Simulated input return loss of the two differential quadrature generators in

Fig. 2-4...82

Appendix B

Fig. B-1 Schematic of the pHEMT single-quadrature Gilbert down-conversion mixer. ...85 Fig. B-2 Photograph of the single-quadrature Gilbert down-conversion mixer using

depletion mode pHEMT technology...85 Fig. B-3 37-dB image rejection ratio and 5.5-dB conversion gain are measured in

the pHEMT single-quadrature Gilbert down-conversion mixer. ...87 Fig. B-4 Measured linearity performances of IP1dB and IIP3. ...87

Appendix C

Fig. C-1 Design dimension of the V-band CPW Lange coupler. ...89 Fig. C-2 Simulation of the CPW Lange coupler. ...89 Fig. C-3 Circuit schematic of the balanced amplifier with CPW Lange couplers....90 Fig. C-4 (a) Die photograph of the balanced amplifier with the CPW Lange coupler

and (b) a photo of the V-band balanced amplifier with flip-chip technology. ..90 Fig. C-5 Measured S-parameters of the V-band balanced amplifier...92 Fig. C-6 Measured power performance of the balanced amplifier. ...92

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xvii

List of Tables

TABLE 1-1 Typical data of pHEMT and mHEMT technologies [Herbert, MTT 2006]. ...3 TABLE 3-1 Performance comparisons of up-conversion mixers...42 TABLE 5-1 Performance comparisons of the state-of-the-art 60 GHz receivers ...64

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xviii

List of Abbreviations and Symbols

Abbreviations

CPW Coplanar Waveguides

CG Conversion Gain

EM Electromagnetic

FGCPW Finite-Ground Coplanar Waveguide

GSGSG Ground–Signal–Ground–Signal–Ground

I/OP1dB Input/Output 1-dB Gain Compression Point I/OIP3 Input/Output Third-Order Intercept Point

I/Q In-Phase/Quadrature

IC Integrated Circuit

LO Local Oscillator

LNA Low Noise Amplifier

MS Microstrip Line

MMIC Monolithic Microwave Integrated Circuit MIM Metal-insulator-metal

NF Noise Figure

mHEMT metamorphic High Electron Mobility Transistor pHEMT pseudomorphic High Electron Mobility Transistor RFD Regenerative Frequency Divider

RX Receiver

SSB Single Side-Band

SOC System-on-Chip

TX Transmitter

TaN Tantalum Nitride

Symbols

λ Wavelength

ω0 Operating frequency, resonant frequency fT Cut-off frequency

fmax Maximum Oscillator Frequency gm Transconductance of a transistor

k Coupling factor

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1.1 Advantages of HEMT Technology

xix

Z0 Terminal impedance

Z0e Even-mode characteristic impedance Z0o Odd-mode characteristic impedance

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1

Chapter 1 Introduction

1.1 A

DVANTAGES OF

HEMT

T

ECHNOLOGY

Until now, high electron mobility transistor (HEMT) technology has played a chief role in microwave and millimeter-wave circuits [1], [2]. The advantages of HEMT transistors, such as large transconductance, great power density, low noise figure, and high breakdown voltage, as well as a semi-insulating GaAs substrate are favorable for circuits operating at high frequencies. Today, the HEMT technology retains the world record for the cut-off frequency and maximum operation frequency (about 500-GHz ft and about 400-GHz fmax) [3]. Obviously, HEMT-based low-noise amplifiers (LNAs) and power amplifiers (PAs) are superior to silicon-based circuits at microwave and millimeter-wave regimes in terms of gain, noise figure and power performances [4]-[6]. Much effort has been expended to integrate silicon-based front-end circuits with CMOS analog and logic circuits. However, HEMT-based LNAs and PAs are not yet replaceable for better performance especially at much higher frequencies. Connections between individual LNAs, PAs, and mixers using different technologies in a module suffer from large loss. It is preferable to implement the front-end circuits with the same process and on the same chip to reduce chip connections at high frequencies. Here, the HEMT technology is the best choice at high-frequency regimes [7]. Figure 1-1 shows the profile of a GaAs-based HEMT structure [8]. The process includes the metal-insulating-metal (MIM) capacitors (Cplate=0.39 fF/μm2), thin-film resistors (50 Ω/□), mesa resistors (150 Ω/□ for pHEMT and 180 Ω/□ for mHEMT), backside processing, via-hole etching, air-bridge and two metal layers.

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Introduction

2

Fig. 1-1 Profile of a GaAs-based HEMT structure.

A metamorphic HEMT (mHEMT) on a GaAs substrate has a lower noise figure, a higher transconductance and a higher cutoff frequency (fT) as compared with a pseudomorphic HEMT (pHEMT). Fully integrated 60 GHz single-chip front-end MMICs show that the mHEMT, contrasted with the pHEMT, has higher gain, higher output power and lower power consumption [7]. The advantage of the technology appears obviously in the amplifiers, which is a conclusive outcome. In the past, different kinds of passive mixers, such as diode mixers and FET resistive mixers, were discussed using the HEMT technology [9]-[11]. However, the diode passive mixers, using the pHEMT and mHEMT technologies, show comparable performances because the potential barriers associated with pHEMT and mHEMT diodes are almost equivalent. Identical resistive mixers using the 0.15 μm mHEMT and pHEMT technologies nearly have the same conversion loss, even though the mHEMT technology has a higher ft of 110 GHz, while the 0.15 m pHEMT technology employed has an 85 GHz fT [10]. TABLE 1.1 shows the comparison between pHEMT and mHEMT technologies.

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1.2 Current State of development for Millimeter-Wave Front-End in GaAs

3

TABLE 1-1 Typical data of pHEMT and mHEMT technologies [Herbert, MTT 2006].

Parameter pHEMT mHEMT Unit

Gate length 0.15 0.15 μm In mole fraction 15~30 40 % t f 88 110 GHz max f 183 200 GHz Gmpeak 495 730 mS/mm

Vbreakdown(gate-drain) 10 12 volt

IDSmax(Vgs=0.5V) 650 530 mA/mm

The diode and passive mixers have good linearity but a larger conversion loss [12]-[14], whereas the traditional microwave passive components based on quarter-wavelength design concepts are not compact and consume the real estate in the IC technology [15], [16]. Therefore, analog circuit design, where a high fT is important, concepts are adopted in this dissertation rather than implementing impedance matching design approaches. The double balanced Gilbert mixer is a popular topology for designing an active mixer due to the benefits of high conversion gain, compact size, and good isolation. Many Gilbert complex mixers have been realized using CMOS and SiGe HBT technologies, mostly at low frequencies. Lately, advancements in silicon device scaling have made Gilbert mixers possible even at millimeter-wave frequencies [10], [17].

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In the wireless communications, the combination package provides voice, video, and data service. This type of service requires the high data-rate and board bandwidth. The millimeter-wave regime can be used to satisfy these requirements. In recent years, researchers have paid significant attention to the 60 GHz front-end monolithic

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Introduction

4

microwave integrated circuits (MMICs) in the millimeter-wave regime. 57 GHz ~ 64 GHz bands in the U.S. and 57 GHz ~ 66 GHz bands in Europe are the best solutions due to unlicensed bands and oxygen resonance. Figure 1-2 shows that oxygen absorption in the air reaches its maximum value of 10~15 dB/km in the 60 GHz band. The advantages of the millimeter-wave band include greater high-speed bandwidth, higher resolution radar, smaller antenna, less crowded bandwidth, less jamming and less interference. Furthermore, the chip in the band is light, small, and highly integrated. On the other hand, it also comes with certain disadvantages – expensive parts, higher air loss, lower power device, and difficulty in design and manufacture.

Fig. 1-2 Millimeter-wave atmosphere absorption.

Previous research has developed GaAs-based single-chip front-end circuits in the millimeter-wave regime [18], [1], [7]. Figure 1-3, 1-4 and 1-5 illustrate these circuits. Figure 1-3 depicts the coplanar monolithic microwave integrated circuits for 77 GHz millimeter-wave sensor applications designed by Siemens Semiconductor Group. Part (a) and (b) of this figure depict the block diagram and photograph of this highly integrated transceiver, respectively. Siemens Semiconductor developed this 0.12 μm pHEMT technology in-house.

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1.2 Current State of development for Millimeter-Wave Front-End in GaAs

5

(a)

(b)

Fig. 1-3 (a) Block diagram and (b) chip photograph of the 77-GHz transceiver MMIC (2.0mm × 3.0mm) [Siemens, MTT 1998].

Herbert recently proposed a V-band single-chip transmitter and receiver using 0.15 μm pHEMT and mHEMT technologies. Figure 1-4 (a) and (b) shows the block diagrams of the V-band transmitter (Tx) and receiver (Rx), respectively. Figure 1-5 (a) and (b) shows the Tx and Rx photographs of the fabricated chip using pHEMT technology. Figure 1-6 (a) and (b) corresponds with Fig. 1-4 (a) and (b), respectively, for mHEMT technology. The performances of HEMT V-band transmitters and receivers usually perform than those of CMOS. These results prove the feasibility of a GaAs single MMIC chip in the millimeter-wave front-end circuits. Furthermore, a package technique is necessary in the manufacture IC products, especially in

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Introduction

6

microwave and millimeter-wave regimes.

(a) Tx (b) Rx

Fig. 1-4 Circuit block diagrams of (a) Tx and (b) Rx chips at 60 GHz [Herbert, JSSC 2005, 2007].

(a) pHEMT transmitter chip

(b) pHEMT receiver chip

Fig. 1-5 (a)The pHEMT transmitter chip measures 5.0 mm × 3.5 mm and (b) the pHEMT receiver chip is 5.7 mm × 5.0 mm [Herbert, JSSC 2005].

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1.3 Package in Microwave and Millimeter-Wave Regimes  Flip-Chip Technology

7

(a) mHEMT Tx photo (b) mHEMT Rx photo

Fig. 1-6 Sizes of (a) the mHEMT transmitter chip and (b) the mHEMT receiver chip are 4.0 mm × 3.0 mm and 5.5 mm× 3.0 mm, respectively [Herbert, JSSC 2007].

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Generally, bonding is needed for interconnection of integrated circuit packages. Especially at higher frequencies, conventional wire bonding has larger parasitic effects and poor reliability. Thus, the resulting circuit performances degrade. The flip-chip bonding technology [19]-[22] in development plays a more and more important role in the monolithic microwave integrated circuit (MMIC) packages. The flip-chip bonding offers great benefits of negligible parasitic effects and higher reliability thanks to shorter interconnected lines and superior mechanical stability [19]-[21]. Up to present, a microstrip (MS) line is still a classic type utilized in MMICs because of less time consumption in electro-magnetic (EM) simulations and flexible layout in designs. However, the MS is not compatible to the flip-chip technology [7]. Figure 1-7 shows the profile of a MMIC chip mounted on a carrier using flip-chip bonding. For the flip-chip bonding, coplanar waveguide (CPW) or finite-ground coplanar waveguide (FG-CPW) structures are more suitable than an MS because they can offer the smooth transition interface in nature.

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Introduction

8

Fig. 1-7 Flip-chip bonding profile of MMIC chip on a carrier.

In a fully integrated MMIC transceiver, the CPW’s size is intolerable in the low frequency application while the MS is suitable for the MMIC integration and can be designed with compact size, flexibilities on routing and wafer dicing easily [7]. The process with backside ground can support the MS and CPW designs at the same time. The CPWG type has wide uniplanar ground planes that, along with a back conductor, excite the parallel-plate mode easily [23]-[26]. The parallel-plate mode inducing parasitic resonance can be suppressed by the finite ground or via holes connecting front side ground with backside ground for an electric short. Besides, by adequately using via holes, the CPW mode can transfer easily to the MS mode [27]. Under these considerations, the FG-CPWG type is adopted in Chapter 4. The FG-CPWG in possession of narrow ground planes can eliminate surface wave and leakage effect [24]-[26]. However, the extremely small ground width causes large loss and higher impedance. So, the best design for flip-chip bonding is to optimize ground planes of the FG-CPWG and to overcome drawbacks of the CPW. The FG-CPWG type is hence becoming more and more popular in compact integrated circuits.

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1.4 Organizations

9

1.4 O

RGANIZATIONS

Chapter 2 analyzes the accuracy of RC-CR polyphase filters based on GaAs and CMOS technologies and designs pHEMT Gilbert mixers with polyphase filters, which are fundamental, leveled-LO and stacked-LO subharmonic Gilbert mixers. Chapter 3 compares the performances between the pHEMT and mHEMT Q-band subharmonic Gilbert up-conversion mixers. The V-band CPW-MS-CPW two-stage amplifier with flip-chip technology is demonstrated in Chapter 4. Chapter 5 designs and measures the V-band fully integrated mHEMT MMIC receiver. In Chapter 6, the Ka-band divide-by-2 Miller divider with quadrature outputs using pHEMT technology is depicted.

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Chapter 2 Ka/Ku-Band PHEMT Gilbert Mixers

With Polyphase and Coupled-Line

Quadrature Generators

2.1 I

NTRODUCTION

Recently, increased attention has been paid to complex mixers in modern wireless systems. Complex mixers with both in-phase and quadrature-phase mixing are employed to image rejection mixers and single-sideband (SSB) up-converters. The RC-CR polyphase filters [28]-[32] are used to generate the differential quadrature signals needed by complex mixers and subharmonic mixers. However, the RC-CR polyphase filters in CMOS and SiGe HBT technologies were realized below 2 GHz because it is difficult to fabricate accurate, small resistors and capacitors at high frequencies due to the Si substrate parasitic effect [30]. Even with electronic tuning, the complex Gilbert mixers based on the silicon technology can function at up to 6 GHz and the uncalibrated sideband rejection of the SSB Gilbert mixer at 6 GHz is 48.2 dB [31], [32]. On the contrary, the GaAs-based technology has accurate thin film resistors, metal-insulator-metal (MIM) capacitors and no parasitic substrate effect. Thus, the resistors and capacitors required for the polyphase filter can be implemented in a precise way. The high accuracy in GaAs-based thin film resistors comes from the in-situ film thickness monitor during processing. A 5 GHz complex mixer with accurate RC-CR polyphase filters has been realized in GaInP/GaAs HBT technology, but the performance is limited by the GaInP/GaAs HBT device due to its low ft [33]. At high operating frequencies, a quadrature coupler is another good choice for complex mixers. Nevertheless, the silicon-based coupler has a poor quality factor and bad magnitude balance at high frequencies. The 5.9 GHz CMOS I/Q subharmonic

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Ka/Ku-Band PHEMT Gilbert Mixers With Polyphase and Coupled-Line Quadrature Generators

12

mixer with a quadrature coupler and transformers at the RF path reveals a large magnitude mismatch in the output waveforms [34].

The subharmonic Gilbert mixer also plays an important role because the LO frequency of a subharmonic mixer is only half of the fundamental mixer’s LO frequency. This can solve the problem associated with generating LO signals at high frequencies. However, at high LO frequencies, the transistor time delay destroys the frequency doubling mechanism in the LO stage, so that the LO speed and the RF-to-IF isolation degrade [35]. Thus, a time-delay compensator is proposed at the stacked-LO stage to improve the performances of the subharmonic Gilbert mixer in this Chapter. This time-delay compensated subharmonic Gilbert mixer is reformed based on the previous work [35] to reduce the amount of transistors and to balance the current density of the transistors at the current commutating stages.

The low breakdown voltage in the advanced silicon technology makes the analog circuit design approach difficult. Thus, GaAs-based pHEMT technology with a high cut-off frequency, high breakdown voltage and semi-insulating substrate becomes the technological choice for high-frequency complex Gilbert mixers and subharmonic Gilbert mixers. So far, very few papers on Gilbert mixers incorporating HEMT technology have been published [36]-[39]. The 0.15-μm pHEMT technology employed has an 85-GHz ft and 10-V breakdown voltage. The high-performance active devices and precise passive components are utilized to realize several typical pHEMT Gilbert up- and down-converters, which are fundamental, leveled-LO and stacked-LO subharmonic Gilbert mixers. In Section 2 part 1, Monte Carlo simulations are employed to verify that the polyphase filter on the GaAs substrate has better accuracy than that on the silicon substrate. In Section 2 part 2, the S-matrices of the two types of differential quadrature coupled-line generators are analyzed for our Gilbert mixer at an

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2.2 Component Design of Millimeter- Wave Gilbert Mixer With Quadrature Features

13

RF port. In Section 2 part 3, the novel time-delay compensator, which cancels the phase error, is explained. From the experimental results, polyphase filters and 90˚/180˚ passive couplers used at the LO and RF stages are suitable for applications in the microwave and millimeter-wave regimes. A 15-GHz Ku-band pHEMT SSB complex Gilbert up-converter of 63-dB sideband rejection is realized in Section 3 part 1. A 34-GHz quadrature RF subharmonic down-converter with I/Q outputs is successfully demonstrated in Section 3 part 2 and a 40-GHz stacked-LO subharmonic mixer with a novel compensation technique is represented in Section 3 part 3.

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2.2.1 Polyphase Filter Design Using Monte Carlo Simulation for GaAs and CMOS Technologies

There are two common methods to design a quadrature generator—one is a polyphase filter and the other is a coupler. A polyphase filter is composed of sequential resistor-capacitor (R-C) and C-R components. The one-stage RC-CR polyphase filter is only designed at a center frequency and usually many stages are cascaded to tolerate mismatch errors. A two-section polyphase filter is shown in Fig. 2-1. This topology can generate balanced quadrature signals with equal amplitude at 0°, 90°, 180°, and 270° when R and C values are designed at the desired frequency ω=1/(RC). The two-stage polyphase filter has lower sensitivity to process variations than a one-stage. Thus, the two-stage polyphase filter is adopted in our mixer design to achieve optimum trade-offs in terms of magnitude balance, phase error, loss, and layout size.

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Fig. 2-1 Two-section RC-CR polyphase filter structure.

In the GaAs pHEMT technology, the Tantalum Nitride (TaN) thin film resistors and metal-insulator-metal (MIM) capacitors possess a sheet resistance of 50 Ω/sq ± 2 % and a unit capacitance of 0.4 fF/μm2 ± 10 % [7], respectively. On the other hand, the

Fig. 2-2 Magnitude and phase errors of the two-section polyphase filter by Monte Carlo simulations with resistance and capacitance variations.

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15

poly resistors and MIM capacitors in the TSMC 1P6M 0.18-μm CMOS technology have 7.58 Ω/sq ± 25 % and 1 fF/μm2 ± 15 %, respectively. Compared with the silicon-based technology, the semi-insulating GaAs-based HEMT process has better accuracy for passive components. The in-situ film thickness monitor in the thin-film resistor fabrication enhances resistance accuracy. According to Monte Carlo simulations with process variations, the maximum phase mismatch of 7° and magnitude error of -28 dB in a two-section GaAs-based polyphase filter for the worst case are shown at the desired frequency, f0, in Fig. 2-2. Figure 2-3 describes the rejection ratio of the two-stage polyphase filters between the silicon-based and GaAs-based technologies using Monte Carlo simulations with resistance and capacitance variations. The formula for the sideband and image rejection ratios is expressed as

2 2

(1+ ) + 2(1+ )cos +1) Rejection ratio (dB) = 10 log

(1 ) 2(1 ) cos 1          _ _ _ _   _{ (1)}

with the function of amplitude (χ %) and phase (θ degree) errors [7]. The mean rejection ratio of the GaAs-based polyphase filter reaches 34 dB, but there is only a 24-dB rejection ratio for the silicon-based counterpart. A 60-dB rejection ratio can be achieved in the ideal case.

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Fig. 2-3 Rejection ratio of Si- and GaAs-based polyphase filters by Monte Carlo simulations.

2.2.2 Performance Analysis of Differential Quadrature Coupled-Line Generator

The passive RC-CR polyphase filter is more suitable for applications below 30 GHz while a quadrature coupler consumes formidably large sizes at lower frequencies. However, as the operating frequency becomes higher and higher, the polyphase filters are not easily realized due to process limitations, interconnection delays and high driven power requirements, so that a quadrature coupler becomes a preferable alternative. At 30 GHz, a quarter-wavelength coupled line is about 1000 μm. The layout size of a coupler can be further reduced by the spiral shape, and thus a coupler can be easily implemented in the integrated circuits above 30 GHz.

There are two methods to generate differential quadrature signals based on microwave components. One is a quadrature coupler followed by two Marchand baluns and the other is a Marchand balun before two quadrature couplers, as illustrated in Fig. 2-4(a) and (b), respectively. All quadrature couplers are terminated with a 50-Ω resistor at the isolation port. Since the Marchand balun is composed of two

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back-to-back quadrature couplers, the first topology has five couplers while the second counterpart has four couplers. As derived in Appendix A, the scattering parameter matrix for each differential quadrature generator is

 



2 2



11 12 12 12 12 12 22 23 12 23 22 12 22 23 12 23 22

0

B Q Q Q B Q B Q B Q B Q B B B a _Q _B _B _B Q B B B Q B B B

S

T

C

T S

C S

T S

S

_{T S}

_S

C S

S

C S

S



_

_

















_

_

_







_











(2.2) and

 

11 12 12 12 12 2 2 12 22 23 22 23 2 2 12 23 22 23 22 2 2 12 22 23 22 23 2 2 12 23 22 23 22 B Q B Q B Q B Q B Q B Q B Q B Q Q B Q Q B Q B Q B Q B Q Q B Q Q B b Q B Q Q B Q Q B Q B Q B Q B Q Q B Q Q B Q B Q B

S

T S

C S

T S

T C S

T S

T C S

S

C S

T C S

C S

T C S

C S

































_







,(2.3) (a) (b)

Fig. 2-4 Differential quadrature generator consists of (a) one coupler with two baluns or (b) one balun with two couplers.

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18

with the coupling coefficient (C Q) and through coefficient (TQ) of the coupler and the S parameters (S11B, S12B, S22B and S23B) of the Marchand balun as defined in the Appendix. Obviously, these two combinations produce the same differential quadrature outputs. The input return loss of the first type is improved by the factor of (TQ2+CQ2) in comparison with the second counterpart because the reflected power caused by the impedance mismatch between the coupler and balun can be absorbed totally at the isolation port of the coupler. This design approach is commonly used in balanced amplifiers. In the first structure, the two Marchand baluns do not interfere with each other since S24(42), S25(52), S34(43) and S35(53) are equal to zero.

In this Chapter, the structure of the coupler followed by two Marchand baluns is employed at the RF input stage and connected with common-gate-configured transistors with 50-Ω input impedance. The ac grounded terminals in the Marchand balun can be used as the dc grounds for the common-gate-configured transistors [37]. Thus, this structure does not need to add an auxiliary ac choke and an auxiliary dc blocking capacitor to separate the ac signal and dc bias of the mixers. The layout size can also be reduced by the first topology because of no extra biasing components

2.2.3 Stacked-LO Subharmonic Gilbert Cell With Time-Delay Compensation

A transistor has a finite time delay between the output drain current and input gate voltage. The I-V transfer function of a transistor can be expressed by the gate-source voltage, the drain-source voltage, and the time delay . When the gate-source port of a transistor is fed by a step voltage function, the output drain shows up after the phenomenological time delay , which is generally one-third of the transistor transit-time delay. Thus, the adiabatic approximation for I-V characteristics is used when the operating frequency is much slower than the inversion of the time delay

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19

( 1 

 ) [28]. However, the time delay problem can not be ignored when a mixer

operates at higher frequency.

 

RF LO

4i sin 2ω t - θ -4i sin 2ω t - θ_RF  _LO 

LO sin ω t LO sin ω t LO -sin ω t RF i -i_RF   RF LO 2i sin ω t - θ _ _ RF LO -2i sin ω t - θ LO cos ω t cos ω tLO LO -cos ω t LO sin ω t LO -sin ω t RF i   RF LO 2i cos ω t - θ _ _ RF LO -2i cos ω t - θ LO cos ω t cos ω tLO LO -cos ω t LO sin ω t RF -i Conventional stacked-LO stage Compensator

A C B D

 

 

 

RF LO

2i sin 2ω t - θ + sin θ -2iRF_sin 2ω t - θ + sin θ LO  _ 2iRFsin 2ω t - θ - sin θ LO   -2iRFsin 2ω t - θ - sin θ LO  

Fig. 2-5 Time-delay (θ) compensation analysis for the compensated stacked-LO subharmonic mixer.

Fig. 2-6 Time-delay-compensated LO multipliers [35].

A conventional stacked-LO subharmonic Gilbert mixer is shown in Fig. 2-5. The stacked-LO stage provides a frequency doubling mechanism when differential quadrature LO signals are applied. Thus, the mixer outputs are 2sin(2ωLOt)iRF and -2sin(2ωLOt)iRF at nodes A and C, respectively. However, the finite transistor delay, θ = ωτ, which is pronounced at high frequencies, introduces the extra dc term, sin(θ) at nodes A and C. This dc offset problem makes the LO speed of a conventional stacked-LO subharmonic Gilbert mixer slow and degrades the RF-to-IF isolation. A novel time-delay compensated subharmonic Gilbert mixer is proposed and analyzed in

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Fig. 2-5. The time-delay compensator is employed at the stacked-LO stage to improve the LO speed and isolation of the subharmonic Gilbert mixer. The upper/lower LO stages of the conventional stacked-LO stage and compensator are fed with (I+,I-)/(Q+,Q-) and (Q+,Q-)/(I+,I-) signals, respectively. The nodes A and C of the conventional stacked-LO stage connect with the nodes B and D of the compensator, respectively, and as a consequence the component (±2iRFsin(θ)) is cancelled. Only the ±4sin(2ωLOt-θ)iRF signal is available at the outputs. Further, for the purpose of enhancing the LO speed, the upper and lower LO stages can use the smallest transistors with a width of 2×15 μm, which is limited by air-bridge fabrication, to obtain the same high current density.

The time-delay compensated LO multiplier shown in Fig. 2-5 is an improved version of the first proposed one as shown in Fig. 2-6 [35]. It is evident that both time-delay-compensated mixers have the identical mathematical functions. The mixer intrinsic response depends on the transistor cut-off frequency, which is determined by the current density. On the other hand, the mixer extrinsic response caused by the device capacitance is limited by the device size. The current density and device size are optimized for the improved version because the switching pairs of the lower- and upper-LO are identical as shown in Fig. 2-5. Thus, the improved version has the advantages of higher speed, smaller size and less power consumption.

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2.3 Millimeter-Wave Up- and Down-Converter Designs and Measured Results

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Fig. 2-7 Simple block diagram of a Ka-band system.

Figure 2-7 shows the block diagram and frequency planning of a Ka-band system. The circuits in the shaded area are implemented in this Chapter. The polyphase filters needed for both transmitting and receiving are designed around 15 GHz thanks to the semi-insulating GaAs substrate. The received signal is amplified by an LNA and then sequentially down-converted to 200 MHz by the 34-GHz I/Q subharmonic mixer. The LO frequency works at only half an RF frequency for the subharmonic mixer to reduce the effects of DC offset and self-mixing. Dual conversion is employed in the transmitter chain. A quadrature IF input is first up-converted to 15 GHz by the 15-GHz SSB up-converter and subsequently up-converted to 30-GHz by a double balanced fundamental up-converter. The simple 30-GHz double balanced up-converter has equal

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LO and IF frequencies. Thus, the undesired sideband signal is around dc and can be eliminated by the front-end circuits and antenna [40]. The proposed frequency planning has its merit because all the mixers in Fig. 2-7 share the same voltage control oscillator (VCO) of 15 - 17 GHz to reduce the complexity. In addition, the VCO operated at low frequency consumes less power than the one operated at high frequency.

As mentioned above in Section 2, the polyphase filter, quadrature coupler, and compensation technique have their own advantages in the up- and down-conversion mixers. In this section, all the implemented mixers adopt the two-section polyphase filter at the LO stages. The predictions of the RF output return loss of the up-converter and the input RF return loss of the down-converter by simulations are accurate because precise passive components can be built on the semi-insulting GaAs substrate. A pHEMT device reaches the maximum transconductance when the fully transfer of electrons from the low mobility donor layer to the high mobility channel layer occurs. The gate terminal controls the two-dimensional electron gas (2-DEG) channel at the hetero-junction interface when a more negative gate voltage is applied. The abrupt charge transfer renders the pHEMT device characteristics sensitive to the process variation and thus makes the circuit prediction from the given active device model inaccurate. Passive components and all of the high-frequency routings are simulated by an EM simulator. The distance between high-frequency routings is kept at least 25 μm to avoid line-to-line coupling effects. The symmetry in the circuit is well preserved in layouts by keeping the symmetrical paths equal length to suppress the phase mismatch. The sideband rejection in the SSB up-converter and I/Q IF waveforms in the I/Q down-converter are the best vehicles to verify the overall quadrature accuracy. 63-dB single sideband rejection is achieved for the 15-GHz SSB up-converter. The

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leveled-LO subharmonic I/Q down-converter at 34 GHz has < 0.4-dB magnitude and < 1° phase errors in the output waveform. The advantage of combination of analog and microwave circuit design methodology in HEMT technology is evident. The fabricated pHEMT mixers for high-frequency applications are measured by on-wafer testing.

2.3.1 15-GHz Up-Conversion Mixer With 63-dB Sideband Rejection

Figure 2-8 shows the functional block diagram of a double-quadrature single-sideband (SSB) up-converter. The SSB output expression, i.e. cos(ωLOt+ωIFt), is derived and explained straightforwardly in Fig. 2-8. Quadrature IF signals and quadrature LO signals are needed in the SSB up-converter. The SSB up-converter in Fig. 2-9 includes an LO polyphase filter, two fundamental analog multipliers, IF active baluns, and a current combiner with the matching network for the RF output. The two analog multipliers are two double balanced Gilbert mixers, which are composed of Gilbert cells (M5~M8 and M9~M12), IF input stages (M13~M16) and current sources (M17 and M18). The source resistors are used for self-biasing the current sources because only the depletion mode pHEMT devices are available. The self-biasing technique had been utilized in amplifiers [41]. The differential quadrature signals needed by the Gilbert cells are generated by applying the differential signals to the two-stage polyphase filter.

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Fig. 2-8 Block diagram of an SSB up-converter.

Fig. 2-9 Circuit topology of a 15-GHz SSB up-conversion mixer using depletion mode AlGaAs/InGaAs pHEMT technology.

The input quadrature IF signals are transformed to the differential quadrature signals via the IF active baluns. These active baluns are employed to generate two IF

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signals with balanced magnitude and opposite phase. The IF active balun is intentionally designed with low gain in order to not limit the gain compression point. In addition, when compared with the passive baluns, the active baluns can save much valuable real estate in the IC technology at low IF frequencies.

Two inductors, L1 and L2, and a capacitor, C, form an LC passive current combiner designed at  1/(2L C1,2 ). The purpose of the LC current combiner is to transform the

differential output of the Gilbert mixer into the single-ended output while doubling the current gain [42]. In general, the performance of a passive LC current combiner at higher frequencies is superior to an active current mirror load because an active current mirror has a limited output voltage swing and cannot respond rapidly at higher frequencies. Furthermore, a passive LC current combiner possesses higher linearity. The microstrip line inductor has a good quality factor because the GaAs-based technology owns the backside ground plane and semi-insulating substrate. On the other hand, the high quality microstrip line inductor cannot be realized in the Si-based technology due to the lack of the backside ground plane and the lossy silicon substrate.

Figure 2-10 displays the micrograph of the fabricated chip in Fig. 2-9. The layout is kept as symmetric as possible and the IFI and IFQ inputs are located on opposite sides for the sake of symmetrical considerations. A ground-signal-ground (GSG) IFI input is on the right-hand side, a GSGSG LO pad is on the top, and an IFQ input and RF output GSGSG pad is on the left-hand side. The chip size is 1.4 × 0.9 mm2 including pads. The supply voltage and current for the mixer cores are 4.8 V and 18 mA, respectively.

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Fig. 2-10 Micrograph of a 15-GHz pHEMT SSB Gilbert up-converter.

Fig. 2-11 SSB suppression performance of the pHEMT SSB Gilbert up-converter. 63-dB sideband rejection is achieved.

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Fig. 2-12 Measured and simulated RF output return loss and measured conversion gain of the pHEMT SSB Gilbert up-converter.

When IF1 = 0.18 GHz and LO = 15 GHz, the conversion gain keeps a constant of 5 dB for LO input power from 10 dBm to 20 dBm. The sideband rejection ratio of the SSB up-converter is shown in Fig. 2-11. The sideband rejection ratio is defined as the power ratio between the wanted and unwanted signals. We have achieved a 63-dB sideband rejection ratio in this study.

The simulation and measurement of the RF output return loss are shown in Fig. 2-12. The output return loss is determined by the LC current combiner and the output matching network because the impedance looking into the output of the commutating Gilbert mixer cell is high. The simulated curve of the RF output return loss is close to the measured curve. The RF output return loss is better than 10 dB from 12.8 GHz to 17 GHz and 20 dB between 15.4 GHz and 15.8 GHz. The measured conversion gain versus RF frequencies is also illustrated in Fig. 2-12. The experimental RF 3-dB bandwidth is about 1 GHz in the RF frequency range of 14.4 GHz to 15.4 GHz and is limited by the LC current combiner and the associated output matching network. Meanwhile, the LO-to-RF isolation is better than 31 dB for 14.7~15.2-GHz LO

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frequencies and the IF-to-RF isolation is above 50 dB for 0.1~0.4-GHz IF frequencies. The output power performances of an SSB up-converter are displayed in Fig. 2-13. The measured OP1dB equals -6 dBm and OIP3 equals 8 dBm while IF1=0.18 GHz and IF2=0.28 GHz. The measured data reveal that the SSB up-converter has good linearity because the band-pass LC current combiner is utilized instead of an active low-pass current mirror.

Fig. 2-13 Power performance of the pHEMT SSB Gilbert up-converter when IF1=0.18 GHz and

IF2=0.28 GHz.

2.3.2 34-GHz Double-Quadrature I/Q Subharmonic Down-Conversion Mixer

The micrograph of a 34-GHz double-quadrature I/Q subharmonic down-converter is shown in Fig. 2-14. The mixer utilizes an area of 2.35 × 1.85 mm2. This proposed circuit of the leveled-LO I/Q subharmonic down-conversion mixer is employed with the quadrature LO and RF inputs. The quadrature LO signals and differential quadrature RF signals are generated by a two-section polyphase filter and one coupler followed by two Marchand baluns, respectively. The mixer core consists of a leveled-LO subharmonic Gilbert mixer to perform frequency translation, as shown in Fig. 2-15 [28]. The mixer core has 12 mA and the supply voltage is 8V.

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Fig. 2-14 Micrograph of the 34-GHz pHEMT double-quadrature subharmonic Gilbert mixer.

Fig. 2-15 Schematic of the 34-GHz I/Q subharmonic down-conversion mixer.

Figure 2-16 displays the 200-MHz IFI andIFQ output waveforms when RF and LO input frequencies are 34.2 GHz and 17 GHz, respectively. The measured performances

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have smaller than 1° phase error and 0.4-dB amplitude error limited by the measurement accuracy of ±0.5° phase and ±0.1-dB amplitude errors. Figure 2-17 shows the phase and magnitude errors as a function of frequencies and the I/Q phase error and the output mismatch from 32.5 GHz to 34 GHz are less than 1˚ and 0.5 dB, respectively. The excellent I/Q performance reveals that the LO R-C polyphase filter as well as the RF coupler and baluns can be implemented precisely on the semi-insulating GaAs substrate and operates well at high frequencies. The two-stage polyphase filter at the LO port has a wider balanced magnitude-and-phase bandwidth than the coupled-line components at the RF port. The differential quadrature signal for feeding the RF port of the mixer is produced by the composite network, which consists of one quadrature coupler and two Marchand baluns. Because the Marchand balun has a wider balanced bandwidth than that of the coupler, the I/Q output difference in conversion gain is mainly affected by the quadrature coupler. The peak conversion gain reaches 4.5 dB for 14~15 dBm LO input power.

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Fig. 2-17 Measured phase error and output difference of the 34-GHz I/Q subharmonic down-converter.

The RF input return loss is simulated and measured in Fig. 2-18 and the RF input return loss is better than 10 dB from 20 GHz to 39.2 GHz. The input matching network of the subharmonic I/Q down-converter shown in Fig. 2-15 consists of a differential quadrature coupled-line coupler and source-port input impedance of the common-gate configuration. The common-gate input impedance is simply a reciprocal of the transconductance for the frequency up to the transistor cut-off frequency, 85-GHz in the employed pHEMT transistor. Thus, the simulated and measured data of the input return loss in the down-converter is very consistent. From 200 MHz to 300 MHz, the measured noise figure (N.F.) is about 24.5 dB, as shown in Fig. 2-18. The 3-dB IF bandwidth is 500 MHz.

Figure 2-19 depicts that the input 1-dB compression point, IP1dB, of the RF signal is -8 dBm while the input third-order intercept point, IIP3, is 3-dBm. All port-to-port isolations regarding LO leakage are more than 50 dB for 15-GHz to 18-GHz LO frequencies. Meanwhile, LO-to-RF and 2LO-to-RF [43] isolations exceed 60 dB. The

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outstanding isolations of the I/Q subharmonic down-converter prevent the self-mixing problem.

Fig. 2-18 Measured and simulated RF input return loss and measured noise figure of the 34-GHz pHEMT leveled-LO subharmonic Gilbert down-converter.

Fig. 2-19 Power performance of the I/Q subharmonic Gilbert down-converter when RF1=34.1 GHz

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2.3.3 40-GHz pHEMT Stacked-LO Subharmonic Gilbert Down-Conversion Mixer With Time-Delay Compensation

In order to cancel the dc offset resulting from the transistor delay, the highly symmetrical stacked-LO subharmonic Gilbert mixer is designed with a time-delay compensation technique. This structure not only improves the LO speed but also largely reduces the amount of transistors required as compared with previous work [35].

Fig. 2-20 Schematic of the 40-GHz pHEMT stacked-LO subharmonic Gilbert down-conversion mixer with a time-delay compensation technique.

As shown in Fig. 2-20, the 20-GHz R-C polyphase filter is employed at the LO stage when the RF input stage is a common-gate-configured amplifier with a Marchand balun. Here, the common-gate-configured transistors provide an input impedance of 50-Ω for the Marchand balun and hence facilitate the input matching. The fabricated

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chip is shown in Fig. 2-21. The chip size is 2.4 mm × 1.9 mm. The microstrip lines connecting a polyphase filter with stacked-LO Gilbert cells are a critical issue, and these microstrip lines are meandered so as to remain equal in length for the phase error reduction of the differential quadrature LO signals. The current consumption of the mixer core is 11 mA at the supply voltage of 8V.

Fig. 2-21 Micrograph of the 40-GHz pHEMT compensated stacked-LO subharmonic Gilbert down-conversion mixer.

The maximum conversion gain of 3.1 dB is obtained from a single-ended IF output at the LO power of 10 dBm, as shown in Fig. 2-22. At the same time, the 3-dB RF bandwidth is about 4 GHz from 37 GHz to 41 GHz. The measured N.F. of the 40-GHz stacked-LO subharmonic down-converter with the time-delay compensation is also shown in Fig. 2-22. The N.F. almost keeps a constant of 18 dB. The 3-dB IF bandwidth is 550 MHz. The LO-to-IF, 2LO-to-IF, LO-to-RF, and 2LO-to-RF [43] isolations are better than 30 dB, 45 dB, 40 dB and 50 dB, respectively. Further, the RF-to-IF

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isolation is better than 30 dB. The 1-dB gain compression occurs when the input RF power equals -4.5 dBm and the IIP3 of 10 dBm is achieved, as shown in Fig. 2-23.

Fig. 2-22 Measured conversion gain and noise figure of the 40-GHz pHEMT stacked-LO subharmonic down-converter.

Fig. 2-23 Power performance of the 40-GHz compensated stacked-LO Gilbert down-converter when RF1=40.101 GHz and RF2=40.201 GHz.

應用類比電路設計及覆晶封裝技術於毫米波高速電子遷移率電晶體之收發機

國 立 交 通 大 學

電信工程學系

博 士 論 文

應用類比電路設計及覆晶封裝技術

於毫米波高速電子遷移率電晶體之

收發機

Millimeter-Wave HEMT Transceiver

With Analog Circuit Design Approach

and Flip-Chip Technology

研 究 生：蘇珍儀

指導教授：孟慶宗

應用類比電路設計及覆晶封裝技術於毫米

波高速電子遷移率電晶體之收發機

Millimeter-Wave HEMT Transceiver With

Analog Circuit Design Approach and

Flip-Chip Technology

研究生：蘇珍儀

Student:

Jen-Yi

Su

指導教授：孟慶宗 博士 Advisor:

Dr.

Chinchun

Meng

國立交通大學

電信工程學系

博士論文

A Dissertation

Submitted to Institute of Communication Engineering

College of Electrical and Computer Engineering

National Chiao Tung University

in Partial Fulfillment of the Requirements

for the Degree of Doctor of Philosophy

in

Communication Engineering

Hsinchu, Taiwan

應用類比電路設計及覆晶封裝技術於毫米波高

速電子遷移率電晶體之收發機

學生:蘇珍儀 指導教授:孟慶宗博士

Abstract (Chinese)

國立交通大學

電信工程學系博士班

摘

要

Millimeter-Wave HEMT Transceiver With

Analog Circuit Design Approach and Flip-Chip

Technology

Student: Jen-Yi Su Advisor: Chinchun Meng

Department of Communication Engineering

National Chiao Tung University

Abstract (English)

Acknowledgements

最重要的是要感謝父親蘇寬及母親蔣秀卿小姐，及兄姐等親人給

予我一路上的扶持與鼓勵，讓我更有信心繼續支持下去直到完成博士

學位。

很感謝我的指導老師孟慶宗教授，孟教授不論在學業或研究上都

惠我良多，使我一次比一次進步，孟教授給予我機會磨練自己，眾多

的訓練及教誨使我能有今天的成就與學術上的貢獻。

謝謝材料系張翼教授的科專計畫，讓我們生活上不至於困乏，且

提供設備及下線機會。另外也謝謝國家晶片系統設計中心提供晶片實

作機會，還有國家奈米元件實驗室高頻技術中心黃國威博士提供我們

完善且舒適的量測環境，及優秀量測團隊：佳松學長、書毓、汶德、

國祥和小鄧等人提供專業協助。

博士班的成員：宗翰、聖哲、宏儒、及金詳，謝謝你們陪我走過

這些日子，當我遇到困難時候，你們總是能提供我專業的意見，這段

漫長艱辛的路只有你們知道。曾經參與科專的主要優秀成員，從慶

鴻、智凱、家宏、約停、揚鮮、大維及泰麟學弟，這

6 年的計畫如果

沒有你們的努力與配合，也不會今天豐碩的成果。雖然這一路上走來

很辛苦，但是我相信這在人生的道路上可以增強自己的心智。還有實

驗室的金釵學妹們，宜蓁、雅惠、宜珊、欣怡及嘉苓，謝謝你們陪我

分享不能說的心事。最貼心及帶給我歡笑的學弟柏誼、冠璋、勝文、

宇文、樺輿、熙良及忠佑，生活多了你們才能忘記痛苦且帶來歡樂。

曾經為了資格考所組的讀書會成員：順子、憲宏及繼禾，很感恩你們

一路上對我不論是生活上或是課業上的關心及照顧。另外很感謝助理

小薔，你總是在我有麻煩時候都助我一臂之力，分享心事。謝謝我身

邊曾經出現過的人，不管是訓練我的或是關心我的，因為有了你們，

才有今天成長茁壯的我，謝謝大家。

蘇珍儀

國立交通大學

博士論文

研究生：蘇珍儀

指導教授：孟慶宗博士 Advisor:

學生:蘇珍儀指導教授:孟慶宗博士