Influence of an anomalous dimension effect on thermal instability in
amorphous-InGaZnO thin-film transistors
Kuan-Hsien Liu, Ting-Chang Chang, Wu-Ching Chou, Hua-Mao Chen, Ming-Yen Tsai, Ming-Siou Wu, Yi-Syuan Hung, Pei-Hua Hung, Tien-Yu Hsieh, Ya-Hsiang Tai, Ann-Kuo Chu, and Bo-Liang Yeh
Citation: Journal of Applied Physics 116, 154508 (2014); doi: 10.1063/1.4897236
View online: http://dx.doi.org/10.1063/1.4897236
View Table of Contents: http://scitation.aip.org/content/aip/journal/jap/116/15?ver=pdfcov Published by the AIP Publishing
Articles you may be interested in
Increase of mobility in dual gate amorphous-InGaZnO4 thin-film transistors by pseudo-doping Appl. Phys. Lett. 103, 043509 (2013); 10.1063/1.4816587
Effect of hydrogen incorporation on the negative bias illumination stress instability in amorphous In-Ga-Zn-O thin-film-transistors
J. Appl. Phys. 113, 063712 (2013); 10.1063/1.4792229
High current stress effects in amorphous-InGaZnO4 thin-film transistors Appl. Phys. Lett. 102, 023503 (2013); 10.1063/1.4775694
Suppress temperature instability of InGaZnO thin film transistors by N2O plasma treatment, including thermal-induced hole trapping phenomenon under gate bias stress
Appl. Phys. Lett. 100, 182103 (2012); 10.1063/1.4709417
The effect of moisture on the photon-enhanced negative bias thermal instability in Ga–In–Zn–O thin film transistors
Kuan-Hsien Liu,1Ting-Chang Chang,2,3,a)Wu-Ching Chou,1,a)Hua-Mao Chen,4 Ming-Yen Tsai,5Ming-Siou Wu,6Yi-Syuan Hung,6Pei-Hua Hung,5Tien-Yu Hsieh,2 Ya-Hsiang Tai,4Ann-Kuo Chu,5and Bo-Liang Yeh7
1
Department of Electrophysics, National Chiao Tung University, Hsin-chu 300, Taiwan
2
Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan
3
Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan
4
Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsin-chu 300, Taiwan
5
Department of Photonics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan
6
Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu 300, Taiwan
7
Advanced Display Technology Research Center, AU Optronics, No.1, Li-Hsin Rd. 2, Hsinchu Science Park, Hsin-Chu 30078, Taiwan
(Received 1 August 2014; accepted 20 September 2014; published online 21 October 2014) This paper investigates abnormal dimension-dependent thermal instability in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors. Device dimension should theoretically have no effects on threshold voltage, except for in short channel devices. Unlike short channel drain-induced source barrier lowering effect, threshold voltage increases with increasing drain voltage. Furthermore, for devices with either a relatively large channel width or a short channel length, the output drain current decreases instead of saturating with an increase in drain voltage. Moreover, the wider the channel and the shorter the channel length, the larger the threshold volt-age and output on-state current degradation that is observed. Because of the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer, the self-heating effect will be pronounced in wider/shorter channel length devices and those with a larger operating drain bias. To further clarify the physical mechanism, fast ID-VGand modulated peak/base pulse time ID-VD measurements are utilized to demonstrate the self-heating induced anomalous dimension-dependent threshold voltage variation and on-state current degradation.
VC 2014 AIP Publishing LLC. [http://dx.doi.org/10.1063/1.4897236]
I. INTRODUCTION
Recently, portable electronic products have been widely applied for consumer uses, especially those using low power consumption IC,1–3 non-volatile memory,4–34 and thin film transistors (TFTs).35–39 Recently, transparent oxide-based semiconductors, such as ZnO and amorphous indium-gal-lium-zinc-oxide (a-IGZO), have attracted much attention due to their considerable potential applications in flat, flexible, and transparent displays.40,41 In particular, a-IGZO TFTs possess advantageous properties such as high mobility, excellent uniformity, good transparency to visible light, and low process temperature, making them a promising candi-date to be adopted in the next generation of the display industry.41–43Therefore, they are very promising alternatives to replace amorphous silicon TFTs for application in active matrix liquid crystal displays (AMLCD) and organic light-emitting diode displays (AMOLED) as switching/driving devices. However, there are some difficulties which are nec-essary to overcome for oxide TFTs to be practical in these applications, such as instability under gate bias stress, light illumination, or the surrounding ambiance.44–47Moreover, a-IGZO TFTs can also be used for gate driver on array (GOA)
technology. Conventionally, driving ICs have been fabricated through CMOS technology and mechanically attached to the sides of the panel. However, GOA technology fabricates gate driver ICs on the array itself instead of attaching them to the panel sides. As a result, GOA technology can reduce process steps and cost as well as achieve thinner panels with narrower edges to realize slim border displays.48,49However, mobility of driving ICs fabricated by single crystal silicon is about one hun-dred times that of a-IGZO. As a result, in order to achieve the same driving current, it is necessary to increase channel width and/or decrease channel length of a-IGZO TFTs for GOA oper-ation. However, the degree to which channel length can be decreased is restricted by photolithography. As a result, increas-ing channel width is a better way to increase drivincreas-ing current. Therefore, investigating the performance and reliability of a-IGZO TFTs with large channel width is of great importance.
II. EXPERIMENT
Back-channel-etching structured n-type a-IGZO TFTs were fabricated on a glass substrate in this work. The double-layer Cu/Mo (500/20 nm) gate electrode films were deposited and then patterned via photolithography on a glass substrate. Then 300-nm-thick Si3N4 and 70-nm-thick SiO2 gate dielectric films were sequentially deposited on the pat-terned gate electrode by plasma enhanced chemical vapor a)Authors to whom correspondence should be addressed. Electronic
addresses: [email protected] and [email protected]
deposition (PECVD). An active layer of 30-nm-thick a-IGZO film was deposited by DC magnetron sputtering using a target of In2O3:Ga2O3:ZnO¼ 1:1:1 in atomic ratio at room temperature, and then patterned. The Mo/Cu (20/500 nm) source/drain electrodes were formed by DC-sputtering and then patterned. Finally, 160-nm-thick SiO2and 50-nm-thick Si3N4were sequentially deposited as a passivation layer by PECVD. After that the device was annealed in an oven at 300C for 2 h in a dark environment. In this paper, the con-ventional and fast I-V measurements were performed by Agilent B1500A and Agilent B1530A semiconductor ana-lyzers, respectively. The device dimensions of channel width/length (W/L) were 100, 200, 500, 1000, 5000, and 10 000 lm/5.5, 6, 10, 15, and 20 lm. The threshold voltage is defined as the gate voltage when the normalized drain cur-rent (NID¼ ID L/W) reaches 1 nA, where L and W are channel length and width, respectively. All measurements were performed in a dark environment.
III. RESULT AND DISCUSSION
Figures 1(a)and1(b) show the ID-VG curve at VD¼ 1, 5, 10, and 20 V, with W/L¼ 10 000/5.5 lm for Figure 1(a) and W/L¼ 100/5.5 lm for Figure1(b). Obviously, threshold voltage increases with increasing drain voltage. Furthermore, the larger the channel width, the larger threshold voltage that can be observed. Conventionally, channel width and drain voltage do not affect threshold voltage in long channel devi-ces. However, an anomalous threshold voltage variation is observed in Figures1(a)and1(b).
In order to better understand the dimension and drain voltage-dependent threshold voltage variation, Figures2(a) and2(b)characterizes threshold voltage versus various chan-nel lengths at low (VD¼ 1 V) and high (VD¼ 20 V) drain
voltages for the W¼ 100 and 10 000 lm devices. Clearly, at low measurement drain voltage (VD¼ 1 V), both W ¼ 100 and 10 000 lm devices with various channel lengths have nearly the same threshold voltage. On the other hand, at a high measurement drain voltage (VD¼ 20 V), threshold volt-age is also independent of channel length for the device with relatively small channel width (W¼ 100 lm) but exhibits dimension-dependent threshold voltage variation for the de-vice with relatively large channel width (W¼ 10 000 lm). In previous literatures, threshold voltage shift results from elec-trons trapping at the IGZO/SiO2 interface or in SiO2 bulk under positive gate bias stress (PGBS),50–53 or high current stress.54,55However, in our research, we found that threshold voltage increases at a shorter channel length for devices with large channel width and operated at high drain voltage (Figures1and2) without imposing stress biases, unlike that found in previous literature.
To further inspect this anomalous phenomenon and explain more precisely, Figure 3(a) illustrates the threshold voltage shift versus various channel widths and drain vol-tages at a fixed channel length (L¼ 5.5 lm). Similarly, Figure 3(b)shows the threshold voltage shift versus various channel length and drain voltages, but at a fixed channel width (W¼ 10 000 lm). Threshold voltage shift is defined as Vth(measurement)-Vth(at VD¼ 1 V). Note that at low drain voltage (VD¼ 5 V), threshold voltage shift is negligible and unapparent, with the same being true for relatively small channel widths (W¼ 100 lm) and/or relatively long channel lengths (L¼ 20 lm) at all drain voltages, as shown in Figures3(a)and3(b). When W⭌ 500 lm, L ⬉ 10 lm, and VD ⭌ 10 V, a significant threshold voltage shift can be observed with increased channel width and increased drain voltage, or with decreased channel length and increased drain voltage. Accordingly, it is reasonable to speculate that
FIG. 1. ID-VGtransfer characteristic of
a-IGZO TFT operated at VD¼ 1, 5, 10,
and 20 V for: (a) W/L¼ 10 000/5.5 lm and (b) W/L¼ 100/5.5 lm.
FIG. 2. Threshold voltage dependent on channel length, with W¼ 100 and 10 000 lm at (a) VD¼ 1 V (b)
VD¼ 20 V.
the abnormal dimension-dependent threshold voltage varia-tion may in fact be induced by the self-heating effect.56It is well known that the self-heating effect arises in silicon-on-insulator (SOI) MOSFETs and low-temperature-polycrystal-line silicon (LTPS) TFTs because the surrounding oxide or other thermal insulating materials make it difficult to dissi-pate the heat generated in the active layer when high current flows through the channel, a situation quite similar to that found in the IGZO channel layer.57In addition, the thermal conductivity of IGZO is much lower than Si and is compara-ble to SiO2. Therefore, heat dissipation in IGZO TFTs is rel-atively more difficult than in Si-based TFTs.58,59 Because the larger drain voltage will form a higher drain current, resulting in higher power (P¼ IV), the heat in channel will be higher, resulting in a more severe self-heating effect. Furthermore, because the temperature is highest at the center of the channel region and the heat dissipate to the surround-ing materials along the channel width direction, larger chan-nel widths make heat dissipation in the chanchan-nel more difficult, again resulting in a more pronounced self-heating effect.57,60 Moreover, the shorter the channel length, the higher drain current flowing through the channel, resulting in more heat generated in the channel. As a result, either a larger channel width or a shorter channel length combined
with a higher operated drain bias will induce a more severe self-heating effect, resulting in more pronounce threshold voltage shift. The inset of Figure3(b)shows the energy band diagram. When the large channel width and/or short channel length TFT is operated at high drain voltage, significant self-heating effect will occur, and channel electrons will be trapped at the IGZO/SiO2interface or in SiO2bulk through the thermionic-field emission process, resulting in a larger observed threshold voltage.54–56 In addition, from Figure 1(a), note that threshold voltage shifts with a small variation of the slope in the transfer characteristics. This indicates that some shallow sub-conduction band trap states are created at the IGZO active layer/gate dielectric interface during the self-heating-induced trapping process, resulting in a small amount mobility and subthreshold swing degradation. However, this small amount of subthreshold swing and mo-bility degradation cannot explain the very large threshold voltage variation. The dominant mechanism of threshold voltage variation may in fact results from the self-heating induced-charge trapping phenomenon.
To confirm the proposed self-heating effect-induced anomalous dimension and drain voltage-dependent threshold voltage variation, fast ID-VG measurement is performed. Figure 4(c) illustrates the waveform of the conventional
FIG. 3. Dependence of threshold volt-age shift on drain voltvolt-age and (a) chan-nel width and (b) chanchan-nel length. The inset of (b) illustrates the thermionic-field emission process of electron trapping.
FIG. 4. The transfer characteristic of a-IGZO TFT with W/L¼ 10 000/5.5 lm before and after measuring at high drain voltage (VD¼ 10 V) by (a)
con-ventional ID-VGmeasurement, and (b)
fast ID-VGmeasurement. The inset in
(b) illustrates the fast ID-VGcurve. (c)
and (d) show the waveform of conven-tional and fast ID-VG measurement,
ID-VG measurement, in which drain voltage is fixed with gate voltage performed stepwise. Note that the time scale of each gate voltage step is on the order of tens of milliseconds (ms). For comparison, Figure4(d) shows the waveform of fast ID-VGmeasurement, in which drain voltage is fixed with gate voltage performed in a pulse. Significantly, the time scale of peak/base time is rather short, approximately on the order of microseconds (ls). Note that the inset of Figure4(b) shows the fast ID-VGcurve, which exhibits good switching characteristics, indicating that the gate capacitance can become effectively charged during the fast ID-VG measure-ment. From previous research,54 sufficient heating time is necessary for Joule heating to take place within the channel, resulting in a pronounced self-heating effect-induced charge trapping phenomenon. This sufficient heating time is approx-imately on the order of tens of ms. Because the gate pulse peak/base time in fast ID-VGmeasurement is on the order of ls, the short heating time is insufficient for Joule heating to occur. Therefore, use of the fast ID-VG measurement will exclude the self-heating effect induced-charge trapping phe-nomenon, and therefore threshold voltage shift can also be excluded. The measurement sequences of Figures4(a) and 4(b) are as follows. First, the ID-VG curve is measured by conventional ID-VG measurement at low drain voltage (VD¼ 1 V) to avoid the self-heating effect and act as the ini-tial state. Second, the ID-VGcurve is measured at high drain voltage (VD¼ 10 V) by conventional ID-VGmeasurement for Figure4(a), or by fast ID-VG measurement for Figure 4(b). Finally, the ID-VGcurve is measured by conventional ID-VG measurement at low drain voltage (VD¼ 1 V) to serve as the final state. Clearly, there is a positive threshold voltage shift between initial and final states after conventional ID-VG measurements at high drain voltage (VD¼ 10 V), as shown in Figure4(a). During the conventional ID-VGmeasurement (VD¼ 10 V), there was sufficient heating time for Joule heat-ing to occur, leadheat-ing to the self-heatheat-ing effect-induced charge trapping phenomenon and resulting in the threshold voltage shift between initial and final states. Conversely, dur-ing the fast ID-VGmeasurement (VD¼ 10 V), the insufficient heating time required for Joule heating results in no thresh-old voltage shift being observed, as shown in Figure 4(b). The fast ID-VG measurement further corroborates that the abnormal dimension and drain voltage- dependent threshold voltage variation does in fact result from the self-heating effect-induced charge trapping phenomenon.
Figures5(a)and5(b)show the ID-VDoutput characteris-tic at a fixed channel length (5.5 lm) and different channel widths (10 000 lm and 100 lm, respectively). Compared to the W¼ 100 lm device, the W ¼ 10 000 lm one exhibits an anomalous output characteristic. When the measurement drain voltage exceeds approximately 15 V, drain current decreases instead of saturating with an increase in drain voltage.
To provide insight into this anomalous on-state current degradation phenomenon, we define on-state current degra-dation percentage (DID %) as [ID,max(measurement)-ID(at VD¼ 30 V)]/ID,max(measurement). Figure 6 shows the de-pendence of on-state current degradation (%) on channel width and length. Clearly, on-state current degradation (%) increases with increasing channel width and/or decreasing channel length. From previous discussions, it is reasonable to speculate that this abnormal on-state current degradation may be induced by the self-heating effect. The heat dissipa-tion in channel will be rather difficult for the larger channel width devices, and the current flowing through the channel will be larger with the shorter channel length devices, result-ing in more heat accumulation in the channel. As a result, a severe self-heating effect-induced charge trapping phenom-enon will occur, resulting in a considerable threshold voltage shift. Because of this large threshold voltage shift, the abnor-mal drain current decreases as drain voltage increases when VD⭌ 15 V, as shown in Figure5(a).
FIG. 5. ID-VDoutput characteristic of
a-IGZO TFT operated at VG¼ 10, 15,
and 20 V for (a) W/L¼ 10 000/5.5 lm and (b) W/L¼ 100/5.5 lm.
FIG. 6. Dependence of on-state current degradation on channel width and length.
In order to confirm the on-state current degradation results from this self-heating effect-induced charge trapping phenomenon, a measurement sequence was designed as Figures7(a)and7(b). First, the ID-VGcurve is measured at low drain voltage (VD¼ 1 V) to avoid the self-heating effect and act as the initial state. Second, the ID-VDcurve is meas-ured. Finally, the ID-VGcurve is measured at low drain volt-age (VD¼ 1 V) to serve as the final state. Clearly, there is a positive threshold voltage shift between initial and final states after ID-VDmeasurements for the large channel width (W¼ 10 000 lm) device, as shown in Figure7(a). During the ID-VD measurement, the high drain voltage region (VD⭌ 15 V) will generate high drain current, resulting in more heat accumulating in the channel, leading to the self-heating effect-induced charge trapping phenomenon and resulting in the threshold voltage shift between initial and final states. On the contrary, because heat dissipation is relatively easy for the small channel width (W¼ 100 lm) device, there is a much smaller threshold voltage shift between initial and final states for the W¼ 100 lm device.
To further corroborate the proposed mechanism, the pulse ID-VD measurement (various peak/base times) was adopted, as shown in Figure 8. Figure 8(a) shows the
dependence of on-state current degradation on peak time at a fixed base time (10 ms), while (b) shows this dependence on base time at fixed peak time (50 ms). The insets of Figures 8(a) and 8(b) illustrate the waveform of the drain pulse. Figure8(c)shows the conventional ID-VDmeasurement and pulse ID-VDmeasurements. In conventional ID-VD measure-ment, gate voltage is fixed with drain voltage performed stepwise. Note that the time scale of each drain voltage step is on the order of tens of milliseconds (ms). For comparison, in pulse ID-VDmeasurement, gate voltage is fixed with drain voltage performed in a pulse form, and we can modulate var-ious peak/base times to extract the on-state current degrada-tion at various drain pulses. Previous research54 has indicated that sufficient heating time is necessary for Joule heating to take place within the channel, resulting in a pro-nounced self-heating effect-induced charge trapping phe-nomenon. As a result, if on-state current degradation does indeed result from self-heating effect-induced charge trap-ping phenomenon, the deterioration degree should decrease as the heating time, i.e., the peak time, decreases. As shown in Figure8(a), when the peak time is 50 ms, the degradation approaches that of conventional ID-VDmeasurement, and the degradation decreases when the peak time decreases. When
FIG. 7. ID-VGtransfer characteristic of
a-IGZO TFT before and after ID-VD
measurement for (a) W/L¼ 10 000/ 5.5 lm and (b) W/L¼ 100/5.5 lm.
FIG. 8. Dependence of on-state current degradation on (a) peak time (fixed base time¼ 10 ms) and (b) base time (fixed peak time¼ 50 ms). The insets of (a) and (b) show the waveforms of drain pulse at various peak times (fixed base time) and various base times (fixed peak time), respectively. (c) Schematic diagrams of conventional and pulse ID-VDmeasurement.
the peak time is smaller than 10 ms, no on-state current deg-radation is observed. Furthermore, from previous literature, cooling time is also an important factor influencing the Joule heating to occur within the channel.55As a result, if on-state current degradation does indeed result from the self-heating effect-induced charge trapping phenomenon, the deteriora-tion degree should decrease as the cooling time, i.e., the base time, increases. As shown in Figure8(b), when the base time is 10 ms, the deterioration approaches that of conventional ID-VD measurement, and decreases when the base time increases. When the base time is larger than 500 ms, an insig-nificant amount of on-state current degradation is observed. This comparison of conventional and pulse (various peak/ base time) ID-VDmeasurements further corroborates that the abnormal dimension-dependent on-state current degradation does in fact result from the self-heating effect-induced charge trapping phenomenon. Note that the effective cooling time is much longer than the effective heating time, at least by a factor of twenty. This is because the thermal conductiv-ity of IGZO is much lower than Si and is comparable to SiO2. Therefore, heat dissipation in IGZO TFTs is relatively more difficult than in Si-based TFTs.
IV. CONCLUSION
The anomalous dimension effect on thermal instability in a-IGZO TFTs has been investigated. Devices with larger channel widths and/or shorter channel lengths and which are operated at higher drain voltages will produce larger thresh-old voltages and more severe on-state current degradation, with the effect becoming even more pronounced as channel width or drain voltage increases and/or channel length decreases. This is due to the surrounding oxide and other thermal insulating material and the low thermal conductivity of the IGZO layer. The more pronounced self-heating effect is a product of both the more difficult heat dissipation in wider channels as well as the higher drain current in devices operated at higher drain voltages and shorter channel length. Because sufficient heating time (approximately on the order of tens of ms) is necessary for Joule heating to take place within the channel, the fast ID-VG and modulated various peak/base pulse time ID-VDmeasurements are performed to confirm the proposed mechanism. Because the time scale of the peak/base time in the fast ID-VGmeasurement is shorter, on the order of ls, the heating time is insufficient for Joule heating, resulting in no observed threshold voltage shift. The fast ID-VG measurement confirms that the abnormal dimension-dependent threshold voltage variation is due to the self-heating effect induced-charge trapping phenomenon. Furthermore, the pulse ID-VD measurement again demon-strates that the abnormal dimension-dependent threshold voltage variation and on-state current degradation indeed results from the self-heating effect induced-charge trapping phenomenon. Further, the effective cooling time is much longer than the heating time, indicating that IGZO is a low thermal conductivity material compared to Si, and is compa-rable to SiO2. From this research, device dimension is a sig-nificant factor that governs the thermal instability of a-IGZO TFTs for the use of GOA technology. How to lessen or even
eliminate the self-heating effect induced charge trapping phenomenon is of great importance for GOA technology.
ACKNOWLEDGMENTS
This work was performed at the National Science Council Core Facilities Laboratory for Nano-Science and Nano-Technology in the Kaohsiung-Pingtung area and was supported by the National Science Council of the Republic of China under Contract Nos. NSC 102-2120-M-110-001.
1
K. P. Rodbell, D. F. Heidel, H. H. K. Tang, M. S. Gordon, P. Oldiges, and C. E. Murray,Trans. Nucl. Sci.54, 2474–2479 (2007).
2C. H. Dai, T. C. Chang, A. K. Chu, Y. J. Kuo, S. C. Chen, C. C. Tsai, S. H.
Ho, W. H. Lo, G. Xia, O. Cheng, and C. T. Huang,IEEE Electron Device Lett.31, 540 (2010).
3
W. H. Lo, T. C. Chang, C. H. Dai, W. L. Chung, C. E. Chen, S. H. Ho, O. Cheng, and C. T. Huang,IEEE Electron Device Lett.33, 303 (2012).
4K. C. Chang, T. M. Tsai, T. C. Chang, K. H. Chen, R. Zhang, Z. Y. Wang,
J. H. Chen, T. F. Young, M. C. Chen, T. J. Chu, S. Y. Huang, Y. E. Syu, D. H. Bao, and S. M. Sze,IEEE Electron Device Lett.35(5), 530 (2014).
5R. Zhang, K. C. Chang, T. C. Chang, T. M. Tsai, S. Y. Huang, W. J. Chen,
K. H. Chen, J. C. Lou, J. H. Chen, T. F. Young, M. C. Chen, H. L. Chen, S. P. Liang, Y. E. Syu, and S. M. Sze,IEEE Electron Device Lett.35(6), 630 (2014).
6W. Guan, S. Long, R. Jia, and M. Liu, Appl. Phys. Lett. 91, 062111
(2007).
7
C. C. Shih, K. C. Chang, T. C. Chang, T. M. Tsai, R. Zhang, J. H. Chen, K. H. Chen, T. F. Young, H. L. Chen, J. C. Lou, T. J. Chu, S. Y. Huang, D. H. Bao, and S. M. Sze,IEEE Electron Device Lett.35(5), 633 (2014).
8T. J. Chu, T. M. Tsai, T. C. Chang, K. C. Chang, R. Zhang, K. H. Chen, J.
H. Chen, T. F. Young, J. W. Huang, J. C. Lou, M. C. Chen, S. Y. Huang, H. L. Chen, Y. E. Syu, D. H. Bao, and S. M. Sze,IEEE Electron Device Lett.35(2), 217 (2014).
9K. C. Chang, J. H. Chen, T. M. Tsai, T. C. Chang, S. Y. Huang, R. Zhang,
K. H. Chen, Y. E. Syu, G. W. Chang, T. J. Chu, G. R. Liu, Y. T. Su, M. C. Chen, J. H. Pan, K. H. Liao, Y. H. Tai, T. F. Young, S. M. Sze, C. F. Ai, M. C. Wang, and J. W. Huang,J. Supercrit. Fluids85, 183 (2014).
10K. C. Chang, J. W. Huang, T. C. Chang, T. M. Tsai, K. H. Chen, T.
F. Young, J. H. Chen, R. Zhang, J. C. Lou, S. Y. Huang, Y. C. Pan, H. C. Huang, Y. E. Syu, D. S. Gan, D. H. Bao, and S. M. Sze,
Nanoscale Res. Lett.8, 523 (2013).
11R. Zhang, T. M. Tsai, T. C. Chang, K. C. Chang, K. H. Chen, J. C. Lou, T.
F. Young, J. H. Chen, S. Y. Huang, M. C. Chen, C. C. Shih, H. L. Chen, J. H. Pan, C. W. Tung, Y. E. Syu, and S. M. Sze,J. Appl. Phys.114, 234501 (2013).
12Q. Liu, W. Guan, S. Long, R. Jia, M. Liu, and J. Chen,Appl. Phys. Lett.
92, 012117 (2008).
13
Y. T. Su, K. C. Chang, T. C. Chang, T. M. Tsai, R. Zhang, J. C. Lou, J. H. Chen, T. F. Young, K. H. Chen, B. H. Tseng, C. C. Shih, Y. L. Yang, M. C. Chen, T. J. Chu, C. H. Pan, Y. E. Syu, and S. M. Sze,Appl. Phys. Lett.
103, 163502 (2013).
14
K. C. Chang, T. M. Tsai, R. Zhang, T. C. Chang, K. H. Chen, J. H. Chen, T. F. Young, J. C. Lou, T. J. Chu, C. C. Shih, J. H. Pan, Y. T. Su, Y. E. Syu, C. W. Tung, M. C. Chen, J. J. Wu, Y. Hu, and S. M. Sze,Appl. Phys. Lett.103, 083509 (2013).
15
T. M. Tsai, K. C. Chang, R. Zhang, T. C. Chang, J. C. Lou, J. H. Chen, T. F. Young, B. H. Tseng, C. C. Shih, Y. C. Pan, M. C. Chen, J. H. Pan, Y. E. Syu, and S. M. Sze,Appl. Phys. Lett.102, 253509 (2013).
16
K. C. Chang, R. Zhang, T. C. Chang, T. M. Tsai, J. C. Lou, J. H. Chen, T. F. Young, M. C. Chen, Y. L. Yang, Y. C. Pan, G. W. Chang, T. J. Chu, C. C. Shih, J. Y. Chen, C. H. Pan, Y. T. Su, Y. E. Syu, Y. H. Tai, and S. M. Sze,IEEE Electron Device Lett.34(5), 677 (2013).
17
K. C. Chang, C. H. Pan, T. C. Chang, T. M. Tsai, R. Zhang, J. C. Lou, T. F. Young, J. H. Chen, C. C. Shih, T. J. Chu, J. Y. Chen, Y. T. Su, J. P. Jiang, K. H. Chen, H. C. Huang, Y. E. Syu, D. S. Gan, and S. M. Sze,
IEEE Electron Device Lett.34(5), 617 (2013).
18
K. C. Chang, T. M. Tsai, T. C. Chang, H. H. Wu, K. H. Chen, J. H. Chen, T. F. Young, T. J. Chu, J. Y. Chen, C. H. Pan, Y. T. Su, Y. E. Syu, C. W. Tung, G. W. Chang, M. C. Chen, H. C. Huang, Y. H. Tai, D. S. Gan, J. J. Wu, Y. Hu, and S. M. Sze,IEEE Electron Device Lett.34(4), 511 (2013).
T. M. Tsai, K. C. Chang, T. C. Chang, G. W. Chang, Y. E. Syu, Y. T. Su, G. R. Liu, K. H. Liao, M. C. Chen, H. C. Huang, Y. H. Tai, D. S. Gan, and S. M. Sze,IEEE Electron Device Lett.33(12), 1693 (2012).
21
T. M. Tsai, K. C. Chang, T. C. Chang, Y. E. Syu, S. L. Chuang, G. W. Chang, G. R. Liu, M. C. Chen, H. C. Huang, S. K. Liu, Y. H. Tai, D. S. Gan, Y. L. Yang, T. F. Young, B. H. Tseng, K. H. Chen, M. J. Tsai, C. Ye, H. Wang, and S. M. Sze,IEEE Electron Device Lett.33(12), 1696 (2012).
22
T. M. Tsai, K. C. Chang, T. C. Chang, Y. E. Syu, K. H. Liao, B. H. Tseng, and S. M. Sze,Appl. Phys. Lett.101, 112906 (2012).
23K. C. Chang, T. M. Tsai, T. C. Chang, Y. E. Syu, K. H. Liao, S. L.
Chuang, C. H. Li, D. S. Gan, and S. M. Sze,Electrochem. Solid-State Lett.
15(3), H65 (2012).
24M. F. Hung, Y. C. Wu, and Z. Y. Tang, Appl. Phys. Lett.98, 162108
(2011).
25
K. C. Chang, T. M. Tsai, T. C. Chang, Y. E. Syu, C.-C. Wang, S. K. Liu, S. L. Chuang, C. H. Li, D. S. Gan, and S. M. Sze,Appl. Phys. Lett.99(26), 263501 (2011).
26K. C. Chang, T. M. Tsai, T. C. Chang, Y. E. Syu, H. C. Huang, Y. C.
Hung, T. F. Young, D. S. Gan, and N. J. Ho,Electrochem. Solid-State Lett.14(9), K47 (2011).
27Y. E. Syu, T. C. Chang, J. H. Lou, T. M. Tsai, K. C. Chang, M. J. Tsai, Y.
L. Wang, M. Liu, and S. M. Sze,Appl. Phys. Lett.102, 172903 (2013).
28
Y. E. Syu, T. C. Chang, T. M. Tsai, G. W. Chang, K. C. Chang, Y. H. Tai, M. J. Tsai, Y. L. Wang, and S. M. Sze,Appl. Phys. Lett.100(2), 022904 (2012).
29T. J. Chu, T. C. Chang, T. M. Tsai, H. H. Wu, J. H. Chen, K. C. Chang, T.
F. Young, K. H. Chen, Y. E. Syu, G. W. Chang, Y. F. Chang, M. C. Chen, J. H. Lou, J. H. Pan, J. Y. Chen, Y. H. Tai, C. Ye, H. Wang, and S. M. Sze,IEEE Electron Device Lett.34(4), 502 (2013).
30Y. E. Syu, R. Zhang, T. C. Chang, T. M. Tsai, K. C. Chang, J. C. Lou, T.
F. Young, J. H. Chen, M. C. Chen, Y. L. Yang, C. C. Shih, T. J. Chu, J. Y. Chen, C. H. Pan, Y. T. Su, H. C. Huang, D. S. Gan, and S. M. Sze,IEEE Electron Device Lett.34(7), 864 (2013).
31Y. R. Jhan, Y. C. Wu, H. Y. Lin, and M. F. Hung,Appl. Phys. Lett.103,
053118 (2013).
32
T. C. Chang, F. Y. Jian, S. C. Chen, and Y. T. Tsai,Mater. Today14(12), 608–615 (2011).
33Y. E. Syu, T. C. Chang, T. M. Tsai, Y. C. Hung, K. C. Chang, and M. J.
Tsai,IEEE Electron Device Lett.32(4), 545–547 (2011).
34
M. C. Chen, T. C. Chang, C. T. Tsai, S. Y. Huang, S. C. Chen, C. W. Hu, S. M. Sze, and M. J. Tsai,Appl. Phys. Lett.96, 262110 (2010).
35L. F. Teng, P. T. Liu, Y. J. Lo, and Y. J. Lee,Appl. Phys. Lett. 101,
132901 (2012).
36
C. S. Fuh, S. M. Sze, P. T. Liu, L. F. Teng, and Y. T. Chou,Thin Solid. Films520(5), 1489–1494 (2011).
37W. F. Chung, T. C. Chang, H. W. Li, C. W. Chen, Y. C. Chen, S. C. Chen,
T. Y. Tseng, and Y. H. Tai,Electrochem. Solid-State Lett.14(3), H114 (2011).
28(9), 809 (2007).
40C. T. Tsai, T. C. Chang, S. C. Chen, I. Lo, S. W. Tsao, M. C. Hung, J. J.
Chang, C. Y. Wu, and C. Y. Huang,Appl. Phys. Lett.96, 242105 (2010).
41
M. F. Hung, Y. C. Wu, J. J. Chang, and K. S. Chang-Liao,IEEE Electron Device Lett.34, 75 (2013).
42L. C. Chen, Y. C. Wu, T. C. Lin, J. Y. Huang, M. F. Hung, J. H. Chen, and
C. Y. Chang,IEEE Electron Device Lett.31(12), 1407–1409 (2010).
43
T. C. Chen, T. C. Chang, C. T. Tsai, T. Y. Hsieh, S. C. Chen, C. S. Lin, M. C. Hung, C. H. Tu, J. J. Chang, and P. L. Chen,Appl. Phys. Lett.97, 112104 (2010).
44
P. T. Liu, Y. T. Chou, and L. F. Teng, Appl. Phys. Lett.95, 233504 (2009).
45T. C. Chen, T. C. Chang, T. Y. Hsieh, W. S. Lu, F. Y. Jian, C. T. Tsai, S.
Y. Huang, and C. S. Lin,Appl. Phys. Lett.99, 022104 (2011).
46
D. Kang, H. Lim, C. Kim, I. Song, J. Park, Y. Park, and J. Chung,Appl. Phys. Lett.90, 192101 (2007).
47J. S. Park, J. K. Jeong, H. J. Chung, Y. G. Mo, and H. D. Jim,Appl. Phys. Lett.92, 072104 (2008).
48
Y. S. Lee, H. W. Park, S. H. Moon, T. Kim, K. C. Lee, B. H. Berkeley, and S. S. Kim,SID37, 1083–1086 (2006).
49J. Jeon, K. S. Choo, W. K. Lee, J. H. Song, and H. G. Kim,SID35, 10–13
(2004).
50
A. Suresh, P. Wellenius, and J. F. Muth, Tech. Dig.–Int. Electron Devices Meet. 9829167, 587–590 (2007).
51A. Suresh and J. F. Muth,Appl. Phys. Lett.92, 033502 (2008). 52
J. M. Lee, I. T. Cho, J. H. Lee, and H. I. Kwon,Appl. Phys. Lett.93, 093504 (2008).
53
M. E. Lopes, H. L. Gomes, M. C. R. Medeiros, P. Barquinha, L. Pereira, E. Fortunato, R. Martins, and I. Ferreira,Appl. Phys. Lett.95, 063502 (2009).
54
T. Y. Hsieh, T. C. Chang, T. C. Chen, Y. T. Chen, M. Y. Tsai, A. K. Chu, Y. C. Chung, H. C. Ting, and C. Y. Chen,IEEE Trans. Electron Devices
59(12), 3389–3395 (2012).
55T. C. Chen, T. C. Chang, T. Y. Hsieh, M. Y. Tsai, Y. T. Chen, Y. C.
Chung, H. C. Ting, and C. Y. Chen, Appl. Phys. Lett. 101, 042101 (2012).
56T. Y. Hsieh, T. C. Chang, T. C. Chen, Y. T. Chen, M. Y. Tsai, A. K. Chu,
Y. C. Chung, H. C. Ting, and C. Y. Chen, IEEE Electron Device Lett.
34(1), 63–65 (2013).
57
M. Fujii, H. Yano, T. Hatayama, Y. Uraoka, T. Fuyuki, J. S. Jung, and J. Y. Kwon,Jpn. J. Appl. Phys.47(8), 6236–6240 (2008).
58
D. K. Seo, S. Shin, H. H. Cho, B. H. Kong, D. M. Whang, and H. K. Cho,
Acta Mater.59(17), 6743–6750 (2011).
59
S. C. Andrews, M. A. Fardy, M. C. Moore, S. Aloni, M. Zhang, V. Radmilovic, and P. Yang,Chem. Sci.2(4), 706–714 (2011).
60T. Fuyuki, K. Kitajima, H. Yano, T. Hatayama, Y. Uraoka, S. Hashimoto,
