奈米CMOS通道背向散射實驗及其潛在性應用之研究(III)

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行政院國家科學委員會補助專題研究計畫成果報告

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奈米 CMOS 通道背向散射實驗及其潛在性應用之研究(3/3)

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計畫類別：

■

個別型計畫 □整合型計畫

計畫編號：

NSC 96-2221-E-009-187-

執行期間：

96/08/01 ~ 97/07/31

計畫主持人：陳明哲

計畫參與人員：謝振宇

，

林大文

，

呂立方

，

宋東壕

，

周佳宏

，

陳彥

銘

執行單位：

國立交通大學電子工程學系及電子研究所

中 華 民 國 97 年 10 月 30 日

2

行政院國家科學委員會補助專題研究計畫成果報告

奈米 CMOS 通道背向散射實驗及其潛在性應用之研究(3/3)

Nano-CMOS Channel Backscattering Experiment and Its Potential Applications

執行期限: 96/08/01 ~ 97/07/31

計畫編號: NSC 96-2221-E-009-187-

主持人：陳明哲教授

國立交通大學電子工程學系及電子研究所

一、中文摘要

本計劃為期三年，進行通道背向散射實驗並找到

在奈米場效電晶體上的應用。第一年建立通道背向散

射實驗之核心： (1) 一維解薛丁格-浦以松方程式量子

力學模擬器以從電容電壓數據萃取製程參數， 藉由此

得到在開始的 K

B

T

層中的平均熱入射速度, 等效閘

電容和近似於平衡臨界電壓; (2) 次臨界 DIBL 量測

以有效計入二維效應的影響; (3) 利用比例與位移方

法估計源極/集極的串聯電阻和通道或閘極的長度; (4)

利用近似於平衡的遷移率量測， 去量化橫跨 K

B

T

層

的背向散射自由平均路徑; (5) 利用電流電壓擬似法

決定 K

B

T

層的寬度; 最後， (6) 利用機率和統計知

識、微觀傳輸物理、解浦以松方程式和蒙地卡羅模擬，

有系統的去處理與證明所萃取出來的 K

B

T

層寬度和

他們的物理意義及製程關鍵指引。 據此實驗核心， 我

們進行：(1) 通道背向散射實驗應用於 Bulk 奈米場效

電晶體測試晶片; (2) Bulk 奈米場效電晶體雜訊實驗

並與通道背向散射數據相關性探討; 以及(3) Bulk 奈

米場效電晶體介觀物理理解、特性分析（經由機率和

統計處理）、簡潔元件模型、元件製造關鍵和設計規範

之建立。

關鍵詞

：

奈米場效電晶體, 通道背向散射, 介觀物

理, 矽變形奈米場效電晶體, 雙倍式閘極奈米場效電

晶體, 鍺通道奈米場效電晶體, 雜訊。

英文摘要

This is a three-years project to perform channel backscattering experiment and find potential applications in nanoFETs. In the first year, the core of channel backscattering experiment to be established consists of the following key elements: (1) 1-D self-consistent Schrodinger-Poisson quantum simulator such as to assess process parameters from C-V data, which in turn can quantify average thermal injection velocity at the beginning of the KBT layer, effective gate capacitance, and

quasi-equilibrium threshold voltage; (2) subthreshold DIBL measurement to account for 2-D effect; (3) usage of

ratio-and-shift method to measure source/drain series resistances and gate or channel length; (4) long-channel quasi-equilibrium mobility measurement in order to quantify mean-free-path for backscattering over the KBT layer; (5) I-V fitting to determine the width of the KBT layer; and finally (6) applying knowledge of probability and statistics, microscopic transport physics, solving of Poisson equation, and Monte Carlo simulation, in a systematical way to deal with and clarify the extracted KBT layer width, as well as underlying physical meanings and key process guidelines. Based on this experimental set-up, we proceed with the following: (1) application of channel backscattering experiment to bulk nanoFET test devices; (2) noise measurement on bulk nanoFETs along with correlation with channel backscattering data; and (3) establishment of bulk nanoFETs mesoscopic physics and understanding, characteristics analysis (via probability and statistics), compact model, key for devices manufacturing, and design guidelines.

Key Words：NanoFETs, Channel Backscattering, Mesoscopic Physics, Strained-Silicon NanoFETs, Double-Gate NanoFETs, Germanium Channel NanoFETs.

二、緣由與目的

歐 盟 最 近 通 過 了 為 期 至 少 3 年 的

Nano-CMOS

泛歐大計劃 (自 2004 年 3 月開始).

此重大事件意味著兩件事: 一方面, Nano-CMOS

繼 續 為 國 際 間 重 點 研 究 題 目 ; 另 方 面 , 來 自

Nano-CMOS領域國際同儕的品質要求與日俱增, 在

此領域非得做出好的研究不可。在 Nano-CMOS 廣

泛領域中, 以 Channel Backscattering 為基礎的載子

傳輸理論, 國際上公認為描述下世代奈米元件物理

行為特性的嶄新語言, 理論創始人普渡大學 Mark

Lundstrom

及 Supriyo Datta 兩位教授並因而獲得

2002

年 IEDM Cledo Brunetti 獎。 數年前我们就已

進行 Channel Backscattering 理論及相關量測之研究

並有一篇 IEDM 2002 年論文發表, 日以繼夜研究到

現在, 以 2004 年 9 月產出一篇 IEEE TED 長文最有

代表性. IEEE TED 兩位國際評審也高度肯定此論文

3

之嚴謹及有用性。此論文詳細報告如何適當的進行

通 道 背 向 散 射 實 驗 （ channel backscattering

experiment）並找到在奈米場效電晶體上的應用。 過

去的經驗讓我們了解，透過關鍵地帶 (K

B

T Layer)

的研究，可得到有相當建設性的介觀 (mesoscopic)

物理理解、特性分析（經由機率和統計處理）,

Compact

元件模型建立, 和奈米場效電晶體元件的

製造關鍵等等。通道背向散射實驗均適用於傳統的

金氧半場效電晶體（Nano Bulk MOSFETs）、雙倍式

閘極場效電晶體（double-gate Nano-FETs）、矽變形

場效電晶體（strained-silicon Nano-FETs）和鍺通道

場效電晶體（germanium-channel Nano-FETs）等。

因 此 我 們 草 擬 以 Nano-CMOS channel

backscattering experiment

為主題的國科會 3 年計劃,

此實驗的核心為:

(i)

一維的 self-consistent Schrodinger-Poisson solver

從 C-V data 粹取製程參數, 藉由此製程參 數可以得

到在開始的 K

B

T layer

中的平均熱入射速度(average

thermal injection velocity),

等效閘電容(effective gate

capacitance)

和 近 似 於 平 衡 臨 界 電 壓

(quasi-equilibrium threshold voltage);

(ii)

Subthreshold DIBL(drain-induced barrier

lowering)量測以有效計入二維效應的影響;

(iii) 利用比例與位移方法(ratio-and-shift method)去

估計源極/集極(source/drain)的串聯電阻和通道或閘

極(gate)的長度;

(iv) 利 用 近 似 於 平 衡 (quasi-equilibrium) 的 遷 移 率

(mobility)量測, 去量化橫跨 layer 的背向散射

自由平均路徑(mean-free-path for backscattering) ;

(v)

利用 I-V fitting 的方法去 K

B

T layer

的寬度;

(vi)

然後利用機率和統計 Knowledge, 微觀傳輸物

理 , 解 浦 以 松 方 程 式 (Poisson equation along the

channel direction)

和 蒙 地 卡 羅 模 擬 (Monte Carlo

simulation),

有系統的去處理與證明所粹取出來的

K

B

T layer

寬度和他們的物理意義及製程關鍵指引。

三、研究方法與成果

已建立 channel backscattering 實驗核心:

1.

1-D self-consistent Schrodinger-Poisson solver

從

C-V data

粹取製程參數, 藉由此製程參數以得到在

開始的 K

B

T layer

中的平均熱入射速度, 等效閘電容

和近似於平衡臨界電壓;

2.

Subthreshold DIBL

量測以有效計入二維效應的

影響;

3.

利用比例與位移方法去估計源極/集極的串聯

電阻和通道或閘極的長度;

4.

利用近似於平衡的遷移率量測, 去量化橫跨

layer

的背向散射自由平均路徑; 利用 I-V fitting 的

方法去 K

B

T layer

的寬度;

5.

然後利用機率和統計 Knowledge, 微觀傳輸物

理, 解浦以松方程式和蒙地卡羅模擬, 有系統的去

處理與證明所萃取出來的 K

B

T layer

寬度和他們的

物理意義及製程關鍵指引。

四、 結論與討論 (i)

在 Nano-CMOS 通道背向散射(即波動導向

的下世代奈米元件物理)領域, 本人研究群這

幾年完成了大量的實驗工作,改進了原先的理

論模式,發表了一系列相關論文, 並被知名學

術界及世界級研發機構引用:

z Stanford-MIT team in a 2004 IEDM paper “Electro-thermal comparison and performance optimization of thin-body SOI and GOI MOSFETs”

z TSMC in a 2005 Symposium on VLSI Technology paper “The impact of uniaxial strain engineering on channel backscattering in nanoscale MOSFETs”

z STMicroelectronics/CNRS/LETI/NXP Semiconductor in 2005 December Issue of IEEE TED “A new backscattering model giving a description of the quasi-ballistic transport in nano-MOSFET”

z TSMC in 2006 IEEE EDL

z TSMC in 2006 VLSI-TSA

z CEA/LETI/L2MP (France) in 2007 Symposium on VLSI Technology: “Will strain be useful for 10nm quasi-ballistic FDSOI devices? An experimental study”

z (Univ. Udine, Italy) M. Zilli, P. Palestri, D. Esseni, and L. Selmi, “On the experimental determination of channel backscattering in nanoMOSFETs,” IEEE IEDM, p. 105, 2007.

z (Beijing Uni., China and Sumsung, Korea) Y. Tian, et al., “New self-aligned silicon nanowire transistors on bulk substrate fabricated by Epi-free compatible CMOS technology: process integration, experimental characterization of carrier transport and low frequency noise,” IEEE IEDM, p. 895, 2007.

z (Grenoble, France) M. Ferrier, et al., “Conventional technological boosters for injection velocity in ultrathin-body MOSFETs,” IEEE Nanotechnology, vol. 6, pp. 613-621, Nov. 2007.

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z (Bologna Univ. Italy) C. Fiegna, Y. Yang, E. Sangiorgi, et al., “Analysis of self-heating effects in ultrathin-body SOI MOSFETs by device simulation,” IEEE TED, vol. 55, pp. 233-244, Jan. 2008.

z (MIT) A. Khakifirooz and D. A. Antoniadis, “MOSFET performance scaling-Part I: Historical Trends,” IEEE TED, vol. 55, pp. 1391-1400, June 2008.

簡言之，目下傳統的半導體元件物理已不

能應付下世代奈米元件物理所需，以波動導向

觀點的物理圖像則趁勢而起。本人在此關鍵領

域的成功可由

Prof. Gerhard Klimeck, Technical Director, Network for Computational Nanotechnology, Purdue University, 01/10 2007 e-mail中的一段得知: “..Interestingly enough we have difficulty trying to get success stories like this and the NSF keeps asking us if the site is useful for research….”. 本人最近更審查 國外十幾篇有關 Channel Backscattering 的 submitted papers.

五、 結論與討論 (ii)

應變矽 技 術最近 已 被廣泛 應 用在奈 米

CMOS

製程技術中。 主要有二種不同的方法

在製程中加入應力: (1) 在矽鍺基板上長出磊

晶矽原子層; 以及(2) 利用製程步驟本身及材

料性質差異製造應力，如：淺塹渠絕緣、覆蓋

層、矽化物或者矽鍺源汲極等。至目前為止，

針對機械應力的重要性有兩個主要的探討方

向。其一是晶圓在生產過程所感受的機械應力

會增強或減緩雜質的擴散，也因此影響最終掺

雜在元件之中分佈的情形。在做了上述這些製

程的改變後，檢驗應變矽元件表面特性及閘級

介電層的健全度是否受到影響是很重要的。另

一方面，機械應力也可改變元件的能帶結構，

因之改變了電晶體特性，諸如載子遷移率、熱

載子造成的可靠度問題、臨界電壓和閘極直接

穿隧電流等。憑仗這幾年的努力，我們已在應

變矽技術領域產出重要成果:

z

利用閘極直接穿隧電流估算應變矽金氧

半場效電晶體通道應力大小

能夠定量的推斷出元件結構內部的應力

大小及應力的種類(如：壓縮應力、伸張應力)

是必要的。目前已經有三種評估元件結構內部

應力的方法被提出：(1) 彎曲晶圓夾具，(2)精

密的應力模擬，及(3)拉曼光譜。但是利用電晶

體電性改變來推斷內部應力大小及種類的方

法仍未被提出過。然而，值得一提的是經由外

部施加應力造成的閘極直接穿隧電流改變已

經被深入的探討過了。另一方面，根據最近的

研究，形變位能係數已經可由實驗萃取而得，

並且和理論計算所預測的值一致。因此，在形

變位能係數已知的情況下，利用閘級穿隧電流

來反推元件內部應力大小已經變成一個可行

的方案。研究細節可參考我們發表的相關文獻:

C. Y. Hsieh and M. J. Chen, “Measurement of channel stress

using gate direct tunneling current in uniaxially stressed

n-MOSFETs,” IEEE Electron Device Letters, vol. 28, pp.

818-820, Sept. 2007.

z

應力製程微觀物理

我們在產製下世代受應力電子元件 Strain

Engineering

領 域 針 對 Uniaxial Strain 下

Impurities (為目前國際上高度挑戰卻也爭議性

極大的題目) 在 Silicon 的高溫特殊擴散行為

提出前所未有、創新微觀物理模式並獲得實驗

強力支持。且藉由成熟的元件製程模擬，所謂

的 TCAD(製程電腦輔助設計)，可以延伸到實

際元件的應用。研究細節可參考我們發表的相

關文獻:

1. M. J. Chen and Y. M. Sheu, “Effect of uniaxial strain on anisotropic diffusion in silicon,” Applied Physics Letters, Vol. 89, pp. 161908-1-181908-3, Oct., 2006.

2. Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 30-38, January 2005.

此兩篇論文最近被跨國際團隊(IMEC, Univ. Leuven, ASM USA,

ASM Belgium, and TI)引用:

E. Simoen, et al., “Leakage current study of Si1-xCx embedded source/drain junctions,” Applied Surface Science, vo. 254, pp. 6140-6143, March 2008.

z

藉由邊緣直接穿隧電流量測在機械應力

下雜質的擴散情況

能夠擁有從電性量測反推元件因生產過程

而增強或是減低雜質擴散的能力是不可或缺

的。傳統上，這是由 TCAD 來達成。我們提出

了一個電性的方法,稱之為邊緣直接穿隧電流

的方式，可直接地決定在源極及汲極的局部機

械應力對摻雜在通道中橫向的擴散。研究細節

可參考我們發表的一篇長文:

C. Y. Hsieh and M. J. Chen, “Electrical measurement of

local stress and lateral diffusion near source/drain extension

corner of uniaxially stressed n-MOSFETs,” IEEE Trans.

Electron Devices, vol.55, pp. 844-849, March 2008.

z

量測應變矽 MOSFETs 閘級介電層與矽介

5

在做了應變製程的改變後，檢驗應變矽元

件表面特性及閘級氧化層介面的健全度是否

受到影響是很重要的。而我們最近進行的應變

矽MOSFETs元件的1/f低頻雜訊量測正好可以

作為此一議題深入分析的有效工具。研究細節

可參考我們發表的相關文獻:

1. M. P. Lu, W. C. Lee, M. J. Chen, “Channel-width dependence of low-frequency noise in process tensile-strained n-channel metal-oxide-semiconductor transistors,” Applied Physics Letters, vol. 88, pp. 063511-1—063511-3, Feb. 2006.

2. C. Y. Hsieh, Y. T. Lin, T. H. Liang, W. C. Lee, J. B. Bouche, and M. J. Chen, “Effect of STI mechanical stress on p-channel gate oxide integrity,” IEEE Semiconductor Interface Specialist Conference, p.5, 2007.

z

我們另有其他貢獻於應變矽技術領域者:

國際上，從事應變矽技術的研究者在 IEEE

Symposium on VLSI Technology

頂尖國際會議

上引用了我們的成果:

1. H. Tsuno, K. Anzai, M. Matsumura, S. Minami, A. Honjo, H. Koike, Y. Hiura, A. Takeo, W. Fu, Y. Fukuzaki, M. Kanno, H. Ansai, and N. Nagashima, “Advanced analysis and modeling of MOSFET characteristics fluctuation caused by layout variation,” IEEE Symposium on VLSI Technology, p. 204, 2007.

2. V. Barral, et al., “Will strain be useful for 10nm quasi-ballistic FDSOI devices? An experimental study,” IEEE Symposium on VLSI Technology, p. 128, 2007.

3. H. N. Lin, et al., “The impact of uniaxial strain engineering on channel backscattering in nanoscale MOSFETs” IEEE Symposium on VLSI Technology, p. 174, 2005.

z

我們培育出應變矽技術的頂尖人才

:

1.

許 義 明 博 士 : 2007 年 畢 業 (with Ph.D.

Dissertation entitled “Layout Dependent Effect

on Advanced MOSFETs”) 即成為 TSMC RD

Manager. TCAD and Device Engineering

領域權

威, 曾發表多篇 IEDM 及 Symposium on VLSI

Technology

會議論文.

2.

黃煥宗博士：TSMC 32/22 奈米 RD 技術經

理; 2003-2005 年選派為 Scientist to Freescale

Company, USA. 曾 發 表 多 篇 IEDM 及

Symposium on VLSI Technology

會議論文; 去

年就以第一作者領銜一篇IEDM 論文:

H. T. Huang, et al., “45nm high-k/metal-gate CMOS technology for GPU/NPU applications with highest PFET performance,” IEEE IEDM Tech. Dig., p. 285, 2007.

參考文獻:

1. M. J. Chen, R. T. Chen, Y. S. Lin, “Decoupling channel backscattering coefficients in nanoscale MOSFETs to establish near-source channel conduction-band profiles,” IEEE Silicon Nanoelectronics Workshop, pp. 50-51, 2005.

2. Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, L. P. Huang, T. Y. Huang, M. J. Chen, and C. H. Diaz, “Modeling mechanical stress effect on dopant diffusion in scaled MOSFETs,” IEEE Trans. Electron Devices, vol. 52, pp. 30-38, January 2005. 3. M. P. Lu, C. Y. Hsian, P. Y. Lo, J. H. Wei, Y. S. Yang, and M. J.

Chen, “Semiconducting single-walled carbon nanotubes exposed to distilled water and aqueous solution: electrical measurement and theoretical calculation,” Applied Physics Letters, vol. 88, pp. 053114-1—053114-3, Feb. 2006.

4. M. P. Lu, C. Y. Hsian, P. Y. Lo, J. H. Wei, Y. S. Yang, and M. J. Chen, “Semiconducting single-walled carbon nanotubes exposed to distilled water and aqueous solution: electrical measurement and theoretical calculation,” Selected Articles in Virtual Journal of Nanoscale Science & Technology, Vol. 13, Issue 6, 2006. 5. M. P. Lu, C. Y. Hsian, P. Y. Lo, J. H. Wei, Y. S. Yang, and M. J.

Chen, “Semiconducting single-walled carbon nanotubes exposed to distilled water and aqueous solution: electrical measurement and theoretical calculation,” Selected Articles in Virtual Journal of Biological Physics Research, Vol. 11, Issue 4, 2006.

6. M. P. Lu, W. C. Lee, M. J. Chen, “Channel-width dependence of low-frequency noise in process tensile-strained n-channel metal-oxide-semiconductor transistors,” Applied Physics Letters, vol. 88, pp. 063511-1—063511-3, Feb. 2006.

7. Y. M. Sheu, S. J. Yang, C. C. Wang, C. S. Chang, M. J. Chen, S. Liu, and C. H. Diaz, “Reproducing subthreshold characteristics of metal-oxide-semiconductor field effect transistors under shallow trench isolation mechanical stress using a stress-dependence diffusion model,” Japanese Journal of Applied Physics, vol. 45, pp. L849-L851, August 2006.

8. Y. M. Sheu, K. W. Su, S. Tian, S. J. Yang, C. C. Wang, M. J. Chen, and S. Liu, “Modeling the well-edge proximity effect in highly-scaled MOSFETs,” IEEE Trans. Electron Devices, Vol. 53, pp. 2792-2798, Nov., 2006.

9. M. J. Chen and Y. M. Sheu, “Effect of uniaxial strain on anisotropic diffusion in silicon,” Applied Physics Letters, Vol. 89, pp. 161908-1-181908-3, Oct., 2006.

10. M. J. Chen, S. G. Yan, R. T. Chen, C. Y. Hsieh, P. W. Huang, and H. P. Chen, “Temperature oriented experiment and simulation as corroborating evidence of MOSFET backscattering theory,” IEEE Electron Device Letters, vol. 28, pp. 177-179, Feb. 2007. 11. C. Y. Hsieh and M. J. Chen, “Measurement of channel stress

using gate direct tunneling current in uniaxially stressed n-MOSFETs,” IEEE Electron Device Letters, vol. 28, pp. 818-820, Sept. 2007.

12. C. Y. Hsieh, Y. T. Lin, T. H. Liang, W. C. Lee, J. B. Bouche, and M. J. Chen, “Effect of STI mechanical stress on p-channel gate oxide integrity,” IEEE Semiconductor Interface Specialist Conference, p.5, 2007 (Arlington).

13. D. W. Lin, M. L. Cheng, S. W. Wang, C. C. Wu, and M. J. Chen, “A constant mobility method to enable MOSFET series resistance extraction,” IEEE Electron Device Letters, vol. 28, pp. 1132-2234, December, 2007.

14. C. Y. Hsieh and M. J. Chen, “Electrical measurement of local stress and lateral diffusion near source/drain extension corner of uniaxially stressed n-MOSFETs,” IEEE Trans. Electron Devices, vol.55, pp. 844-849, March 2008.

15. M. J. Chen and L. F. Lu, “A parabolic potential barrier oriented compact model for the kBT layer’s width in nano-MOSFETs,” IEEE Trans. Electron Devices, vol.55, pp. 1265-1268, May 2008. 16. D. W. Lin, M. Wang, M. L. Cheng, Y. M. Sheu, B. Tarng, C. M.

Chu, C. W. Nieh, C. P. Lo, W. C. Tsai, R. Lin, S. W. Wang, K. L. Cheng, C. M. Wu, M. T. Lei, C. C. Wu, C. H. Diaz, and M. J. Chen, “A millisecond-anneal-assisted selective (FUSI) gate process,” IEEE Electron Device Letters, vol. 29, pp. 998-1000, Sept. 2008.

17. M. J. Chen, L. F. Lu, and C. Y. Hsu, “On the mean-free-path for backscattering in kBT layer of bulk nano-MOSFETs,” IEEE Trans. Electron Devices, accepted and will be published in the December issue, 2008.

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 5, MAY 2008 1265

A Parabolic Potential Barrier-Oriented Compact

Model for the

k

_B

T

Layer’s Width in

Nano-MOSFETs

Ming-Jer Chen, Senior Member, IEEE, and Li-Fang Lu

Abstract—On the basis of a parabolic potential profile around

the source-channel junction barrier of nanoscale MOSFETs, a

new compact model is physically derived, which links the width

of thermal energy k

B

T layer (a critical zone in the context of

the backscattering theory) to the geometrical and bias parameters

of the devices. The proposed model is supported by

experimen-tal data and by a critical analysis of various simulation works

presented in the literature. The only fitting parameter remains

constant in a wide range of channel length (10–65 nm), gate

voltage (0.4–1.2 V), drain voltage (0.2–1.2 V), and temperature

(100 K–500 K). The confusing temperature-dependent issues in the

open literature are straightforwardly clarified.

Index Terms—Backscattering, MOSFET, nanometer.

I. I

NTRODUCTION

W

HILE applied to electrically saturated nanoscale

MOSFETs, the channel backscattering theory [1], [2]

establishes a link between the thermal energy k

B

T layer, which

occupies a small fraction of the conductive channel near the

source, and the drive capability of the device. Thus, the ability

to quantitatively determine the width of this critical zone is

essential. To address the issue transparently, an analytically

compact treatment is desirable. One such model can be quoted

in the literature [3]

l

≈ L

k

B

T

qV

D



α

(1)

where l is the width of the k

B

T layer, and L is the metallurgical

channel length. However, so far, there has been some confusion

as to the magnitude of the temperature power exponent α. First

of all, fitting of the room-temperature I–V characteristics of

a simulation double-gate MOSFET has produced the apparent

α

≈ 0.57 [3]. Comparable α ≈ 0.5 has also been obtained

on experimental bulk n-MOSFETs in a temperature range of

233 K–298 K [4], [5]. In contrast, for the bulk case

cover-ing the same temperature range, a higher α

≈ 0.75 has been

Manuscript received November 15, 2007; revised January 28, 2008. This work was supported by the National Science Council of Taiwan, R.O.C., under Contract NSC 96-2221-E-009-187. The review of this brief was arranged by Editor C. Jungemann.

The authors are with the Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. (e-mail: chenmj@faculty. nctu.edu.tw).

Color versions of one or more of the figures in this brief are available online at http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2008.919317

experimentally determined [6]. Even α

≈ 1 has already been

adopted in a temperature-dependent backscattering-coefficient

extraction method [7]. This is also the case for the recent

double-gate device simulation [8], which has shown that l is

approximately proportional to the temperature from 100 K to

500 K. Obviously, these widespread values of the apparent α

must be clarified. On the other hand, a study on experimental

bulk n-MOSFETs has revealed that l significantly decreases

with increasing gate voltage [4], [6]; however, it is difficult for

(1) to elucidate due to the lack of the gate voltage. This hurdle

may be overcome by accurate modeling of the potential profile

in the channel [9]; however, a simple approach without loss of

accuracy is favored.

In this brief, the experimentally determined parabolic

po-tential profile in the previous work [4], [5] will be utilized to

approximate the source-channel junction barrier of nanoscale

MOSFETs in saturation. Then, a new compact model will be

physically derived for l with the channel length, gate overdrive,

drain voltage, and temperature as input parameters. The validity

and applicability of the resulting model will also be examined,

followed by a significant clarification on the aforementioned α

differences.

II. P

ARABOLIC

B

ARRIER

P

ICTURE

A parabolic potential profile near the source is schematically

shown in Fig. 1. Its extension to the remaining channel can be

described by

V (x) = V

D

(x/

L)

2

.

(2)

The origin x = 0 indicates the peak of the barrier. 

L is the

apparent channel length corresponding to a certain position

where the parabolic potential drop from the top of the barrier

is equal to V

D

. Here, the barrier height with respect to the

source side is neglected due to the large drain voltages used. By

substituting x = l into (2) for a local potential drop of k

B

T /q

to constitute the thermal energy layer [1], [2], the following

expression can be obtained:

l = 

L

k

B

T

qV

D



0.5

.

(3)

L is expected to be a function of the channel length, gate and

drain voltage, and temperature. In other words, there exists a set

1266 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 5, MAY 2008

Fig. 1. Schematic demonstration of the parabolic source-channel potential barrier picture corresponding to nano-MOSFET in saturation. The parabolic potential profile is extended to the drain side to highlight the apparent channel length designated by



L. Also shown is the width l of the kBT layer.

of the specific gate and drain voltage denoted by V

Go

and V

Do

,

respectively, at a given temperature T

o

, which can ensure that

L = L. The corresponding thermal energy layer has a width

denoted by l

o

, which can be calculated from (3) with 

L

→ L,

T

→ T

o

, and V

D

→ V

Do

. Then, if the temperature

individu-ally changes from T

o

to T , a power-law relation can hold:

L = L(T/T

o

)

0.5

. This formalism can be obtained by assuming

that the potential profile does not change with temperature;

that is, the local electric field across the thermal energy layer

(≈k

B

T

o

/ql

o

, according to the backscattering theory [1], [2])

at T

o

is approximately equal to that (≈k

B

T /ql) at T . As for

gate-voltage factor, a similar relation can be physically derived

but expressed in terms of the gate overdrive (the gate voltage

V

G

minus the threshold voltage V

th

). This is achieved by twice

differentiating (2) with respect to x, leading to d

2

V (x)/dx

2

=

2V

D

/

L

2

, which, according to Poisson’s equation (see [3] for

details), can be linearly related to the underlying inversion-layer

carrier density or, equivalently, the gate overdrive. As a

re-sult, one achieves 

L = L((V

Go

− V

th

)/(V

G

− V

th

))

0.5

. Here,

the term V

Go

− V

th

represents the specific gate overdrive for

L approaching L. Finally, if the drain voltage increases to

V

D

(> V

Do

), the local electric field [= 2V

D

x/

L

2

as from (2)]

must be larger than that (= 2V

Do

x/L

2

) at V

Do

. As a result,

one obtains 

L = L(V

D

/V

Do

)

ν

with the power exponent ν of

no more than 0.5. This formula remains valid for V

D

< V

Do

.

Indeed, ν of around 0.25 has been experimentally determined

elsewhere [4] and will be cited here.

Through the combination of the aforementioned power-law

relationships, a unique expression can be created for 

L

L = ηL

V

D0.25

(V

G

− V

th

)

0.5

k

B

T

q



0.5

.

(4)

Here, η = (k

B

T

o

/q)

−0.5

(V

Go

− V

th

)

0.5

V

Do−0.25

. In this brief, η

is fixed and is also the only fitting parameter. It is expected

that η is a constant, regardless of the channel length, gate and

drain voltage, and temperature; otherwise, the applicability of

the resulting model may be limited.

III. C

ONFIRMATIVE

E

VIDENCE AND

C

LARIFICATION

The experimental l was created from 55-nm bulk

n-MOSFETs by means of a parameter extraction process detailed

elsewhere [4]–[6]. The results are shown in Fig. 2 versus gate

voltage for two drain voltages of 0.5 and 1.0 V and three

temperatures of 233 K, 263 K, and 298 K. With known l, T ,

and V

D

, the corresponding 

L can be obtained directly from

(3), as shown in Fig. 2(c) and (d) versus the gate voltage. The

near-equilibrium threshold voltages denoted by V

tho

are 0.360,

0.345, and 0.328 V for 233 K, 263 K, and 298 K, respectively,

and the drain-induced barrier lowering (DIBL) magnitudes are

120, 123, and 130 mV/V, respectively. Throughout this brief,

the threshold voltage V

th

at higher drain voltages is equal

to V

tho

− DIBL × V

D

[4]–[7]. Also shown in Fig. 2 are the

calculated results from (3) and (4) using a specific η whose

value will be explained slightly later. On the other hand, the rich

literature [8], [10] dedicated to double-gate device simulations

is quoted. First, in [8], the extracted l at V

D

= V

G

= 1 V is

available in a wide range of the channel length from 14 to

37 nm and the temperature from 100 K to 500 K. The

underlying threshold voltage V

tho

and DIBL are reasonably

0.3 V and 110 mV/V, respectively [10]. Second, the citation

[10] can further provide the relevant data at 300 K: l from

2.0 to 7.0 nm, L from 14 to 65 nm, V

D

(= V

G

) from 1.0

to 1.2 V, and DIBL from 11 to 230 mV/V. In addition, we

have also extracted l directly from the published channel

potential profiles on the simulation double-gate devices [2],

[3], [9], [11], [12]. The corresponding key parameters are the

following: 1) L = 10 nm, V

tho

≈ 0.33 V, DIBL ≈ 140 mV/V,

V

D

= 0.6 V, V

G

= 0.6 V, and T = 300 K [2]; 2) L = 20 nm,

V

tho

≈ 0.33 V, DIBL ≈ 25 mV/V, V

D

= 0.2 V, V

G

= 0.55 V,

and T = 300 K [3]; 3) L = 25 nm, V

tho

≈ 0.3 V, DIBL ≈

100 mV/V, V

D

= 0.8 V, V

G

= 0.5, 0.8, and 1.0 V, and T =

300 K [9]; 4) L = 15 nm, V

tho

≈ 0.2 V, DIBL ≈ 120 mV/V,

V

D

= 0.7 V, V

G

= 0.7 V, and T = 300 K [11]; and 5) L =

15 nm, V

tho

≈ 0.3 V, DIBL ≈ 77 mV/V, V

D

= 0.7 V, V

G

=

0.7 V, and T = 300 K [12]. At this point, a scatter plot can

be created, as shown in Fig. 3, in terms of the experimental

and simulated l versus the quantity of the functional

expres-sion LV

_D0.25

(V

G

− V

th

)

−0.5

(k

B

T /q)

0.5

(k

B

T /qV

D

)

0.5

.

Strik-ingly, all data are seen to fall on or around a straight line. The

slope of the line furnishes η with a value of 4.1 V

−0.25

. As

expected, η remains constant, regardless of the channel length,

gate and drain voltage, and temperature.

Some remarks can now be made to clarify the confusing α

values in the open literature [3]–[8]. First, it is noticed that in

the case of bulk n-MOSFET, two different values of α were

produced: one of 0.5 [4], [5] and one of 0.75 [6]. This difference

can be attributed to the different subband treatments during the

parameter extraction process. A Schrödinger–Poisson equation

solving was utilized in [4] and [5], whereas in [6], this was done

by a triangular potential approximation [13]. Therefore, the

different subband levels can lead to different average thermal

injection velocities, which in turn give rise to different l values.

Second, based on (4), the temperature range of 233 K–298 K

in case of a 55-nm bulk device [4], [5] is not large enough

to affect the calculated 

L. In other words, 

L is considerably

CHEN AND LU: PARABOLIC POTENTIAL BARRIER-ORIENTED COMPACT MODEL FOR THE kBT LAYER’S WIDTH 1267

Fig. 2. Measured and calculated l versus gate voltage at two drain voltages of (a) 0.5 V and (b) 1.0 V for three temperatures and the correspondingL versus



gate voltage for the drain voltages of (c) 0.5 V and (d) 1.0 V. The test device is a 55-nm bulk n-MOSFET. The calculation lines are from (3) and (4) with η = 4.1 V−0.25.

Fig. 3. Scatter plot of the experimental and simulated l versus the quantity of the functional expression L(V0.25

D )(VG− Vth)−0.5(kBT /

q)0.5_(k

BT /qVD)0.5. Also shown is a straight line which fits the data points.

The slope of the line yields η of 4.1 V−0.25.

insensitive to such a narrow temperature range. Consequently,

the resulting apparent temperature power exponent was limited

to 0.5, as reported in the previous work [4], [5]. Indeed, with

the known η as input, fairly good reproduction can be achieved,

as shown in Fig. 2, without adjusting any parameters. The same

interpretations also apply to the α

≈ 0.57 case [3]. Only the

room temperature of operation was involved, and therefore,

the temperature effect of 

L can no longer be examined. In

other words, only in a wide temperature range (as done in the

comprehensive study of [8] and [10]) can the linear relationship

of l

∝ T , as shown in Fig. 3, be observed. Finally, from the

aspect of temperature dependences or the excellent coincidence

with a significant number of data, as shown in Fig. 3, the

exist-ing backscatterexist-ing-coefficient extraction method [7] is valid.

IV. C

ONCLUSION

Based on a parabolic potential profile that is used to

ap-proximate the source-channel junction barrier of nanoscale

MOSFETs, a new compact model of the k

B

T layer’s width

has been physically derived along with the channel length, gate

overdrive, drain voltage, and temperature as input. The validity

of the parabolic potential barrier picture and the applicability

of the resulting compact model have been justified by

exper-imental data and by a critical analysis of various simulation

works presented in the literature. In particular, the confusing

temperature-dependent issues in the open literature have been

satisfactorily clarified.

1268 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 55, NO. 5, MAY 2008

R

EFERENCES

[1] M. S. Lundstrom, “Elementary scattering theory of the Si MOSFET,” IEEE Electron Device Lett., vol. 18, no. 7, pp. 361–363, Jul. 1997. [2] M. Lundstrom and Z. Ren, “Essential physics of carrier transport in

nanoscale MOSFETs,” IEEE Trans. Electron Devices, vol. 49, no. 1, pp. 133–141, Jan. 2002.

[3] A. Rahman and M. S. Lundstrom, “A compact scattering model for the nanoscale double-gate MOSFET,” IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 481–489, Mar. 2002.

[4] M. J. Chen, R. T. Chen, and Y. S. Lin, “Decoupling channel backscatter-ing coefficients in nanoscale MOSFETs to establish near-source channel conduction-band profiles,” in Proc. Silicon Nanoelectronics Workshop, Jun. 2005, pp. 50–51.

[5] M. J. Chen, S. G. Yan, R. T. Chen, C. Y. Hsieh, P. W. Huang, and H. P. Chen, “Temperature-oriented experiment and simulation as cor-roborating evidence of MOSFET backscattering theory,” IEEE Electron Device Lett., vol. 28, no. 2, pp. 177–179, Feb. 2007.

[6] M. J. Chen, H. T. Huang, Y. C. Chou, R. T. Chen, Y. T. Tseng, P. N. Chen, and C. H. Diaz, “Separation of channel backscattering coef-ficients in nanoscale MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 9, pp. 1409–1415, Sep. 2004.

[7] M. J. Chen, H. T. Huang, K. C. Huang, P. N. Chen, C. S. Chang, and C. H. Diaz, “Temperature dependent channel backscattering coefficients in nanoscale MOSFETs,” in IEDM Tech. Dig., Dec. 2002, pp. 39–42. [8] P. Palestri, D. Esseni, S. Eminente, C. Fiegna, E. Sangiorgi, and

L. Selmi, “Understanding quasi-ballistic transport in nano-MOSFETs: Part I—Scattering in the channel and in the drain,” IEEE Trans. Electron Devices, vol. 52, no. 12, pp. 2727–2735, Dec. 2005.

[9] E. Fuchs, P. Dollfus, G. L. Carval, S. Barraud, D. Villanueva, F. Salvetti, H. Jaouen, and T. Skotnicki, “A new backscattering model giving a de-scription of the quasi-ballistic transport in nano-MOSFET,” IEEE Trans. Electron Devices, vol. 52, no. 10, pp. 2280–2289, Oct. 2005.

[10] S. Eminente, D. Esseni, P. Palestri, C. Fiegna, L. Selmi, and E. Sangiorgi, “Understanding quasi-ballistic transport in nano-MOSFETs: Part II—Technology scaling along the ITRS,” IEEE Trans. Electron De-vices, vol. 52, no. 12, pp. 2736–2743, Dec. 2005.

[11] J. Saint-Martin, A. Bournel, and P. Dollfus, “On the ballistic transport in nanometer-scaled DG MOSFETs,” IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1148–1155, Jul. 2004.

[12] D. Querlioz, J. Saint-Martin, K. Huet, A. Bournel, V. Aubry-Fortuna, C. Chassat, S. Galdin-Retailleau, and P. Dollfus, “On the ability of the par-ticle Monte Carlo technique to include quantum effects in nano-MOSFET simulation,” IEEE Trans. Electron Devices, vol. 54, no. 9, pp. 2232–2242, Sep. 2007.

[13] K. N. Yang, H. T. Huang, M. C. Chang, C. M. Chu, Y. S. Chen, M. J. Chen, Y. M. Lin, M. C. Yu, S. M. Jang, C. H. Yu, and M. S. Liang, “A physical model for hole direct tunneling current in p+_{poly-gate pMOSFETs with} ultrathin gate oxides,” IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2161–2166, Nov. 2000.

Ming-Jer Chen (S’78–M’85–SM’98) received the

B.S. degree in electrical engineering (with highest honors) from the National Cheng Kung University, Tainan, Taiwan, R.O.C., in 1977, and the M.S. and Ph.D. degrees in electronics engineering from the National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 1979 and 1985, respectively.

Since 1985, he has been with the Department of Electronics Engineering, NCTU, where he has been a Full Professor since 1993. From 1987 to 1992, he was a Consultant for the Taiwan Semiconductor Manufacturing Company, where he led a team from the NCTU and the Electronics Research and Service Organization/Industrial Technology Research Institute to build up a series of process windows and design rules. From 2000 to 2001, he was a Visiting Professor with the Department of Electrical Engineering, Stanford University, Stanford, CA. He is the holder of eight U.S. patents and six Taiwanese patents in the field of the high-precision analog capacitors, 1-T memory cell, dynamic threshold MOS, electrostatic discharge protection, and Flash memory. He has graduated 14 Ph.D. students and more than 90 M.S. students. His current research interests include semiconductor device physics and nanoelectronics.

Dr. Chen is a member of the Phi Tau Phi.

Li-Fang Lu was born in Taoyuan, Taiwan, R.O.C.,

in 1982. He received the B.S. degree in electro-physics from the National Chiao Tung University, Hsinchu, Taiwan, in 2006, where he is currently working toward the M.S. degree in the Department of Electronics Engineering.

His main research interest is on the physics about backscattering theory in nanoscale devices.

Effect of uniaxial strain on anisotropic diffusion in silicon

Ming-Jer Chen

a兲

and Yi-Ming Sheu

Department of Electronics Engineering, National Chiao Tung University, Hsin-Chu 300, Taiwan

共Received 9 June 2006; accepted 30 August 2006; published online 17 October 2006兲

A physical model is directly extended from the thermodynamic framework to deal with anisotropic

diffusion in uniaxially stressed silicon. With the anisotropy of the uniaxial strain induced activation

energy as input, two fundamental material parameters, the activation volume and the migration

strain anisotropy, can be quantitatively determined. When applied to boron, a process-device

coupled simulation is performed on a p-type metal-oxide-semiconductor field-effect transistor

undergoing uniaxial stress in a manufacturing process. The resulting material parameters have been

found to be in satisfactory agreement with values presented in the literature. © 2006 American

Institute of Physics.

关DOI:

10.1063/1.2362980

兴

Strain engineering has been widely recognized as an

in-dispensable

performance

booster

in

producing

next-generation metal-oxide-semiconductor field-effect transistors

共MOSFETs兲.

1,2

There have been two fundamentally different

methods used to achieve this goal:

1,2

共i兲 biaxially strained

silicon on a relaxed SiGe buffer layer and

共ii兲 uniaxially

strained silicon through the use of trench isolation, silicide,

and cap layers during the manufacturing process. However,

diffusion in strained silicon is essentially different from that

of unstrained silicon. Thus, an understanding of strain

depen-dent diffusion, as well as its control, is a challenging issue.

So far, there have been significant studies in this direction

covering a wide range of experimental findings and

confirmations,

3–9

atomistic

calculations,

10–13

physical

models,

10–16

and technology computer-aided design.

17

Spe-cifically, Cowern et al.

5

experimentally revealed a linear

de-pendence of the activation energy on strain. Within the

ther-modynamic framework constructed by Aziz et al.

共see Ref.

18

, which is more recent and more thorough than the earlier

works cited above兲, the activation volume 共V˜兲 and the

aniso-tropy of the migration volume

共V˜

储

m

− V

˜

_⬜m

兲 exist in nature. The

combination of the activation energy, the activation volume,

and the anisotropy of the migration volume is remarkable, as

demonstrated in a physical model

14–16,18

dedicated to both

the hydrostatic pressure experiment and the in-plane biaxial

stress experiment,

V

˜ +

3

2

Q

_33−biax

⬘

Y

biax

= ±

⍀ + 共V˜

储 m

− V

˜

_⬜m

兲,

共1兲

V

˜ +

3

2

Q

_11−biax

⬘

Y

biax

= ±

⍀ −

1

2

共V˜

储 m

− V

˜

_⬜m

兲,

共2兲

where Q

_33−biax

⬘

is the biaxial strain induced activation energy

in the direction normal to the silicon surface, Y

biax

is the

biaxial modulus,

⍀ is the lattice site volume, and Q

_11−biax

⬘

is

the biaxial strain induced activation energy in the direction

parallel to the surface.

On the other hand, in the case of uniaxial stress as

en-countered while fabricating the MOSFET, without the use of

a relaxed SiGe buffer layer, the stress is created through the

trench isolation, silicide, or cap layers in a manufacturing

process. Therefore, a straightforward extension to the

uniaxial strain counterpart is essential. In this letter, one such

model is derived and its linkage to the case of biaxial strain,

Eqs.

共1兲

and

共2兲

, is established. When applied to boron, a

process-device coupled simulation is performed on a p-type

MOSFET undergoing uniaxial stressing during the

manufac-turing process, followed by a systematic assessment of the

fundamental material parameters.

According to Aziz

14

and Aziz et al.,

18

in the case of

equilibrium or a quickly equilibrated point defect, the effect

of stress on the dopant diffusivity in the direction normal to

a

共001兲 surface can be written as

D

33

共

␴

兲

D

33

共0兲

= exp

冉

␴

关V

f

_{+ V}

_˜

33 m

_兴

k

B

T

冊

.

共3兲

Here the product of the stress tensor

␴

and the formation

strain tensor V

f

is the work done against the stress field in

defect formation, the product of the stress tensor

␴

and the

migration strain tensor V

˜

₃₃m

is the work required for the

tran-sition in the migration path, k

B

is Boltzmann’s constant, and

T is the diffusion temperature. The tensor V

f

_{involves the}

creation or annihilation of a lattice site, followed by a

relax-ation process,

14,18

V

f

= ±

⍀

冤

0

0

1

冥

+

V

r

3

冤

1

1

1

冥

.

共4兲

The

⫹ sign denotes vacancy formation and the ⫺ sign

rep-resents interstitial formation. The relaxation volume

propa-gates elastically to all surfaces, resulting in a change in the

volume of the crystal by an amount V

r

_{. V}

˜

33

m

is expected to

have the form

14,18

V

˜

33 m

=

冤

V

˜

⬜ m

V

˜

⬜ m

V

˜

储 m

冥

.

共5兲

In Eq.

共5兲

, V

˜

_⬜m

and V

˜

储 m

, respectively, reflect the dimension

changes perpendicular and parallel to the direction of the net

transport when the point defect reaches its saddle point.

14,18

Aziz further defined the activation volume as the sum of the

a兲_{Electronic mail: [email protected]}

APPLIED PHYSICS LETTERS 89, 161908

共2006兲

0003-6951/2006/89共16兲/161908/3/$23.00 89, 161908-1 © 2006 American Institute of Physics

three diagonal elements of the formation strain tensor and the

migration strain tensor, as expressed by

V

˜ = ± ⍀ + V

r

+ 2V

˜

_⬜m

+ V

˜

储

m

.

共6兲

It is well recognized

12

that when applying a uniaxial

stress in a certain direction parallel to the silicon surface, the

solid will modify its shape in order to minimize the energy of

the system. In other words, the solid will deform in such a

way that each surface perpendicular to the applied stress

di-rection becomes stress-free. The underlying stress tensor

therefore is

␴

=

␴

_uniax

冤

1

0

0

冥

.

共7兲

On the basis of Hooke’s law,

␴

uniax

in the linear elastic

re-gime can be related to the uniaxial strain

␧

_uniax

induced in the

same direction:

␴

_uniax

= Y

_uniax

␧

_uniax

, where the uniaxial

modu-lus Y

uniax

=

共C

11

− 2

␯

C

12

兲 with Poisson’s ratio

␯

= C

12

/

共C

11

+ C

12

兲. C

11

and C

12

are the elasticity constants. Analogous to

previous work,

5

the uniaxial strain induced activation energy

in the direction normal to the

共001兲 surface, Q

_33−uniax

⬘

, can be

linked to the underlying diffusivity,

D

33

共␧

uniax

兲

D

33

共0兲

= exp

冉

−

Q

33−uniax

⬘

␧

uniax

k

B

T

冊

.

共8兲

By combining Eqs.

共4兲

,

共5兲

, and

共7兲

and equalizing Eqs.

共3兲

–

共8兲

, one obtains Q

_33−uniax

⬘

/ Y

uniax

=−V

r

/ 3 − V

˜

⬜m

. Again, by

incorporating Eq.

共6兲

, the following expression is produced:

V

˜ + 3

Q

33−uniax

⬘

Y

uniax

= ±

⍀ + 共V˜

m储

− V

˜

⬜m

兲.

共9兲

It is then a straightforward task to derive the uniaxial strain

induced activation energy Q

_11−uniax

⬘

in the applied stress

di-rection: Q

_11−uniax

⬘

/ Y

_uniax

= −V

r

_{/ 3 − V}

_˜

储 m

. Consequently, a similar

model is achieved,

V

˜ + 3

Q

11−uniax

⬘

Y

uniax

= ±

⍀ − 2共V˜

储 m

− V

˜

_⬜m

兲.

共10兲

Obviously, the uniaxial strain version is closely related to its

biaxial counterpart: by comparing Eqs.

共1兲

and

共9兲

,

Q

_33−uniax

⬘

=

共Y

uniax

/ 2Y

biax

兲Q

33−biax

⬘

is

obtained.

Another

relation

can

then

be

readily

derived:

Q

_11−uniax

⬘

= −共Y

uniax

/ 2Y

biax

兲Q

33−biax

⬘

+

共Y

uniax

/ Y

biax

兲Q

11−biax

⬘

.

To produce the experimental parameters in terms of the

anisotropy of the uniaxial strain induced activation energy, a

uniaxial stress experiment was carried out in terms of a

p-channel MOSFET in a state-of-the-art manufacturing

process.

17

The channel length was maintained at 65 nm

while changing the spacing in the channel length direction

between the two trench isolation sidewalls. The topside

lay-out is detailed elsewhere.

17

Under such a situation, the

chan-nel zone encounters a compressive stress from the nearby

trench isolation regions in the channel length direction. The

devices used are quite wide

共10

␮

m兲, meaning that the strain

in the channel width direction is relatively negligible. The

共001兲 silicon surface is supposed to be stress free. This

hy-pothesis has been validated using the sophisticated

simula-tions detailed in Ref.

17

, which revealed that in the

proxim-ity of the silicon surface, the stress in the channel length

direction is much larger in magnitude than that in the

direc-tion normal to the surface. Therefore, the proposed physical

model can be adequately applied. The effect of changing the

spacing between the two trench isolation regions in the

chan-nel length direction is reflected in the measured saturation

threshold voltage, as displayed in Fig.

1

. The negative shift

in the saturation threshold voltage with increasing stress

共via

decreasing spacing between the trench isolation regions兲

shown in Fig.

1

can be attributed to the retarded boron

dif-fusion.

A two-dimensional process-device coupled simulation,

as detailed in Ref.

17

, was slightly modified by taking the

anisotropy of the boron diffusivity into account,

D

33

共␧

t

兲

D

₃₃

共0兲

= exp

冉

−

Q

_33−TCAD

⬘

␧

t

k

B

T

冊

,

共11兲

D

11

共␧

t

兲

D

₁₁

共0兲

= exp

冉

−

Q

_11−TCAD

⬘

␧

t

k

B

T

冊

.

共12兲

According to the work in Ref.

17

the total strain

␧

t

is the sum

of the three strain components:

␧

xx

in the channel length

direction,

␧

yy

in the channel width direction, and

␧

zz

in the

direction normal to the silicon surface. From the simulated

strain distributions,

␧

t

⬃␧

xx

, leading to Q

33−TCAD

⬘

⬇Q

33−uniax

⬘

and Q

_11−TCAD

⬘

⬇Q

_11−uniax

⬘

. The simulated saturation threshold

voltages for different values of Q

_33−uniax

⬘

and Q

_11−uniax

⬘

are

plotted in Fig.

1

for comparison. The figure clearly exhibits

that

共i兲 the largest deviation occurs at Q

_33−uniax

⬘

= 0 and

Q

_11−uniax

⬘

= 0, the case of no stress dependencies;

共ii兲 the most

accurate reproduction is achieved with the anisotropic

acti-vation energies, rather than the isotropic variety; and

共iii兲 the

anisotropy of the activation energy must be adequate, that is,

Q

_11−uniax

⬘

= −7 eV per unit strain and Q

_33−uniax

⬘

= −3.5 eV per

unit strain are more favorable than Q

_11−uniax

⬘

= −3.5 eV per

unit strain and Q

_33−uniax

⬘

= −7 eV per unit strain.

FIG. 1. Measured p-MOSFET saturation threshold voltage vs the spacing between the nearby trench isolation sidewalls in the channel length direc-tion. Also shown are those共lines兲 from the process-device coupled simula-tion with and without the strain induced activasimula-tion energies. The reason that the “no stress-dependent diffusion curve” is not entirely horizontal is due to dopant segregation near the edges of the source/drain regions. Specifically, the nonuniformity is caused by boron segregation occurring close to trench isolation oxide during the thermal process. Although the affected profile is not in vicinity of the MOSFET core region, a minor threshold voltage dif-ference共⬃3 mV兲 between large and small active areas can still be observed, even without the stress-dependent diffusion model.

161908-2 M.-J. Chen and Y.-M. Sheu Appl. Phys. Lett. 89, 161908共2006兲

Prior to determining the fundamental material

param-eters, a systematic treatment, such as that indicated in Fig.

2

,

is demanded. In Fig.

2

a series of straight lines of Q

_11−uniax

⬘

vs

Q

_33−uniax

⬘

are from Eqs.

共9兲

and

共10兲

for a literature

range

15,16,18

of V

˜ and the migration strain anisotropy A˜

共⬅共V˜

储

m

− V

˜

_⬜m

兲/⍀兲.

18

In the calculation procedure, the

follow-ing literature values were employed:

19

共i兲 C

11

= 168 GPa and

C

₁₂

= 65 GPa, giving rise to Y

_uniax

= 131 GPa and

␯

= 0.28;

共ii兲

⍀=2.26⫻10

−23

_cm

3

_{. The above experimental parameters}

are also added to the figure. From the figure a set of V

˜ and A˜

can be clearly located around the data point. On the other

hand, uncertainties exist based on a series of literature data:

V

˜ =−0.16±0.05 ⍀.

18

Taking such uncertainties into account,

Fig.

2

reveals that the data point does match the upper limit,

that is, V

˜ =−0.21 ⍀. The corresponding V˜

储m

− V

˜

⬜m

in the

vicin-ity of 0.15

⍀ is determined accordingly, falling within the

reasonable range.

15,16,18

Such corroborating experimental

evidence further indicates that the transient enhanced

diffu-sion effect is relatively insignificant when compared to the

long-term diffusion times in the underlying manufacturing

process. Under such circumstances, the point defect is

rap-idly equilibrated relative to the entire diffusion time.

Finally, we quoted the existing ab initio calculations:

12,13

Q

_11−biax

⬘

= −19.2 eV per unit strain and Q

_33−biax

⬘

= −13.9 eV per

unit strain, which were transformed via the aforementioned

relationship into the equivalent Q

_11−uniax

⬘

of −8.77 eV per unit

strain and Q

_33−uniax

⬘

of −4.975 eV per unit strain. In this

pro-cess, the Y

biax

used was equal to 183 GPa according to

Y

biax

=

共C

11

+ C

12

−

␯

C

12

兲 with its Poisson’s ratio

␯

= 2C

12

/ C

11

.

Evidently, the two data points are quite comparable to each

other, as displayed in Fig.

2

.

A physical model dealing with anisotropic diffusion in

uniaxially stressed silicon is derived and is quantitatively

connected to the biaxial case. A process-device coupled

simulation is performed on a p-type MOSFET undergoing

uniaxial stress during the manufacturing process. A

system-atic treatment is conducted and the resulting fundamental

material parameters are in satisfactory agreement with

litera-ture values.

This research is supported by the National Science

Council of Taiwan under Contract No.

NSC94-2215-E-009-005.

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FIG. 2. Uniaxial strain induced activation energy in the applied stress di-rection共parallel to the silicon surface兲 vs that normal to the silicon surface. The lines are from Eqs.共9兲and共10兲for a literature range共Refs.15,16, and

18兲 of the activation volume and the migration strain anisotropy. Also

plot-ted are the data points from the underlying experiment and the existing ab initio calculations共Refs.12and13兲.

161908-3 M.-J. Chen and Y.-M. Sheu Appl. Phys. Lett. 89, 161908共2006兲