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Performance Evaluation of InGaSb/AlSb P-Channel High-Hole-Mobility Transistor Faricated
Using BCl3 Dry Etching
View the table of contents for this issue, or go to the journal homepage for more 2013 Jpn. J. Appl. Phys. 52 020203
(http://iopscience.iop.org/1347-4065/52/2R/020203)
Performance Evaluation of InGaSb/AlSb P-Channel High-Hole-Mobility Transistor
Faricated Using BCl
3Dry Etching
Chia-Hui Yu1, Heng-Tung Hsu2, Che-Yang Chiang2, Chien-I Kuo1, Yasuyuki Miyamoto3, and Edward Yi Chang1
1Department of Materials Science and Engineering, National Chiao-Tung University, Hsinchu, Taiwan 30010, R.O.C. 2Department of Communications Engineering, Yuan Ze University, Chungli, Taiwan 32003, R.O.C.
3Department of Physical Electrons, Tokyo Institute of Technology, Meguro, Tokyo 152-8552, Japan
Received November 9, 2012; accepted December 13, 2012; published online January 18, 2013
In this study, we present the fabrication and characterization of InGaSb/AlSb p-channel high-hole-mobility-transistor devices using inductively coupled plasma (ICP) etching with BCl3 gas. Devices fabricated by the dry etching technique show good DC and RF performances. Radio-frequency (RF) performance for devices with different source-to-drain spacing (LSD) and gate length (Lg) were investigated. The fabricated
80-nm-gate-length p-channel device with 2-m LSDexhibited a maximum drain current of 86.2 mA/mm with peak transconductance (gm) of 64.5 mS/mm.
The current gain cutoff frequency ( fT) was measured to be 15.8 GHz when the device was biased at VDS¼ 1:2 V and VGS¼ 0:4 V.
# 2013 The Japan Society of Applied Physics
T
he III–V compound semiconductor quantum-well field effect transistors (QWFET) have attracted more attention as a substitution of the Si channel for advanced high-speed and low-power logic applications owing to the well-known characteristics of high electron mobility, high peak velocity and low effective mass.1)With the success in the development of III–V n-channel QWETs for low-power and high-speed logic applications,2–4) the development of p-type counterpart becomes an important issue to complete the complementary circuit technology.5) For this purpose, the InxGa1xSb alloy system shows greatpotential since the GaSb and InSb materials have the highest bulk hole mobilities in III–V compounds. Besides, the significant valence band barrier for such alloy enables good quantum confinement.6,7) Application of the compressive strain to the InxGa1xSb layer has been demonstrated to enhance the hole mobility due to band splitting in Si and SiGe p-MOSFETs.8)
Hole mobility at room temperature up to 1200 cm2V1s1 through strained InxGa1xSb/AlSb quantum
well with optimum growth condition of epitaxial materials leading to good RF performance has been demonstrated.9) In this study, we investigate the effect of source-to-drain spacing (LSD) and gate length (Lg) on the RF performance
of the device. We observed an increase of 19% in the current-gain-cutoff-frequency ( fT) with fixed Lg when LSD
was reduced from 3 to 2m. On the other hand, with fixed LSD, 28% increase in fT was obtained when Lg was scaled
down from 200 to 80 nm. The 80-nm gate-length device with 2-m LSD exhibited a measured fT of 15.1 GHz when the
device was biased at VDS¼ 1:2 V and VGS¼ 0:4 V.
Figure 1 shows the epitaxial structure of the InGaSb p-channel QWFET. The InGaSb/Alsb heterostructure was grown on a semi-insulating 3-in. (001) GaAs substrate by solid-source molecular beam epitaxy (MBE). The AlSb/ Al0:7Ga0:3Sb composite buffer layer was used to accom-modate the lattice mismatch between substrate and channel layer. The biaxial compressive strain was formed by the AlSb/Al0:7Ga0:3Sb barrier layers. Modulation doping of 1 1012 is achieved using planar Be-doped layer on top
of the AlSb layer in order to increase the hole concentration. To enhance the hole mobility, the biaxial compressive strain provided by a lattice mismatch of approximately 1.8% between the AlSb/Al0:7Ga0:3Sb and the In0:4Ga0:6Sb channel
layer was applied. The In0:45Al0:55As and InAs layers were capped to prevent air exposure and provide a chemically stable surface layer. Hall measurements exhibited a hole carrier concentration of 1:42 1012cm2 and a hole mobility of 895 cm2V1s1.
For device fabrication, mesa isolation was carried out by inductively coupled plasma (ICP) process using BCl3 gas and the dry etching was stopped at Al0:7Ga0:3Sb buffer layer. Compared to Cl2-based gases, adoption of BCl3 gas in the dry etching process will lead to a well-controllable etching rate to obtain shallow mesa isolation. Detailed discussions can be found in our earlier work10)Pd/Pt/Au ohmic contacts were evaporated and subsequently annealed at 340C for 30 s in N2 ambient, resulting in a low contact resistance of 1.81 mm and a sheet resistance of 1371 /sq. The Ti/Pt/ Au metal-line gate was formed by E-beam lithography and lift-off techniques. Finally, a 100-nm-thick SiNxpassivation
layer was deposit by plasma-enhanced chemical vapor deposition (PECVD) to protect the devices.
Figure 2 shows the drain–source current (IDS) as a
function of drain–source voltage (VDS) with gate–source
Fig. 1. Epitaxial structure of the InGaSb/AlSb p-channel quantum-well field effect transistors.
Japanese Journal of Applied Physics 52 (2013) 020203
020203-1 # 2013 The Japan Society of Applied Physics RAPID COMMUNICATION http://dx.doi.org/10.7567/JJAP.52.020203
voltage (VGS) varied from1 to 1 V for the 80-nm-gate and
2 50-m2-width device. The device exhibits a maximum
drain current density of 86.2 mA/mm at a gate bias of1 V and a drain bias of 2 V. Figure 3 shows the DC trans-conductance (gm) as a function of gate bias at different VDS
for the same device. A peak gmof 64.5 mS/mm is observed,
which is about 8% higher than that of the 200-nm device. The subthreshold slope of the device at VDS ¼ 1:2 V was
extracted to be 106 mV/dec. The corresponding Schottky gate leakage as a function of gate bias for the same device is shown in Fig. 4.
The high-frequency performance of the device was char-acterized through S-parameter measurement over a frequen-cy range of 1 to 80 GHz using an HP 8510 XF vector net-work analyzer. Standard load–reflection–reflection–match (LRRM) calibration procedure was performed before meas-urement. The extrinsic current-gain cutoff frequency ( fT)
and maximum oscillation frequency ( fmax) were extracted
from measurement based on the usual 6 dB/octave slope. The 80-nm device with 2-m LSD exhibited fT and fmax
of 15.8 and 29.2 GHz at VDS¼ 1:2 V, respectively. These
results demonstrate the feasibility of BCl3 dry etching for shallow mesa formation in InGaSb p-channel QWFET fabrication.
fT and fmax as a function of drain voltage for the 200-nm
2 50-m2-width device with different source–drain
spac-ing is shown in Fig. 5. The gate was biased at peak gm
for all the cases. An increase of 19% in fT is observed when
LSD was reduced from 3 to 2m. Figure 6 shows the cases
for the 2 50-m2-width device with different gate length when LSD was fixed at 2m. We observe an increase of
28.3% in fT when the gate length was scaled from 200 to
80 nm. Apparently, gate-length scaling is much more effec-tive in boosting fT. Such increase is almost comparable to the
boost in fT due to the increase of hole mobility.1,8) From
Figs. 5 and 6, we also observe that the variation of fT with
respect to the drain bias is not as drastic as that of fmax.
In conclusion, we have successfully fabricated p-channel QWFET device and characterized its performance. The effect of different source–drain spacing and gate-length on the RF performance was investigated. It is concluded that gate-length scaling is more effective than reduction of Fig. 2. (Color online) Drain–source current (IDS) as a function of drain–
source voltage (VDS) with gate–source voltage (VGS) varied from1 to 1 V
for the 80-nm-gate and2 50-m2-width device.
Fig. 3. (Color online) The DC transconductance (gm) as a function of
gate bias at different VDSfor the 80-nm-gate and2 50-m2-width device.
Fig. 4. The Schottky gate leakage as a function of gate bias for the 80-nm-gate and2 50-m2-width device.
Fig. 5. (Color online) fTand fmaxas a function of drain voltage for the
200-nm2 50-m2-width device with different source–drain spacing.
C.-H. Yu et al. Jpn. J. Appl. Phys. 52 (2013) 020203
source–drain spacing. Further boost in the RF performance should be possible with device techniques such as T-shaped gate implementation, reduction of gate-to-channel distance and reduction of parasitics.
Acknowledgments The authors would like to acknowledge the assistance and support of the National Science Council, Taiwan, R.O.C., under the contract
NSC 101-2221-E-155-047. A part of this work was supported by MEXT Nanotechnology platform 12025014 (F-12-IT-0004). The authors would also like to thank National Nano Device Laboratories Taiwan for the assistance in RF measurement.
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Fig. 6. (Color online) fTand fmaxas a function of drain voltage for the
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C.-H. Yu et al. Jpn. J. Appl. Phys. 52 (2013) 020203
