Design of a CMOS phase to digital transducer for optical incremental sensors

Cheng-Ta

Chiang

_{, Kaun-Chun}

_Hsieh

_{, Yu-Chung}

_Huang

a_{DepartmentofElectricalEngineering,NationalChia-YiUniversity,Taiwan}

b_{MeasurementTechniquesLaboratory,NationalChiaoTungUniversity,HsinChu,Taiwan}

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Articlehistory:

Received31December2010 Receivedinrevisedform24May2011 Accepted24May2011

Available online 31 May 2011 Keywords:

Opticalincrementalsensors Interpolationcircuits ADC

PLL

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Inthispaper,aCMOSphasetodigitaltransducerforopticalincrementalsensorsisnewlyproposed.The proposedchipcaneasilyproducephaseshiftsofsignalsbyusingaresistorchain.Asetofcalibration circuitsforopticalincrementalsensorsisalsodesignedintheproposedchip.Anotherinnovationisthat theoutputsoftheproposedchiparedirectlydigitized;theycouldbeeasilysentoverawiderangeof transmissionmedia,suchasPSN,radio,optical,IR,ultrasonic,etc.Besides,itdoesnotalsoneedaROM componentorafastcounterasusedinthestructuresofADC-basedandPLL-basedinterpolations.Based uponthedeviceparametersof0.5␮m2P2MCMOStechnologywith5Vpowersupply,allthefunctions andperformanceoftheproposedCMOSphasetodigitaltransducerforopticalincrementalsensorsare successfullytestedandproventhroughmeasurements.TheareaoftheproposedchipincludingESDI/O padsis2010×1502␮m2_{.Theinterpolationfactoris5,10,and40.Theproposedchipissuitableforoptical}

incrementalsensors.

© 2011 Elsevier B.V. All rights reserved.

1. Introduction

The developments of precise measurement and positioning devices[1,2] havebeenusedontheprocess,testingequipment ofelectronicandsemiconductorindustry.Smallerlinewidthand morepreciseneedsarerequiredintonano-meterscale.Thus,the techniquesofimprovingtheaccuracyandresolution onprecise measurementsarestronglyrequired.

Exceptforthelaserinterferometer,themainpositioningand displacementdevicesarelinearencoders,whichhavethe charac-teristicsoflowercost.Amonglinearencoders,opticalencodersare popularinmodernelectronicandsemiconductorindustryduetoits characteristicofhigh-accuracy.Opticalencoders,whichconsistof opticalsensorsandcircuits,employthelightpassingthroughthe grating.Thus,theencodersgenerateperiodicquadraturesignals. Thephasesofthesequadraturesignalsarerelativetothe move-mentofthegrating.However,theaccuracyis stillrestrictedby opticalpropertiesandmechanicalassembly.Inordertoimprove theaccuracy andresolution of opticalencoders,a technique of interpolationis developed [3–10]. Itimprovestheresolution of opticalencoders bydoing thesubdivisionof thephases. Previ-ousmethod[3,4]utilizesaphase-lockedloop(PLL)toachievethe

夽 ThisworkwassupportedbytheNationalScienceCouncil,Taiwan,under con-tractsNSC-99-218-E-415-002.

∗ Correspondingauthor.Tel.:+88652717587;fax:+88652717558. E-mailaddresses:ctchiang@mail.ncyu.edu.tw,ctchiang23@yahoo.com.tw (C.-T.Chiang).

interpolation.However,theseachievementsshoulddesignan oscil-latortosynthesizefrequency.Thedesignofahigh-frequencyPLL, whichiswithprecisionlockedfrequencyandgoodlinearityofan oscillator,isratherdifficult.Anothermethod[5–8],whichusesan analog-to-digitalconverter(ADC),isusedtoperformthe interpo-lation.However,thisschemeneedsaROMcomponenttoperform thefunctionoflook-uptable.ThetechnologyandROMsizewill beanotherconsiderableissue.Besides,this schememayneeda higher systemclock.For example,previouswork[6]requires a clockfrequency of 30MHz. Hence,a technique, whichis based oncomparator-basedinterpolation[9,10],isproposed.However, Stephensetal.[9]andRiederetal.[10]needtouse4and3sine signalstogeneratesignalswithdifferentphases.Theprocessing circuitsarecomplicated.Anotherissueoftheinterpolationerror shouldalsobediscussed.Thephasedelayandfrequencyjitterof PLLproducetheinterpolationerrorofPLL-basedinterpolation.This errorisbasicallyrelatedtothecircuitstructureofPLL.The interpo-lationerrorofADC-basedinterpolationiscausedbytheresolution, responsetime, andaccuracyofADC.Althoughtheinterpolation errorcanbereducedbyusingahighresolutionADC,theresponse time also increases.Besides, theaccuracy is related tothe cir-cuitstructureof ADC.For example,nonlineareffectofADCisa problemontheADC-basedinterpolation.Theinterpolationerror ofcomparator-basedinterpolationcomesfromthefiniteDCgain andresponsetimeofcomparator.Theinterpolationerrorcanbe reducedbyincreasingthefiniteDCgainandspeedingupthe tran-sientresponse ofacomparator.ComparedwithADC-basedand PLL-basedinterpolations,theinterpolationerrorof comparator-basedinterpolationiseasilyreducedbydesigningonthecircuit

0924-4247/$–seefrontmatter © 2011 Elsevier B.V. All rights reserved. doi:10.1016/j.sna.2011.05.026

Fig.1. (a)Opticalabsolutesensorsand(b)opticalincrementalsensors.

structureofauniformcomparator.Differenttopreviousworks,an improvedmethod[11]ofcomparator-basedinterpolationis pro-posed.Theproposedchipcaneasilyproducephaseshiftsofsignals byusinga resistorchain.Asetofcalibrationcircuitsforoptical incrementalsensorsisalsodesignedintheproposedchip.Another innovationisthattheoutputsoftheproposedchiparedirectly digitized;theycouldbeeasilysentoverawiderangeof transmis-sionmedia,suchasPSN,radio,optical,IR,ultrasonic,etc.Besides, itdoesnotalsoneedaROMcomponentorafastcounterasusedin thestructuresofADC-basedandPLL-basedinterpolations.Relative tothiswork,adigital-to-phaseconverterisdiscussedin[12,13]. However,theyaremainlyresearchedonhigh-speedPLLor delay-lockedloop(DLL).Inthiswork,weproposeanimprovedmethod and openly demonstrate how to implement a phase to digital transducerforopticalincrementalsensors.Readerscanunderstand wholedesigntechniquesfromthiswork,andthisisthemain con-tributionofthiswork.

Inthis paper,aCMOSphasetodigital transducerforoptical incremental sensors is newly proposedand designed in CMOS 0.5␮m2P2Mprocesswith5Vpowersupply.Theareaofthe pro-posedchipincludingESDI/Opadsis2010×1502␮m2_.Thepower

consumptionis50mW.Theproposedchipissuitableforoptical incrementalsensors.

In Section 2, theoverview of optical incremental sensors is addressed.Section3discussessystemarchitectureandsimulation results.Section4demonstratesthemeasurements.Finally, conclu-sionsandfutureworksaredescribed.

2. Theoverviewofopticalincrementalsensors

Opticalsensorsusedintheopticalencoderscanbedistinguished intotwotypesasshowninFig.1.Oneisopticalabsolutesensorsand theotherisopticalincrementalsensors.Thedifferencebetween themis in thearrangementsofoptical grating.The distanceof opticalgratingofincrementaltypeisdesignedinequalspace.The outputsignals areperiodic signals. However,thearrangements ofabsolutetypearetotallydifferent.Theoutputsignalsjust cor-respondtoitsabsoluteposition.Thedesignofopticalgratingof incrementaltypeiseasierthanthatofabsolutetype.Inthispaper, theincrementaltypeischosenanditscorrespondingcircuitis pro-posed.However,duetocongenitalfeaturesofincrementaltype,

Fig.2. Opticalincrementalsensorsandtheproposedphasetodigitaltransducer.

measurement errors will be alwaysaccumulated. Thus, optical incrementalsensorsneedtoperformtheextracalibrationto elim-inatetheaccumulatederrors.Thecalibrationmethodistoadda designofreferencemask.AsshowninFig.2,whenaglassscaleand anindexplatehavearelativemovement,thelightingintensityof phototransistorswillbechanged.Theoutputsignalscanbeviewed aswaveswhicharesimilartosinesignalsasshowninFig.3.The outputcurrentsofopticalincrementalsensorsareIA,IB,andIR.IA

andIB arethemaininputsourcesoftheproposedchip.IR isthe

currentusedtocalibratetheaccumulatederrors.TheperiodofIA

andIBisequaltothewidthofanopticalgrating.Tocalculatethe

numbersoftheperiodistoobtainthedistanceofthemovement. Theresolutionofopticalincrementsensorsislimited bythe widthofanopticalgrating.Iftheresolutionneedstoincrease,the widthofanopticalgratingmustalsobeshortened.However,the techniquetomakethewidthbelessthan1␮misratherdifficult. Besides,theeffectsofdiffractionandnoisewillbeseriousproblems. Thisworkproposesanimprovedmethodtodo thesubdivision ofthephases.Byusingtheproposedmethod,resolutioncanbe increasedwithoutchangingthewidthofanopticalgrating.The specificationoftheopticalincrementalsensorcanbecapturedfrom [14].InSection4,theopticalincrementalsensorwillbeapplied andexperimentedontheproposedphasetodigitaltransducer.In thefollowingsections,allthediscussionsofsystemarchitecture, simulation,andmeasurementresultswillbediscussed.

3. Systemarchitectureandsimulationresults

The proposed CMOS phase to digital transducer for optical incrementalsensorsincludesa currenttovoltageconverterand interpolationcircuits.TheinterpolationcircuitsasshowninFig.4 implementaresistorchain,comparators,andthedigitalprocessing circuits.ThesignalsofVA,VA−,Zin,andVBareconnectedtothe

out-putsofthecurrenttovoltageconverter.ThesignalsofAout,Bout,are

thedigitizedoutputs.TheoutputsignalofZoutisusedtocalibrate

theaccumulatederrorsofopticalincrementalsensors.Thesignal ofAcomisthecommon-modevoltage.ThecurrentofIrefisthebias

currentofcomparators.ThesignalsofSel0andSel1candecidethe

interpolationfactorof5or10.ThesignalofEnisanenablesignal, whichcanturnonoroffthechip.

Fig.5 shows thebasicprinciple of theproposedphase-shift method.A resistor chain is built toimplement the phase-shift method.ThepulsesignalofVDistheoutputofacomparatorand

thesignalofVsisaphase-shiftsignalwithphase.Thephase

dif-ferenceofVAandVBis90◦.Accordingtothesuperpositiontheorem,

thevoltageofVscanbeobtainedas

Vs= R2 R1+R2 sin()+ R1 R1+R2 cos()=



Fig.3. IA,IB,andIRaretheoutputcurrentsofopticalincrementalsensors.Aout,Bout,Zoutaretheoutputsoftheproposedphasetodigitaltransducer.ThenumberofIFisthe

interpolationfactor.

Fig.4. Thecircuitdiagramoftheproposedinterpolationcircuits.

and cot= R2

R1

(2) whereistheshiftphase.By(2),whentheratioofR1 andR2is

chosen,theisattained.InFig.6,thesignalofVisacquiredby

usingaXORlogicgate.ThatmeansthattheVisgeneratedfrom

theXORlogicfunctionofVDSandVDA.Thefunctionofinterpolation

isimpliedinthesignalofV.Similarly,theproposedmethodcan

beextendedintotheinterpolationfactorofNasshowninFig.7. Thephasedifferenceofwithineachresistorisafixedphaseof .Byfollowing(1)and(2),eachresistorRMwithinaresistorchain

Fig.5. Thebasicprincipleoftheproposedphase-shiftmethod.

Fig.6.ThewaveformofV.

Fig.7. ThedivisionsofphaseswiththeinterpolationfactorN.Inthisexample,Nis 10.

Fig.8.SPICEsimulationsoftheproposedphase-shiftmethod.Theinterpolation factoris8.

Fig.9. ThecircuitdiagramofphaseshiftshowninFig.4. isderivedas RM=Rtotal×







isthetotalresistanceofaresistorchain.By(1)–(3),thephasescan beeasilydividedbyaresistorchain.Forexample,ifNis10andRtotal

is1M,10resistorsofR1toR10are137k,109k,92k,83k,

79k,79k,83k,92k,109k,and137k,respectively.As showninFig.8,eightphaseswithinaresistorchainaresuccessfully shifted.

Incircuitimplementation,Fig.9showsthecircuitdiagramof phaseshiftshowninFig.4.ThesignalsofV1toV19withdifferent

phasesaregeneratedandconnectedtotheinputsofcomparators. Fig.10demonstratesthecircuitdiagramofdigitalprocessing cir-cuitsshowninFig.4.ThesignalsofU0toU19aretheoutputsignals

ofcomparators.Theyareusedtoperformdigitalprocessing proce-duresthroughthecircuitsofinterpolationAandB,andthecircuit ofzaisAandB.ThecircuitdiagramofinterpolationAandBis dis-playedinFig.11.TheoutputsignalsofAout,Boutcanbeattained

byperformingXORlogicgate.ThecircuitdiagramofzaisAandB isbuiltbya3-inputANDlogicgate.Inthedesignofcomparators, noiseisalwaysaconsiderableproblem.Inordertodecrease erro-neousjudgements,comparatorsneedtohaveahysteresisvoltage. ThecircuitisdisplayedinFig.12,andthehysteresisisderivedas VSPH=Vin+−Vin−=_{gm ×}Iss (ˇ_(ˇB/ˇA)−1

B/ˇA)+1 forˇB≥ˇA (4)

Fig.10.ThecircuitdiagramofdigitalprocessingcircuitsshowninFig.4.

and

VSPL=−VSPH,ˇB=ˇ6=ˇ7,ˇA=ˇ5=ˇ8 (5)

wheregmisthetransconductanceoftheMOSFET,theparameter ofˇisdefinedasnCoxW/L,andVSPLandVSPHarehalfof

Fig.12. Circuitschematicofthecomparator.

Fig.13.SPICEsimulationsofthehysteresisofthecomparator.

Fig.15.SPICEsimulationsofthecurrenttovoltageconverter.

sisvoltage.Aftersimulations,thehysteresisis24mVasshown

inFig.13.Thedesignspecificationsofcomparatorsarelistedin Table1.Fig.14demonstratesthecircuitschematicofthecurrent tovoltageconverterconnectedtoopticalincrementalsensors.The currentsgeneratedbysensorsareI_±A,I_±B,andI_±R.Convertedby thecurrenttovoltageconverter,eachcorrespondingvoltagesof VA,VA−,andVB,areobtainedasshowninFig.15.

Finally,thewholecircuitsarebuiltandsimulated.Theoutput signalsofAout,Bout,andZoutundertheinterpolationfactorof10

and5aredemonstratedinFigs.16and17,respectively.As demon-strated,theseoutputsaresuccessfullyattained.Thetestofintegral nonlinearity(INL)anddifferentialnonlinearity(DNL)areverifiedin

Fig.16.SPICEsimulationsofAout,Bout,andZoutundertheinterpolationfactorof10.

Fig.18.Bothofthemarealllessthan1count,andindicatethatthe proposedchiphasagoodlinearity.Althoughtheinterpolation fac-torcanjustbechosen5or10,theoutputsundertheinterpolation factorof40canbeeasilyobtainedbyperformingtheXORlogic func-tionofAout(IF=10)andBout(IF=10).However,itisoptionalforuser

choice.Allthefunctionsandperformanceoftheproposedphaseto digitaltransducerforopticalincrementalsensorsaresuccessfully testedandproventhroughSPICEsimulations.

4. Measurementresults

Fig. 19 demonstrates the microphotograph of the proposed CMOSphasetodigitaltransducerforopticalincrementalsensors. Inthiswork,theCMOS0.5␮m2P2Mprocesswith5Vpower sup-plyischosenduetoitslowercosttofabricatethischip.Thechip areaincludingESDI/Opadsis2010×1502␮m2_.Thepower

con-sumptionis50mW.Themeasurementsetupisbuiltasshownin Fig.20.Alogicanalyzeristogeneratedigitalcodesfromtwosine signalsthathavethephasedifferenceof90◦.Undoubtedly,these twocodesalsohavethephasedifferenceof90◦.Thecurrentsof ±IAand±IBareobtainedfromadigitaltoanalogconverter(DAC)

andvoltagetocurrentconvertersmarkedasv2i.Thecurrentof±IR

canbeeasilygeneratedbyasignalgenerator.Fig.21demonstrates

Fig.18. TheINLandDNL.

Fig.19.ThemicrophotographoftheproposedCMOSphasetodigitaltransducerfor opticalincrementalsensorsis2010× 1502␮m2_{includingESDI/Opads.}

themeasurementresultsundertheinterpolationfactorof5and 10,respectively.Thesignalfrequencyis50kHz.Asshown,the out-putsignalsaresuccessfullyproven.ThetestoftheINLandDNLis displayedinFig.22.TheINLislessthan0.8countandDNLisless than0.5count.Althoughthevalueisslightlyincreased,itisstill

Fig.20.Themeasurementsetup.

Table2

SummaryonthecharacteristicsoftheproposedCMOSphasetodigitaltransducer foropticalincrementalsensors.

Technology 0.5␮mCMOS2P2M

Powersupply 5V

Interpolationfactor 5,10,40(optional) Signalamplitude ±0.2to±0.8V Signalbandwidth 50kHz Samplingfrequency Donotneed Powerconsumption 50mW Physicallayoutoftheproposedchip 2010×1502␮m2 Applicationfield Opticalincrementalsensors

Fig.21.Themeasurementresultsundertheinterpolationfactorof(a)5and(b)10. Thesignalfrequencyis50kHz.

Fig.22.TheINLandDNLofthemeasurementresultsundertheinterpolationfactor of10.Thesignalfrequencyis50kHz.

Fig.23.Themeasurementresults(a)Aout,(b)Aout,Boutand(c)Zoutoftheproposed chipoperatedwithopticalincrementalsensors.Thefrequencyofoptical incremen-talsensorsis1kHz.

Table3

Comparisonstopreviousjobs.

[4] [6] Thiswork

Technology 1.2␮mCMOS2P2M 0.5␮mCMOS2P2M

Interpolationmethodology PLL-based ADC-based Comparator-based

Samplingfrequency Donotneed(VCOisapplied) 30MHz Donotneed

Interpolationfactor 70 5,10,25,50 5,10,40(optional)

Outputformat Sinesignals Countercode Pulsestream

Calibrationmethod None None Provided

Chiparea N.A. 13mm2 _3mm2

Differentialnonlinearity N.A. <0.3counts <0.5counts

Integralnonlinearity N.A. <0.5counts <0.8counts

lessthan1count.Thatmeansthatthenon-linearityerrorisallless than9◦undertheinterpolationnumberof10.Theproposedchip canattainacharacteristicofgoodlinearity.

Finally,measurementresultsoftheproposedchipoperatedwith opticalincrementalsensorsareperformed.Thefrequencyof opti-calincremental sensorsis 1kHz. Theinterpolation factor is 10. InFig.23,theoutputsofAout,Bout,andZoutarealsosuccessfully

obtained.ThecharacteristicsoftheproposedCMOSphaseto dig-italtransducerforopticalincrementalsensorsaresummarizedin Table2.Thecharacteristicsoftheproposedchiparecomparedwith previousjobsandorganizedinTable3.

5. Conclusion

ACMOSphasetodigitaltransducerforopticalincremental sen-sorsisnewlyproposed. Thischipadoptsa proposedphase-shift method,whichcaneasilygeneratephaseshiftsofsignalsbyusing aresistorchain.Owingtothefactthattheoutputsoftheproposed chiparedirectlydigitized,itdoesnotneedaROMcomponentanda fastercounterasusedinthestructuresofADC-basedandPLL-based interpolations.Theoutputsignalscouldbealsoeasilysentovera widerangeoftransmissionmedia,suchasPSN,radio,optical,IR, ultrasonic,etc.Allthefunctionsandperformanceoftheproposed CMOSphasetodigitaltransducerforopticalincrementalsensors aresuccessfullytestedandproventhroughmeasurements.Inthe future,thedevelopedtechniqueswillbeadaptivelydesignedinto opticaldevices,suchasopticalencoders.

Acknowledgements

TheauthorsacknowledgeCenterforMeasurementStandardsof IndustrialTechnologyResearchInstitutefortheirsupportinoptical incrementalsensorsandalsoacknowledgeMs.AliceKao,Mr. Yu-YuanChenofCenterforMeasurementStandardsfortheirtechnical supportinmeasurementtesting.

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Biographies

Cheng-TaChiang(S’00-M’05)wasborninTaiwan,R.O.C.,in1977.Hereceivedthe B.S.degreeinelectronicsengineeringfromChungYuanChristianUniversity,Jhongli, Taiwan,in1999,theM.S.degreeinbiomedicalengineeringfromtheNationalCheng KungUniversity,Tainan,Taiwan,in2001,andthePh.D.degreeinelectronics engi-neeringfromtheNationalChiaoTungUniversity,Hsinchu,Taiwan,in2006.

HewasavisitingscholarwiththeDepartmentofElectricalandComputer Engi-neering,TheJohnsHopkinsUniversity,Baltimore,MD,fromOctober1,2004until November30,2005.HewasincludedinMarquisWho’sWhoinScienceand Engi-neering2006–2007andMarquisWho’sWhointheWorld2008.Since2007,hewasa reviewcommitteememberoftheNationalChipImplementationCenter,Hsinchu. From2006to2010,hewasamemberoftechnicalstaffatIndustrialTechnology ResearchInstitute,Hsinchu,andwasresponsibleforNyquist&OversampledA/D converters,andMEMScircuits.Since2010,hewaswithNationalChiaYiUniversity, Chiayi,Taiwan,andservicedasanassistantprofessorintheDepartmentofElectrical Engineering.Hismainresearchinterestsincludeanalogintegratedcircuits, biomed-icalelectronics,imagesensorcircuitsandsystems,sensorsignalconditioningand transducers,NyquistA/Dconverters,andhigh-resolutiondelta-sigmamodulator.

Dr.ChiangisaconferencereviewerforIEEEconferencesofI2_{MTC2008,ISIEA}

2009–2011,PECON2010,IAPEC2011,ICEDSA2011,ICBEIA2011,PEOCO2011,CSNT 2011,andajournalreviewerfortheIEEETransactionsonInstrumentationand Mea-surement,IEEEIndustrialElectronics,IEEESensorsJournal,MicroelectronicsJournal, EURASIPJournalonAdvancedinSignalProcessing,andaneditorialadvisoryboard memberfortheSensors&TransducersJournal.

Kaun-ChunHsiehwasborninTaiwan,R.O.C.,in1976.HereceivedtheB.S.degreein electricalengineeringfromNationalTaiwanUniversityandtheM.S.degreein elec-tronicsengineeringfromNationalChiaoTungUniversity,Taiwan,R.O.C.,in1998and 2001,respectively.HecurrentlyservicesinGlobalUnichipCorporation,Hsinchu, Taiwan,R.O.C.

Hismainresearchinterestshavebeeninanalogintegratedcircuits,andIP ser-vices.

Yu-ChungHuangreceivedtheM.S.degreeinelectricalengineeringandPh.D.degree inprocessengineeringfromtheTechnologyUniversityofBerlin,Berlin,Germany, in1982and1985,respectively.

Since1985,hehasbeenaProfessorintheDepartmentofElectronics,National ChiaoTungUniversity,Hsinchu,Taiwan,R.O.C.Hisresearchinterestsaresensors andmeasuringtechnologies.

Prof.HuangisamemberoftheCommitteeoftheChineseMetrologySocietyand amemberoftheMicromechanicalScienceInstitute,R.O.C.