902 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 10, OCTOBER 2007
High-Performance and
Low-Temperature-Compatible p-Channel
Polycrystalline-Silicon TFTs Using
Hafnium-Silicate Gate Dielectric
Ming-Jui Yang, Chao-Hsin Chien, Associate Member, IEEE, Yi-Hsien Lu, Guang-Li Luo,
Su-Ching Chiu, Chun-Che Lou, and Tiao-Yuan Huang, Fellow, IEEE
Abstract—In this letter, high-performance p-channel polycrystalline-silicon thin-film transistors (TFTs) using hafnium-silicate (HfSiOx) gate dielectric are demonstrated with
low-temperature processing. Because of the higher gate-capacitance density, TFTs with HfSiOxgate dielectric exhibit excellent device
performance in terms of higher ION/IOFFcurrent ratio, lower
subthreshold swing, and lower threshold voltage (Vth) albeit with
slightly higherOFF-state current. More importantly, the mobility of TFTs with HfSiOxgate dielectric is 1.7 times that of TFTs with
conventional deposited-SiO2gate dielectric.
Index Terms—Hafnium silicate (HfSiOx), high dielectric
constant (high-κ), polycrystalline-silicon thin-film transistors (poly-Si TFTs).
I. INTRODUCTION
P
OLYCRYSTALLINE-SILICON thin-film transistors (poly-Si TFTs) have been widely used in active-matrix liquid-crystal display because of their superior performance [1]. Recently, the feasibility of integrating the entire system on the panel is being actively pursued [2]. For this goal, the display-driving circuits require high-performance TFTs capable of operating at lower voltages while delivering higher drive currents. Although thinning down the gate oxide can increase the drive current of TFTs, it results in higher gate leakage current [3]. In order to preserve the physical dielectric thickness while increasing the gate capacitance, several new high-κ materials, including Al2O3, Ta2O5, and HfO2, were proposed [4]–[6]. Among them, the κ value of Al2O3 films isManuscript received May 17, 2007; revised July 9, 2007. This work was supported in part by the National Science Council, Taipei, Taiwan, R.O.C., under Contract 95221E009313. The review of this letter was arranged by Editor J. Sin.
M.-J. Yang and C.-H. Chien are with the Department of Electronics Engi-neering and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. They are also with the National Nano Device Laboratory, Hsinchu 300, Taiwan, R.O.C. (e-mail: [email protected]).
Y.-H. Lu and T.-Y. Huang are with the Department of Electronics Engineer-ing and Institute of Electronics, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C.
G.-L. Luo is with the National Nano Device Laboratory, Hsinchu 300, Taiwan, R.O.C.
S.-C. Chiu and C.-C. Lou are with the MSSCORPS Company, Ltd., Hsinchu 30072, Taiwan, R.O.C.
Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/LED.2007.904901
only∼7; therefore, its improvement is not sufficient [7]. On the other hand, due to its narrow band gap, a thicker Ta2O5 film is necessary to reduce the gate leakage current of TFTs [8], thus limiting the gate-capacitance increase. Recently, hafnium dioxide (HfO2) was also applied to TFTs due to its high-κ value (14–20) and wide band gap. Even though poly-Si TFTs using HfO2 gate dielectric show better performance in many aspects, the higher gate leakage current due to poly-crystalline HfO2films and the degraded mobility arising from additional scattering remain to be resolved [6]. In this letter, we studied HfSiOx as the gate dielectric for p-channel poly-Si TFTs,
and we found that the transistors exhibit higher ION/IOFF current ratio, smaller subthreshold swing (SS), lower Vth, and higher mobility over those with conventional deposited-SiO2 dielectric.
II. DEVICEFABRICATION
First, 550-nm-thick thermal oxide was grown on Si wafers in furnace to simulate the glass substrate. Then, a 100-nm-thick amorphous-silicon layer was deposited by the dissociation of SiH4gas in a low-pressure chemical vapor deposition (LPCVD) system at 550 ◦C. Subsequently, solid-phase crystallization was performed at 600 ◦C for 24 h in N2 ambient to induce the recrystallization of amorphous silicon. Individual active regions were then patterned and defined. After cleaning, dif-ferent gate dielectrics, all of which were 60 nm in thickness, were deposited. Specifically, both HfO2and HfSiOxfilms were
deposited by atomic vapor deposition using an AIXTRON Tricent system at a substrate temperature of 500 ◦C. The conventional oxide was prepared by LPCVD with tetra-ethyl-oxy-silane precursor at 700 ◦C to serve as the control sam-ple. Afterward, all wafers received a 300-nm-thick amorphous silicon deposition by LPCVD at 550 ◦C to serve as the gate electrode. The gate electrodes were patterned, and the source, drain, and gate regions were doped by a self-aligned boron-ion implantation at a dosage and an energy of 5× 1015ions/cm−2 and 15 keV, respectively. After source/drain formation, dopant activation was executed at 600 ◦C for 24 h in N2 ambient. Finally, metallization and sintering were performed to com-plete the fabrication. For the device measurements, a Keithley 4200 semiconductor characterization system, an HP 4156A
YANG et al.: POLYCRYSTALLINE-SILICON TFTs USING HAFNIUM-SILICATE GATE DIELECTRIC 903
Fig. 1. Cross-sectional TEM pictures of TFTs using (a) HfO2, (b) HfSiOx, and (c) deposited-SiO2gate dielectrics.
precision semiconductor parameter analyzer, and an Agilent 4284A precision LCR meter were used. The field-effect mobil-ity, which was extracted from the maximum transconductance (Gm), and the SS were measured at Vds=−0.1 V. The thresh-old voltage was defined as the gate voltage at which the drain current reached a normalized drain current of Ids= (W/L)× 10−8A at Vds =−0.1 V. TFTs with W/L = 5 µm/10 µm were measured, where W is the drawn channel width, and L is the drawn channel length.
III. RESULTS ANDDISCUSSION
Fig. 1 shows the cross-sectional transmission electron mi-croscopy (TEM) images of the HfO2, HfSiOx, and
deposited-SiO2 films with physical thicknesses of 57, 53, and 61 nm, respectively. The interfacial layers formed between the HfO2/Si and HfSiOx/Si surfaces are about 3 nm. It can be
seen that the HfSiOxfilm depicts amorphous structure, contrary
to the polycrystalline structure seen in HfO2 film, which is conducive to a smoother surface at both the top and the bottom interfaces. This result is consistent with our X-ray-diffraction spectroscopy data (not shown).
Fig. 2 shows transfer characteristics of TFTs with HfSiOx
and SiO2 at Vds=−0.1 and −2 V. The measured data and the extracted device parameters are summarized in Table I. Obviously, TFTs with high-κ dielectrics depict much better per-formance than TFTs with conventional deposited SiO2 except for theOFF-state leakage current. In addition to the better gate dielectrics/poly-Si interface quality [5], the thinner equivalent oxide thickness with the same physical thickness of high-κ di-electrics could explain the lower Vthand significantly improved SS [9], [10]. Previously, the authors had reported that the Vth and SS factors are sensitive to the density of deep states near the midgap [11]. As the density of states decreases, Vth and
Fig. 2. Transfer characteristics of TFTs using HfSiOxor deposited SiO2as gate dielectric.
TABLE I
SUMMARY OFDEVICEPARAMETERS OFTFTs USINGDIFFERENTGATE
DIELECTRICS ATVds=−0.1 V
SS decrease. Fig. 3 shows the plots of density of states versus
E−Efb of poly-Si TFTs with different gate dielectrics. These results are extracted from the transfer characteristics that were measured at 25◦C, 50◦C, 75◦C, 100◦C, and 125◦C [12]. It can be seen that high-κ dielectrics show lower density-of-state values. Even though the SS and the ION/IOFFcurrent ratio of TFTs with HfSiOxare slightly worse than those of TFTs with
HfO2, we believe that HfSiOxis still more suitable than HfO2 for the gate dielectric of future poly-Si TFTs. The reasons are as follows. First, HfSiOxhas smaller leakage current and larger
breakdown field than HfO2 due to the amorphous nature of HfSiOxafter processing. In particular, the value of gate leakage
current density decreases from 7.60E-8 to 4.70E-9 A/cm2 at
Vgs=−10 V, and the breakdown field increases from −4 to
−7 MV/cm (data not shown) for HfSiOxcompared with HfO2. Second, TFTs with HfSiOx show 0.73 times improvement in
hole mobility, over the conventional TFTs using deposited-SiO2 dielectric, rather than degraded mobility for the case of TFTs with HfO2. According to the previous reports [13]–[15], we speculated that the degraded mobility of TFTs with HfO2 dielectric was due to the additional Coulomb scattering caused by the charges in the HfO2dielectric.
In order to further clarify the mechanism ofOFF-state current, the activation energies of the different gate dielectrics were calculated from the Id− Vgscurves obtained at 25◦C, 50◦C, 75◦C, 100◦C, and 125◦C. The dependence of activation energy on Vgs with Vds =−0.1 V is shown in Fig. 4. It can be seen that TFTs with HfO2have the lowest minimum leakage current due to their highest activation energy. However, with increasing
|Vgs| in theOFF-state regime, the activation energy of TFTs with HfO2decreases drastically which causes theOFF-state current to increase rapidly. Although TFTs with HfSiOxshow slightly
904 IEEE ELECTRON DEVICE LETTERS, VOL. 28, NO. 10, OCTOBER 2007
Fig. 3. Density of states extracted from transfer characteristics (Vds=
−0.1 V) of poly-Si TFTs using different gate dielectrics.
Fig. 4. Channel activation energy obtained from temperature dependence of transfer characteristics (Vds=−0.1 V) of poly-Si TFTs using different gate dielectrics.
higher minimum leakage current than TFTs with HfO2, the
OFF-state current can be improved due to the slowly decreasing activation energy of TFTs with HfSiOx. Regarding the leakage
mechanism of poly-Si TFTs [16]–[19], theOFF-state current, which is related to Frenkel–Poole emission mechanism, is strongly dependent on the peak electric field Epk at the drain junction and is dominated by the vertical electric field at the interface, then IFE∝ exp Epk Epk= (Vgs− Vds− Vfb)εgate dielectric (Tgate dielectricεSi)
where εSi and εgate dielectric are the permittivities of Si and gate dielectric, respectively, Vfb is the flat-band voltage, and
Tgate dielectric is the physical thickness of the gate dielectric. Poly-Si TFTs using high dielectric-constant gate dielectric will exhibit higher peak electric filed, causing a rapidly increasing
OFF-state current.
IV. CONCLUSION
In this letter, high-performance p-channel poly-Si TFTs using hafnium-silicate gate dielectric are demonstrated using low-temperature processing. Higher ION/IOFF current ratio, smaller SS, lower threshold voltage, and higher mobility than those with conventional deposited-SiO2 gate dielectric are achieved. Our results suggest that HfSiOxis a potential
candi-date for the gate-dielectric material of future high-performance poly-Si TFTs.
ACKNOWLEDGMENT
The authors would like to thank M.-H. Lee and Dr. H.-C. Lin for the support of computer software.
REFERENCES
[1] H. Oshima and S. Morozumi, “Future trends for TFT integrated circuits on glass substrates,” in IEDM Tech. Dig., 1989, pp. 157–160.
[2] K. Werner, “The flowering of flat displays,” IEEE Spectr., vol. 34, no. 5, pp. 40–49, May 1997.
[3] A. Takami, A. Ishida, J. Tsutsumi, T. Nishibe, and N. Ibaraki, “Threshold voltage shift under the gate bias stress in low-temperature poly-silicon TFT with the thin gate oxide film,” in Proc. Int. Workshop AM-LCD, Tokyo, Japan, Jul. 2000, pp. 45–48.
[4] M. Y. Um, S.-K. Lee, and H. J. Kim, “Characterization of thin film transistor using Ta2O5gate dielectric,” in Proc. Int. Workshop AM-LCD, Tokyo, Japan, Jul. 1998, pp. 45–46.
[5] Z. Jin, H. S. Kwok, and M. Wong, “High-performance polycrystalline SiGe thin-film transistors using Al2O3gate insulators,” IEEE Electron
Device Lett., vol. 19, no. 12, pp. 502–504, Dec. 1998.
[6] C.-P. Lin, B.-Y. Tsui, M.-J. Yang, R.-H. Huang, and C.-H. Chien, “High-performance poly-silicon TFTs using HfO2gate dielectric,” IEEE
Elec-tron Device Lett., vol. 27, no. 5, pp. 360–363, May 2006.
[7] B. W. Busch, O. Pluchery, Y. J. Chabal, D. A. Muller, R. L. Opila, J. R. Kwo, and E. Garfunkel, “Materials characterization of alter-native gate dielectrics,” MRS Bull., vol. 27, no. 3, pp. 206–211, Mar. 2002.
[8] H. S. P. Wong, “Beyond the conventional transistor,” IBM J. Res.
Develop., vol. 46, no. 2/3, pp. 133–168, Mar.–May 2002.
[9] B. F. Hung, K. C. Chiang, C. C. Huang, A. Chin, and S. P. McAlister, “High-performance poly-silicon TFTs incorporating LaAlO3as the gate dielectric,” IEEE Electron Device Lett., vol. 26, no. 6, pp. 384–386, Jun. 2005.
[10] K. H. Lee, J. K. Park, and J. Jang, “A high-performance polycrystalline silicon thin film transistor with silicon nitride gate insulator,” IEEE Trans.
Electron Devices, vol. 45, no. 12, pp. 2548–2551, Dec. 1998.
[11] I.-W. Wu, T. Y. Huang, W. B. Jackson, A. G. Lewis, and A. Chiang, “Passivation kinetics of two types of defects in polysilicon TFT by plasma hydrogenation,” IEEE Electron Device Lett., vol. 12, no. 4, pp. 181–183, Apr. 1991.
[12] H.-C. Lin, K.-L. Yeh, M.-H. Lee, Y.-C. Su, T.-Y. Huang, S.-W. Shen, and H.-Y. Lin, “A novel methodology for extracting effective density-of-states in poly-Si thin-film transistors,” in IEDM Tech. Dig., 2004, pp. 781–784.
[13] T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, “Additional scattering effects for mobility degradation in Hf-silicate gate MISFETs,” in IEDM Tech. Dig., 2002, pp. 621–624. [14] P. D. Kirsch, M. A. Quevedo-Lopez, H.-J. Li, Y. Senzaki, J. J. Peterson,
S. C. Song, S. A. Krishnan, N. Moumen, J. Barnett, G. Bersuker, P. Y. Hung, and B. H. Lee, “Nucleation and growth study of atomic layer deposited HfO2gate dielectrics resulting in improved scaling and electron mobility,” J. Appl. Phys., vol. 99, no. 2, p. 023 508, Jan. 15, 2006. [15] A. Morioka, H. Watanabe, and T. Mogami et al., “High mobility MISFET
with low trapped charge in HfSiO films,” in VLSI Symp. Tech. Dig., 2003, pp. 165–166.
[16] C. F. Yeh, S. S. Lin, T. Z. Yang, C. L. Chen, and Y. C. Yang, “Perfor-mance and off-state current mechanisms of low-temperature processed polysilicon thin-film transistors with liquid phase deposited SiO2 gate insulator,” IEEE Trans. Electron Devices, vol. 41, no. 2, pp. 173–179, Feb. 1994.
[17] C. T. Angelis, C. A. Dimitriadis, I. Samaras, J. Brini, G. Kamarinos, V. K. Gueorguiev, and T. E. Ivanov, “Study of leakage current in n-channel and p-channel polycrystalline silicon thin-film transistors by conduction and low frequency noise measurements,” J. Appl. Phys., vol. 82, no. 8, pp. 4095–4101, Oct. 15, 1997.
[18] M. Hack, I.-W. Wu, T. J. King, and A. G. Lewis, “Analysis of leakage currents in poly-silicon thin film transistors,” in IEDM Tech. Dig., 1993, pp. 385–388.
[19] M. Yazaki, S. Takenaka, and H. Ohshima, “Conduction mechanism of leakage current observed in metal-oxide-semiconductor transistors and poly-Si thin-film transistors,” Jpn. J. Appl. Phys., vol. 31, no. 2A, pp. 206–209, Feb. 1992.
