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Printed circuit board production planning using Physical programming approach 姜平、陳偉星

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Printed circuit board production planning using Physical programming approach 姜平、陳偉星

E-mail: 9315366@mail.dyu.edu.tw

ABSTRACT

Most of the previous research about printed circuit board (PCB) assembly had focused on machine-level optimization problems, such as placement sequence and feeder assignment. Less research effort was devoted to middle to short period production planning problems simultaneously. On the basis of goal-oriented strategies, this thesis studied the PCB production planning from Master Production Scheduling (MPS) to Finally Assembly Scheduling (FAS). The goal strategies in MPS were based two types of cost reductions that included production and holding cost. MPS is therefore a multiple criteria optimization problem. This thesis applied physical programming approach to solve this MPS problem. The solution from MPS was fed into the second layer problem to obtain final assembly sequence. The second layer (FAS) problem is a NP hard problem. In this research, GA was chosen to solve FAS problem. We compared solutions obtained from GA approach and the mathematical model in term of solution quality and efficiency.

Keywords : Printed circuit board assembly ; Master Production Schedule ; Finally Assembly Schedule ; Physical programming ; Genetic algorithm

Table of Contents

封面內頁 簽名頁 授權書 iii 中文摘要 iv ABSTRACT v 誌謝 vi 目錄 vii 圖目錄 x 表目錄 xii 第一章 緒論 1 1.1 研究背景與動機 1 1.2 研究目的 3 1.3 問題描述與假設 4 1.4 研究流程 7 第二章 文獻探討及相關理論 8 2.1 印刷電路板相關文獻 8 2.2 生產系 統相關文獻 9 2.3 研究相關理論 10 2.3.1 多目標規劃 10 2.3.2 排程問題 13 2.3.3 基因演算法(Genetic Algorithm; GA) 16 第三章 研究方法 17 3.1 實體規劃方法 18 3.1.1 決策者準則偏好決定 19 3.1.2 準則的分類 20 3.1.3 Class Function的結構 21 3.1.4 LLPW Algorithm 及實體規劃數學模型 24 3.2 主生產排程導入實體規劃 25 3.3 最終組裝排程問題 27 3.4 最終組裝排程數學 模型 28 3.5 基因演算法 30 3.5.1染色體編碼 33 3.5.2染色體複製 33 3.5.3染色體交配 34 3.5.4染色體突變 35 3.5.5適合度函數 35 第四章 實驗結果與分析 37 4.1主生產排程之實體規劃結果分析 37 4.1.1 求解最小化組裝成本及最小化持有成本之結果 40 4.1.2 求解實體規劃及目標規劃之結果 41 4.2 最終組裝排程問題結果分析 48 4.2.1 基因演算法世代長度之分析 49 4.2.2 基因 演算法之族群大小、交配率、突變率之ANOVA分析 50 4.2.3 最佳化方法與基因演算法求解比較 55 第五章 結論與建議 58 5.1 結論 58 5.2 建議 58 參考文獻 60

REFERENCES

1. 李文瑞、陳秋宏,產業群聚與競爭優勢-我國印刷電路板產業發展與競爭力之分析,經濟部經濟情勢暨評論季刊第三卷第四期(1998)。

2. 黃振倫,印刷電路板小元件裝配排程問題-以Fuji CP機器為例,元智大學工業工程與管理研究所碩士論文(2002)。 3. 林家嘉,PCB插件 整合最佳化問題解算法之研究-以CNC機器為例,元智大學工業工程與管理研究所碩士論文(2003)。 4. Adan, I. J. B. F. & Van der Wal, J.,

“Combining make to order and make to stock”, OR Spektrum, 1998 pp. 73-81. 5. Bemelmans, R. P. H. G. “The capacity-aspect of Inventories

”, Springer Verlag, Heidelberg, 1986. 6. Current, J., Min, H. and Schilling, D., “Multiobjective Analysis of Facility Location Decisions”, European Journal of Operational Research, 1990, pp. 295-307. 7. Cornelis Klomp, Joris van de Klundert, Frits C.R. Spieksma, Siem Voogt,

“The feeder rack assignment problem in PCB assembly:A case study”, Int. J. Production Economics, 2000, pp. 399-407. 8. Federgruen, A. &

Katalan, Z., “Impact of adding a make-to-order item to a make-to-stock production system”, Management Science, 1999, pp. 980-994. 9.

Holland, J. H., “Adaptation in Nature and Artfifical Systems”, University if Michigan Pres, Ann Arbor, 1975. 10. Hwand, C. L. and Yoon, K.,

“ Multiple Attribute Decision Making: Methods and Applications,” Springer-Verlag, New York, 1981. 11. Katharine R. Haberle, Robert J.

Graves, “Cycle Time Estimation for Printed Circuit Board Assemblies”, IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2001. 12. Kimberly P. Ellis, Fernando J. Vittes, John Kobza, “Optimizing the Performance of a Surface Mount Placement Machine”, IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2001. 13. Kimberly P. Ellis, Fernando J. Vittes, John Kozba, “Development of a placement time estimator function for a turret style surface mount placement machine”, Robotics and Computer Integrated Manufactoring, 2002, pp. 241-254. 14. Kimberly P. Ellis, Leon f. McGinnis, Jane C. Ammons, “An approach for grouping circuit cards into families to minimize assembly time on a placement machine”, IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2003. 15. L.P. Khoo, T.K. Ng, “A genetic algorithm-based planning system for PCB component

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placement”, Int. J. Production Economics, 1998, pp. 321-332. 16. Leanne K. Moyer, Surendra M. Gupta, “SMT feeder slot assignment for predetermined component placement paths”, Journal of Electronics Manufacturing, 1996, pp. 173-192 17. Mark S. Hillier, Margaret L.

Brandeau, “Optimal component assignment and board grouping in printed circuit board manufacturing”, Operation Research, 1998. 18. Mark S. Hillier, Margaret L. Brandeau, “Cost minimization and workload balancing in printed circuit board assembly”, IIE Transactions, 2001, pp.

547-557. 19. Messac, A., Gupta, S. M., and Akbulut, B. ”Linear Physical Programming: A NewApproach to Multiple Objective Optimization”, Transactions on Operational Research, 1996, pp.39-59. 20. Messac, A., Batayneh, W. M., and Ismail-Yahaya, A.”Production Planning

Optimization with Physical Programming”, Engineering Optimization, Taylor and Francis Publisher, 2002, pp. 323-340. 21. Maria, A., Mattson, C. A., Ismail-Yahaya, A., and Messac, A. ”Linear Physical Programming for Production Planning Optimization”, Engineering Optimization, 2003, pp. 19-37. 22. P. Ji, M.T. Sze, W.B. Lee, “A genetic algorithm of determining cycle time for printed circuit board assembly lines”, European Journal of Operational Research, 2001, pp. 175-184. 23. Teck Sang Loh,Satish T.S. Bukkapatnam, Deborah Medeiros, Hongkyu Kwon, “A genetic algorithm for sequential part assignment for PCB assembly”, Computers & Industrial Eigineering, 2001, pp. 293-307. 24.

Williams, T. M., “Special products and uncertainty in production/inventory system”, Eurpean Journal of Operation Research, 1984, pp. 46-54.

25. Yves Crama, Olaf E. Flippo, Joris van de Klundert, Frits C.R. Spieksma, “The assembly of printed circuit boards:A case with multiple machines and multiple board types”, European Journal of Operational Research, 1998, pp. 457-472. 26. Yves Crama, Joris van de Klundert, Frits C.R. Spieksma, “Production planning problems in printed circuit board assembly”, working paper, 1999. 27. YU-AN LI, SABAH

RANDHAWA, “Component to multi-track feeder assignment and board sequencing in printed circuit board assembly”, Journal of Manufacturing, 2002, pp. 51-68.

參考文獻

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