Index Terms— Correlator, delay-lockedloop, direct sequence spreadspectrum, tracking error variance.
I. S YSTEM D ESCRIPTION AND S IGNAL M ODEL
I N THIS letter, we present a code tracking receiver with less complexity, by employing adifferentiallycoherent tech- nique originally proposed for pseudonoise (PN) acquisition receiver . The proposed differentiallycoherentdelay-lockedloop (DCDLL) scheme is shown in Fig. 1. The received signal is first filtered by front-end band-pass filter (BPF) and the bandwidth of BPF is . is set to be chip rate ( , where is the chip duration). Then this proposed DCDLL scheme processes the received signal using a differential decoder with adelay of -chip duration in the delay path. The decoder output is then correlated with the difference of the advanced (early) and retarded (late) versions of the local PN code to produce an error signal. After the error signal is filtered by a low-pass filter (LPF), then it drives the voltage-controlled clock (VCC) through the loop filter and corrects the code phase error of the local PN code generator. In this proposed system, the bandwidth of LPF, denoted as , is set to be the system data rate ( , where is the data bit duration). The processing gain of this direct-sequence spread-spectrum (DS/SS) system is thus given by or . Usually, if the system is applied in ranging, and
4.3 Quad-phase clock generator
A time-interleaving ADC requires a multiphase clock generator to individually provide clocks for sub-ADCs. The variation between the sub-ADC clocks can cause distortion of output digital signals. So the delays of the clocks are critical. In our 65 nm and 45 nm CMOS ADCs, the number of sub-ADC is four, and thus, we design a quad-phase clock generator. Figure 5 shows the blocks of the clock generator, which includes, a phase-frequency detector, a charge pump, aloop filter/integrator and a voltage-control delay line (VCDL). The generator is basically adelay lock loop. The input signal is 5 GHz clock and the output quad-phase clocks will be locked at the same phase. So the total delay time of the VCDL is a period, 0.2 ns. VCDL contains four stages that generate four phase clocks. The phase detector compares the phase between the original 5 GHz clock and VCDL output clock, and then decides the charge pump to charge or discharge the loop integrator, a capacitor. The VCDL varies the delay between the stages accordingly until the loop feedback lock condition is satisfied.
Digital code tracking becomes very popular because of the evolution toward all digital modem implementation of DSSS systems.
In this paper, accurate nonlinear analysis for the noncoherent second-order digital code tracking loops is investigated over AWGN channels with the presence of Doppler shift. This modeling of channel finds applications in GPS  and other civilian or military satellite-based DSSS systems, where Doppler shift is due to the relative movement between the satellite and the receiver. In the analysis, based on a regenerative Markov chain modeling of the code tracking process, the lock-in range, transient response, MSE, and MTLL are evaluated more accurately than the traditional analysis. Furthermore, in a digital DLL, the adaptation of code tracking can only be done in discrete steps, i.e., quantized adaptation and that will result in significant changes in the loop performance. In this analysis, the effect of quantized adaptation is evaluated as well.
With the evolution and continuing scaling of CMOS technologies, the demand of high speed and high integration density VLSI systems have exponential growth recently. However, the synchronization problem among IC modules is undoubtedly important and becoming one of the bottlenecks for high performance systems.
VI. C ONCLUSION
A wide-range and fast-locking all-digital DLL is presented in this paper. The CCDU enlarges the operating frequency range of the proposed DLL by a factor of without decreasing timing resolution. The two-step SAR controller ensures the DLL to lock the input clock within 32 clock cycles regardless of the input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range and achieves an acceptable jitter performance as compared to a conventional analog DLL . The proposed all-digital DLL is suitable for the advanced deep-submicron technologies. If more advanced technologies were used, the performance of the DLL such as operating frequency range and jitters could be improved with a little design effort. The power consumption and the total die area would be reduced as well.
For the transmission of images over SS-CDMA AWGN channels, a subband coding scheme that divides the image information into a number of independent data streams using an analysis filter bank, each of which is multiplied by its unique signature PN code, enables the transmission of these data streams via multiple parallel virtual channels created by their correspond- ing PN codes. With a sufficiently large number of streams, the total signal is able to fit within the narrow radio channel bandwidth even though the total bandwidth of all the signals may exceed the channel bandwidth. At receiver, each received signal is separately recovered at the decoder by multiplying its PN code and integrating over the code length in order to obtain the desired subband. All the recovered subbands are then reassembled by a synthesis filter bank into a close reproduction to the original image. Additionally, for color subband image transmission, color images are first transferred to luminance (Y) and two chrominance components (I, Q). Each component is then decomposed independently into several subbands for SS-CDMA transmission. Therefore, a number of additional PN codes are required to support the transmission of the chrominance signals over the CDMA channels whereas the luminance signal was treated in the same manner as monochrome pictures. Moreover, SS-CDMA allows more than one image to be transmitted and be accessed simultaneously at the same limited channel bandwidth.
The proposed ADSSCG employs a novel rescheduling division trian- gular modulation (RDTM) to enhance the phase tracking capability and provide wide programmable spreading ratio. The proposed low-power DCO with auto-adjust algorithm saves the power consumption while keeping delay monotonic characteristic. This paper is organized as fol- lows. Section II describes the proposed architecture and spread spec- trum algorithm of ADSSCG. Section III focuses on the low-power DCO design and the auto-adjust algorithm for monotonic delay char- acteristic. In Section IV, the implementation and measurement results of the fabricated ADSSCG chip are presented. Finally, the conclusion is addressed in Section V.
Another major difference between spectrum auctions and traditional auctions is that spectrum auctions are held re- peatedly due to the dramatic changes of spectrum utilization.
Mostly previous studies on this issue neglect the repeatability of spectrum auctions. Clues about others’ private information may be concluded form historical records or previous rounds, so that spiteful secondary users can use such information to cheat or collusion. These malicious manipulations not only abate victims’ enthusiasm for participation in auctions, which reduces the long-term revenue of primary users, but also cause some vindictive actions from secondary users who never have a chance to win .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 4, APRIL 2003 673
ASpread-Spectrum Clock Generator With Triangular Modulation
Hsiang-Hui Chang, Student Member, IEEE, I-Hui Hua, and Shen-Iuan Liu, Member, IEEE
Abstract—In this paper, aspread-spectrum clock generator (SSCG) with triangular modulation is presented. Only a divider and a programmable charge pump are added into a conventional clock generator to accomplish the spread-spectrum function.
Abstract—This brief presents a frequency trackingloop (FTL) to realize a crystalless wireless sensor node (WSN) for wireless body area network (WBAN). By trackinga remote wireless RF reference for system clock calibration, the proposed FTL allows WSNs to tolerate a large-frequency error from on-chip CMOS oscillators. Moreover, to achieve energy-efficient transmissions in crystalless, a sufficiently accurate convergence clock is required to enable burst overmegabits-per-second system throughput with minimized operation duty cycle. For the dedicated purpose, a comparison-based binary-search tracking scheme, which ensures accurate and robust convergence against noisy wireless channel, is further developed to manage the operation of FTL. The in- termediate frequency back-end part of FTL is implemented in 90-nm CMOS process. Measurement results show that the FTL extends an initial tolerance of system clock error to ±3% and achieves a final quartz-crystal comparable ±50-ppm accuracy.
B ANDWIDTH C OMPARISON R ESULTS B ETWEEN PSPN C ODES AND PN C ODES
Fig. 4. Plot of bandwidth versus toggle rate of the spreading codes.
The block of “frequency divider” generates the clock with data rate. PN code generator generates the PN code. Despreader is used for despreading procedure and the decision circuit detects the signal. The transistor netlist of the blocks in Fig. 6 is implemented. The circuit level simulator Hspice simulates the power consumption of the transistor netlist. All the blocks shown in Fig. 6 are included in this power consumption simulation. The circuit schematics described in Fig. 6 could be operated by different spreading codes with different code lengths. That is to say, this is a soft-coded spreadspectrum system. The simulation results of the power consumption are listed in Table IV. From Table IV, we find the percentages of reduction for power consumption range from 8% to 14% with PSPN codes compared to PN codes. The concept of low toggle rate means low-power consumption has been verified by the simulation results.
Channel modeling simulation tools that enable researchers and designers to accurately predict the performance of wire- less systems become increasingly important as personal com- munications and wireless data services evolve. A basic under- standing of the channel is important not only for designing modulation and coding schemes for robust communication over such channel, but also for investigating the channel fad- ing impact on existing networking algorithms, such as rout- ing and power adjustment which critically depend on channel attenuation. At present, most network protocol simulations and even power control algorithms are using the free space (distance) channel propagation model which is basically only function of transmitter-receiver distance. Typically, for the indoor environment, the channel characteristics are much too complex to be modeled by simple distance functions. Yet, a realistic channel model is essential for network protocol eval- uation, especially in the presence of mobility. Therefore, a more realistic channel fading model which accounts for chan- nel quality variations with movement is needed for network protocol simulation.