第四章 晶片量測結果與分析
4.9 量測結果總結
表 4.10 則是將量測結果與表 1.1 近年來在 IEEE 上發表的相關作品做比較。
可以看到本論文在此表中是唯一一篇以Ring-VCO 產生 6GHz 時脈搭配除頻器調 變 方 法 的 設 計 ， 也 是 唯 一 一 篇 有 量 測 結 果(*表示只有模擬結果) 並 且 符 合 SATA-3.0 規格的 SSCG。
表4.10 將量測結果與近年來在 IEEE 上發表的相關作品做比較
Process Modulation type Clock frequency
EMI reductions Jitter:peak-peak PLL / SSCG
Power VDD
[4]
ISSCC2005
0.18um Multiphase 1.5GHz 9.8dB (RBW=100K)
41.008ps 58.311ps
N/A
[5]
ISCAS2005
0.18um Divider 1.5GHz 23.44dB
(RBW=10K)
80ps N/A
55mW 1.8V
[6]
ISSCC2005
0.15um Divider 1.5GHz 20.3dB
(RBW=1K)
CICC2006
90nm Multiphase 3GHz (LC-VCO)
9.78dB (RBW=100K)
21.1ps 23.8ps
44mW 1V
[8]
TCASⅡ2007 0.18um Multiphase 1.5GHz 14.77dB (RBW=100K)
N/A 34.2ps
34.2mW 1.8V
[9]
ASSCC2007 0.13um Divider 1.5GHz
12.6dB (RBW=100K)
N/A N/A
14.4mW 1.2V
[10]
CICC2007 0.13um Divider 1.5GHz
10dB (RBW=100K)
N/A N/A
30mW N/A
[11]
CICC2007 0.18um VCO & Divider 1.5GHz
19.63dB (RBW=10K)
30ps 35ps
27mW N/A
[12]
CICC2008 0.13um Divider 3GHz
14.5dB (RBW=100K)
N/A N/A
14.7mW 1.2V
[13]
CICC2008
0.18um Divider 1.5GHz 14.2dB
(RBW=100K)
27.88ps N/A
40mW 1.8V
*[14]
DDECS2008
0.13um Divider 6GHz
(LC-VCO)
SOC2008
0.18um Divider 6GHz
(LC-VCO)
ESSCIR2008
0.15um Divider 1.5GHz 10dB
(RBW=100K)
N/A N/A
29mW 1.5V
[17]
TEMC2009 0.18um VCO & Divider 1.5GHz
10.14dB (RBW=100K)
30ps 35ps
15.3mW N/A
*[18]
ASICON2009
90nm Multiphase 6GHz (1.2GHz×5)
ESSCIRC2009
0.13um Divider 1.5GHz 10dB
(RBW=100K)
N/A N/A
18mW N/A
[20]
ASPDAC2009
0.15um Divider 1.5GHz 10dB
(RBW=100K)
N/A N/A
29mW 1.5V
[21]
JSSC2009 0.18um Divider 1.5GHz
10.48dB (RBW=100K)
28.4ps N/A
15mW 1.8V
[22]
TCASⅠ2010 0.13um Divider 3GHz
14.5dB (RBW=100K)
N/A N/A
14.7mW 1.2V
This work 2010 0.18um Divider
6GHz (Ring-VCO)
100K/13.55dB 10K/24.30dB
16.256ps 21.541ps
65.658mW
Frequency Process VCO type PLL area Active area Chip area
*[14] 6GHz 0.13um LC N/A N/A 1.5mm×0.9mm
*[15] 6GHz 0.18um LC N/A 0.57mm×0.45mm N/A
*[18] 1.2GHz×5 90nm Multiphase 0.0484mm2 N/A N/A
This work 6GHz 0.18um Ring 0.0375mm2 500um×300um 933um×933um
本論文在 TSMC-0.18um 1P6M CMOS 製程下，設計出一個運用在 SATA-3.0 傳輸介面的展頻時脈產生電路，在所有晶片(13 顆)量測中，每一顆皆能夠符合
SATA-3.0 所訂立的各項規格要求，其晶片面積為 933um×933um，而核心電路面 積為 500um×300um。晶片操作頻率為 6GHz，工作電壓為 1.8V，功率消耗為 65.658mW(不包含輸出 buffer)，EMI reduction 在 RBW=100K 時為 13.55dB，在 RBW=10K 時為 24.30dB。PLL 鎖定在 6GHz 的 peak to peak jitter 為 16.256ps，rms jitter 為 2.152ps，展頻功能啟動時 peak to peak jitter 為 21.541ps，跟 PLL 相比增 加了5.285ps，而在展頻期間任意取 250 個週期的 peak to peak jitter 為 10.106ps，
以上的數字為所有晶片常溫下的量測平均結果。而在晶片溫度上升的測試中，只 需將電壓調整為2.0V，PLL 功能值到 125°C 都能夠正常工作產生 6GHz 時脈。
當然本次設計也有四個待改進的地方，首先是在 4.8 節中討論的，頻譜上有 25MHz harmonic tone，雖然這是選擇除頻器調變架構所帶來的不可避免因素，但 也有部分原因在於設計迴路濾波器頻寬時，因為本論文認為VCO 產生的高頻雜 訊會是比較需要在意的部份，因此選擇調高頻寬來抑制VCO 雜訊，但另一方面 來說就無法讓低頻的輸入雜訊被濾去，所以才會有這麼嚴重的harmonic tone。第 二個要改進的地方是PCB 版在 VCO 差動時脈輸出路徑上並沒有做對稱直線，導 致有一端6GHz 時脈無法量測，故喪失了差動輸出可降低雜訊 6dB 的益處。
第三個地方在於跟雖然量測跟模擬結果相比各項數據差不多，唯獨在 PLL peak to peak jitter 有較大的差異，這是因為實際 phase noise 的結果與模擬有一段 落差所造成的jitter 上升。第四個地方在於雖然 PVT 分析中確實能夠改變電源來 對抗溫度變異，但是只能看到PLL 鎖定，調變電路的部份則是因為電壓的提升，
讓它失去了將除率控制在限定範圍變化的能力而無法驗證SSCG 的展頻功能。
以上這四點雖然都是不完美的地方但畢竟不是 SATA-3.0 定的規格之列，因 此總結來說，本次設計雖有缺陷之處，但確實本論文在 TSMC-0.18um 1P6M CMOS 製程下，設計出一個能夠運用在 SATA-3.0 傳輸介面的展頻時脈產生電路。
第五章
結論
本 論 文 在 TSMC-0.18um 1P6M CMOS 製 程 下 ， 完 成 了 一 個 可 運 用 在 SATA-3.0 介面的展頻時脈產生電路，其中以 Ring-VCO 直接產生 6GHz 時脈取樣 搭配三階的ΔΣ-modulator 展頻調變電路，並且在設計時加入了 PVT 分析。這樣 完成的SSCG 晶片不但量測結果符合了 SATA-3.0 規格，且具有架構簡單容易實 現，全積體化，低面積使用，有效降低電磁干擾以及具備能夠在任意製程下作平 移的能力，對未來完全整合SATA-3.0 介面所需的其它電路，具有非常大的優勢。
同時從大量量測數據中以及溫度上升的實驗中為本論文所設計的晶片留下最完 整的PVT 分析統計資料。
未來的相關設計本論文認為應該放在幾個地方，首先是在迴路頻寬設計上要 針對25MHz 的 harmonic tone 做抑制。再來是提升 Ring-VCO 的 phase noise 表 現，以降低 PLL 的 jitter。接著是在溫度變異時調整電源會令展頻電路無法正常 工作，需要設計好調變電路的偏壓點。而在PCB 版的設計上會改成將三組 VCO 的差動輸出都拉出觀測，好得到差動輸出抑制雜訊的效果。最後的目標會放在繼 續 將 時 脈 資 料 回 復 電 路(Clock and Data Recovery, CDR) 、 資 料 接 受 端 (RX-Receive)、資料傳輸端(TX-Transmit)等完整 SATA 介面所需的其它傳輸電 路，期望最終能夠完整將此傳輸平台實踐出來。
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