During normal circuit operating condition with 1.2-V VDD power supply and grounded VSS, when a 3×VDD (3.3-V) input signal is applied to the I/O pad, the voltage level at the internal ESD bus will be charged up to 3.3V through the diode Dp connected between I/O pad and ESD bus. For the convenience of easily describing the circuit operation of the 3×VDD-tolerant ESD clamp circuit with HSPICE simulations, the ESD bus is treated as an external 3.3V power supply in this section.
The ESD clamp circuit that can be operated under 3.3-V bias with only 1.2-V low-voltage devices is shown in Fig. 4.3. Under normal circuit operating condition, the diode-connected PMOS (Mp1~Mp3) are used as the voltage divider to bias the substrate driver (Mn1, Mp4, and Mp5) of the ESD detection circuit, where a deep N-well is used in Mn1 to avoid the gate-oxide overstress between gate and bulk. The NMOS (Mn2) is used to keep the voltage level of the trigger node at VSS, so the ESD clamp device is guaranteed to be kept off in the normal circuit operating condition. Here, the RC time constant of R1 and Mp7 should be designed around the order of ~1μs to distinguish the normal circuit operating condition from the ESD transition.
Fig. 4.3 Circuit implementation of the 3×VDD-tolerant ESD clamp circuit A realized with 1×VDD devices.
4.3.1 Operation under Normal Circuit Operating Condition
During normal circuit operating condition, the node 1 and node 2 in the ESD detection circuit will be biased at 2.2V and 1.1V, respectively. The node 5 is biased at 1.2V through the 1kΩ resistor of R2 to VDD, so that Mp5 is turned off. There is no trigger current generated from the ESD detection circuit into the ESD clamp device. In addition, the Mn2 in the turned-on state, whose gate is connected to VDD through the resistor of R2, can increase the noise margin of the ESD detection circuit to guarantee the ESD clamp device against false triggering during the normal circuit operating conditions. All devices in the proposed ESD detection circuit with 1.2-V gate oxide can be free from gate-oxide reliability issue under the ESD bus of 3.3V.
In this ESD detection circuit, the drain-to-gate voltage of Mn1 is (3.3V-2.2V), where Mn1 is working at inversion region under the normal circuit operating conditions. But, the induced channel region of Mn1 could be insufficient to shade the strength of the electric field across the gate and bulk if its bulk region is grounded. There is somewhat gate-oxide reliability concern on Mn1 if its bulk is grounded. Therefore, to avoid this possible issue, the bulk of Mn1 is connected to its own source node. To avoid the leakage current path through
the bulk (p-well) of Mn1 to the grounded p-substrate, the bulk (p-well) of Mn1 is isolated by the deep N-well with 3.3-V bias from the common p-substrate, as the diagram shown in Fig.
4.4. Fig. 4.4 also marks with the Spice-simulated voltages at the nodes of the ESD detection circuit during normal circuit operating condition. From these simulated voltages, the voltages between each two adjacent nodes of devices do not exceed their voltage limitation (1.32V for 1.2-V devices). Therefore, the ESD detection circuit is free from the gate-oxide reliability issue.
Fig. 4.4 Cross-sectional view of the NMOS Mn1 and the HSPICE-simulated voltages at the nodes of ESD detection circuit under the normal circuit operating condition.
4.3.2 Operation under ESD Transition
When ESD voltage is applied to the I/O pad with VSS relatively grounded, such ESD transient voltage will be conducted into ESD bus through the Dp diode in forward-biased condition. Therefore, the ESD bus will have a fast rising-up ESD voltage. The capacitor (Mp6) will couple some ESD transient voltage to the node 1 to turn on Mn1 and to pull up the node 3. The RC delay from R1 and Mp7 in the ESD detection circuit will keep the gate of Mp4 (node 4) at a relatively lower voltage level (compared to the node 3) for a long time. The VDD is initially floating with an initial voltage level of 0V during a PS-mode ESD stress at I/O pad. Some ESD transient voltage would be coupled to VDD through the parasitic
capacitance during ESD zapping, but the R2 and the parasitic capacitance at the gates of Mp5 and Mn2 will hold the gate of Mp5 at a low voltage level for a long time to keep Mp5 in on state. Therefore, Mp4 and Mp5, whose initial gate voltages are at low voltage level, can be quickly turned on by ESD energy to generate the substrate-triggered current into the substrate of SCR. Then, the ESD clamp device can be quickly triggered on to discharge ESD current from ESD bus to VSS.
Fig. 4.5 shows the HSPICE-simulated voltages and the substrate-triggered current of the ESD detection circuit under ESD transition. A 0-to-6V ESD-like voltage pulse with a rise time of 10ns is applied to the ESD bus to simulate the ESD transient voltage. The Spice-simulated results show that the gate voltage of Mn1 (node 1) is quickly pulled high through Mp6, whereas the gate voltage of Mp4 (node 4) is kept low due to the RC time delay from R1 and Mp7. Therefore, the ESD clamp device can be triggered on to discharge ESD current from ESD bus to VSS. The substrate driver can provide the substrate-triggered current larger than 35mA within 10ns when the 0-to-6V transient voltage is applied to ESD bus, as shown in Fig. 4.5. By selecting the suitable device dimensions of R1, Mp7, and the substrate driver (Mn1, Mp4, and Mp5), the peak current and the period of the substrate-triggered current can be adjusted to meet different applications or specifications.
Fig. 4.5 HSPICE-simulated voltages on the nodes of ESD detection circuit and the substrate-triggered current through Mp5 under 0-to-6V ESD-like transition on ESD bus.