Implementation of ESD Protection Circuit with LDNMOS

The proposed ESD protection designs with gate-driven ESD detection circuit (gate-biased technique) and substrate-triggered ESD detection circuit are shown in Figs. 5.8(a) and 5.8(b), respectively, which are named as the gate-driven ESD protection circuit and the substrate-triggered ESD protection circuit in this work. The ESD clamp device (MESD) is implemented by LDNMOS with 2 × 2 octagonal cells, as discussed in Section II. In Fig.

5.8(a), the gate-driven ESD detection circuit is composed of a 40-V HV diode (HVDIO), a 7-V zener diode (ZDIO), a 10-kΩ resistor (R), and a 5-V NMOS device (M1). The reverse-biased HV diode and zener diode are connected in series to sustain the high-voltage (40V) applications on the output pad (O/P) during the normal circuit operating condition. The margin of 7V from the total breakdown voltage of the diodes to the operating voltage is used to avoid mis-triggering on the LDNMOS, even if a 10% overshooting voltage happens to the pad. Therefore, the gate-driven ESD protection circuit can be ensured against gate-oxide overstress issue under the normal circuit operating condition. The gate of M1 is connected to the low-voltage power supply (VDDA). The turned-on NMOS (M1) keeps the gate of the LDNMOS at VSS, so the ESD clamp device (MESD) is guaranteed to be kept off during the normal operating condition. When a positive fast-transient ESD voltage is applied to the output pad with VSS grounded and VDDA floating, the HV diode and the zener diode will enter the breakdown mode to conduct some of ESD current across the resistor R to generate bias voltage to the gate of MESD. Therefore, the gate voltage of MESD can be quickly pulled up to turn itself on by the gate-biased technique during ESD stress. After that, the ESD clamp device enters the snapback region to discharge ESD current from the output pad to VSS. The VDDA is initially floating with an initial voltage level of ~0V during ESD stress event, so M1 is kept in off state without influence on the operation of ESD clamp device.

In Fig. 5.8(b), the substrate-triggered ESD protection circuit includes not only the HVDIO, ZDIO, R, and M1 (which are used in gate-driven ESD detection circuit), but also an additional LDNMOS (MN) as driving element and a 5-V NMOS device (M2). The gates of M1 and M2 are connected to VDDA to keep the voltage levels at the gate of MN and the

P+_trig node of the ESD clamp device (MESD) at VSS. During the ESD transient event, the driving element MN is turned on by the gate-biased effect from the diodes in breakdown mode, and then generates some channel current through MN into the P+_trig node of the ESD clamp device (MESD). The substrate-triggered effect can be accomplished to accelerate the turn-on speed of the ESD clamp device.

(a)

(b)

Fig. 5.8. The proposed ESD protection circuits with (a) gate-driven, and (b) substrate-triggered, ESD detection circuits.

5.4 Experimental Results

The proposed ESD protection circuits have been fabricated in a 0.35-μm 5V/40V BCD

process. No any additional mask layer is needed to fabricate the proposed ESD protection circuits. The typical gate-coupled LDNMOS by connecting a resistor from its gate to VSS has been also fabricated in the same wafer for comparison with the proposed gate-driven and substrate-triggered ESD protection circuits. The gate-coupled LDNMOS is drawn by multiple finger structure with each finger width of 75μm, and the total device width is 300μm. On the other hand, the ESD clamp device in the proposed ESD protection circuits are drawn by 2 × 2 octagonal cells with equivalent total device width of 320μm. To investigate the device behavior during ESD stress, the transmission line pulsing (TLP) technique has been widely used to measure the trigger voltage (Vt1) and the secondary breakdown current (It2) of ESD devices. The TLP generator (TLPG) with a pulse width of 100 ns and a rise time of 10 ns is used in this work to find the Vt1 and It2 of the LDNMOS with gate-biased or substrate-triggered technique. The HBM ESD levels and MM ESD levels of the ESD protection circuits are measured by KeyTek ZapMaster and the failure criterion is defined as the I-V characteristic curve shifting over 20% from its original curve after three continuous ESD zaps at every ESD test level.

5.4.1. TLP Characteristics of Stand-Alone LDNMOS with Gate-Biased or Substrate-Triggered Effects

The TLP-measured I-V characteristics of the LDNMOS device drawn by 2 × 2 octagonal cells with equivalent total device width of 320μm under different gate-biased voltages (Vg) are shown in Fig. 5.9. Without any gate-biased voltage, the Vt1 of the LDNMOS device is ~60V. When the gate-biased voltage is increased to 1V, 3V, and 5V, the Vt1 of the LDNMOS device is reduced to around 57V, 50.5V, and 48V, respectively. With the gate-biased voltage of 8V and 10V, the Vt1 of the LDNMOS device can be reduced to ~40V.

The TLP-measured I-V characteristics of the LDNMOS device drawn by 2 × 2 octagonal cells with equivalent total device width of 320μm under different substrate-triggered currents (I_trig) are shown in Fig. 5.10. When the applied substrate-triggered current is higher than 130mA (equivalent to 0.4mA/μm), the parasitic NPN BJT in the LDNMOS device starts to be turned on, and the Vt1 of the LDNMOS device is reduced. When the I_trig is increased to 0.5mA/μm and 0.55mA/μm, the Vt1 can be reduced to 45V and 23V, respectively. When the I_trig is higher than 0.6mA/μm, the LDNMOS can be turned on rapidly to enter the snapback region without the breakdown mechanism, so the Vt1 is observed as ~11V. From the experimental results of the TLP characteristics of the LDNMOS device with gate-biased

voltage and substrate-triggered current, the acceleration to the turn-on speed of LDNMOS device can be achieved by the gate-biased or substrate-triggered techniques.

Fig. 5.9. TLP-measured I–V curves of the LDNMOS device drawn by 2 × 2 octagonal cells with device width of 320μm under different gate-biased voltages (Vg).

Fig. 5.10. TLP-measured I–V curves of the LDNMOS device by with 2 × 2 octagonal cells with device width of 320μm under different substrate-triggered currents (I_trig).

5.4.2. ESD Performance of LDNMOS with Gate-Coupled Design

The TLP-measured I-V characteristics of the gate-coupled LDNMOS with the resistor of 10kΩ and 50kΩ are shown in Fig. 5.11. The trigger voltage of the gate-coupled LDNMOS with device width of 300μm is still ~60V which is the same as the Vt1 of the standalone gate-grounded LDNMOS with the same device width. Moreover, there is no obvious difference between these two conditions with resistors of 10kΩ and 50kΩ, because the parasitic capacitance from gate to drain of the LDNMOS device is too small to couple sufficient transient voltage to the gate for triggering on the LDNMOS device.

Fig. 5.11. The TLP-measured I-V characteristics of the gate-coupled LDNMOS (drawn by multiple-finger structure with width of 300μm) with resistors of 10kΩ and 50kΩ connected from gate to source.

5.4.3. ESD Performance of LDNMOS with Gate-Driven and Substrate-Triggered ESD Detection Circuits

The TLP-measured I-V characteristics of the gate-driven ESD protection circuit and the substrate-triggered ESD protection circuit are shown in Fig. 5.12, where the I-V characteristic of the gate-coupled LDNMOS with resistor of 10kΩ is also plotted into the figure for comparison. As seen in Fig. 11, the LDNMOS starts to be turned on by the gate-driven or

substrate-triggered ESD detection circuit when the applied voltage is higher than 47V. The Vt1 of the LDNMOS with the gate-driven ESD detection circuit and substrate-triggered ESD detection circuit can be reduced to ~55V and ~51V, respectively. From the TLP measured I-V curves, both gate-driven and substrate-triggered ESD detection circuits are effective in triggering on the LDNMOS device, where the substrate-triggered ESD detection circuit gains more benefit to reduce the Vt1. However, it needs an additional device MN as the driving element which will occupy some layout area. The leakage current of the gate-coupled LDNMOS was obviously increased when the TLP current is higher than 2.1A. The failure criterion for the It2 measurement is determined by leakage current increasing 30% compared to that of fresh samples in this work. Therefore, the It2 level of the gate-coupled LDNMOS is determined as 2.1A. However, the It2 of the LDNMOS drawn by 2 × 2 octagonal cells with the gate-driven and substrate-triggered ESD detection circuits can be improved up to 2.6A and 2.7A, respectively.

Fig. 5.12. The TLP-measured I-V characteristics of the LDNMOS with the proposed ESD detection circuits and the gate-coupled LDNMOS.

The HBM and MM ESD levels of the gate-coupled LDNMOS, the gate-driven ESD protection circuit, and the substrate-triggered ESD protection circuit are listed in Table 5.1.

The gate-coupled LDNMOS has ESD levels of 3kV in HBM and 200V in MM ESD tests.

With the gate-driven ESD detection circuit, the HBM and MM ESD levels of LDNMOS can

be improved to 4.4kV and 275V, respectively. With the substrate-triggered ESD protection circuit, the HBM and MM ESD levels of LDNMOS are 4.2kV and 275V, respectively. No obvious difference in ESD robustness of the LDNMOS device with these two ESD detection circuits, because each octagonal cell of the LDNMOS device can be turned on uniformly. If a higher ESD level is desired, the number of the octagonal cells in LDNMOS should be increased to sustain the ESD stress.

Table 5.1

Comparison of ESD Robustness among the Gate-Coupled LDNMOS, Gate-Driven ESD Protection Circuit, and Substrate-Triggered ESD Protection Circuit

5.4.4. Failure Analysis

The experimental results have shown that the trigger voltage of the LDNMOS device can be substantially reduced by the gate-driven and substrate-triggered ESD detection circuits.

Failure analyses carried by SEM images provide the visual evidence to the LDNMOS device drawn in multiple octagonal cells which can be triggered on uniformly by the ESD detection circuit. Fig. 5.13 shows the ESD failure locations on the proposed gate-driven ESD protection circuit after 4.6-kV positive-to-VSS HBM ESD stress. The failure spots were found at the drain contacts in each cell of the LDNMOS device, indicating that the LDNMOS device has been uniformly turned on by the proposed gate-driven ESD detection circuit.