Improvement in circuit performance of operating frequency and density of the CMOS integrated circuits (IC) for aggressive device scaling with gate lengths down into nanoscale regime. Aggressive scaling of CMOS technology has reduced the SiO2 gate dielectric thickness below 3nm. Major causes for concern in further reduction of oxide thickness include increased poly-silicon gate depletion, boron penetration into the channel region, and high direct tunneling gate leakage current which leads to questions regarding dielectric integrity, reliability, and standby power consumption. According to the International Technological Roadmap for Semiconductors (ITRS), gate oxide thicknesses of 1.2–1.5 nm have been required in 2004 for sub-100-nm CMOS. For such an ultrathin gate oxide, direct tunneling current will dominate the gate leakage current and the off-state power dissipation of the transistor [1]-[2]. For the transistors in conventional CMOS process, the dominant leakage mechanism is mainly due to short channel effects owing to drain-induced barrier lowering (DIBL). However, in the ultrathin gate oxide transistors, the gate leakage current could contribute to standby leakage current significantly, which may result in faulty circuit operation since designers may assume that there is no appreciable gate current.
1.1.1 Gate Current in N/P-Type MOSFET Devices
The gate current arises due to the finite probability of an electron directly tunneling through the insulating SiO2 layer. The amount of the gate current is a strong exponential
function of the gate oxide thickness as well as the voltage potential across the gate oxide. A difference in gate oxide thickness of 0.2nm can result in an order of magnitude change in the gate current, making it the most sensitive parameter with respect to any physical dimensions.
Even the gate oxides can be well controlled (within ±4% in general), as compared to other device dimensions (such as effective channel length or width of metal line), this significant sensitivity makes serious variation in the gate current among different dies in the same wafer.
Another key point is that the gate current of a PMOS device is typically one order of magnitude smaller than that of an NMOS device, under the identical gate oxide thickness and voltage potential across the gate oxide[3]-[4]. This is due to the much higher energy required for hole tunneling in SiO2 and the fact that there are very few electrons associated with a PMOS device. However, in alternate dielectric materials the energy required for electron and hole tunneling can be completely different. In the case of nitrided gate oxides, in use today in some processes, the gate current of the PMOS can actually exceed that of the NMOS depending on the nitrogen concentration (higher nitrogen content increases the gate current of the PMOS relative to the NMOS) [5]-[6].
1.1.2 Modeling of Gate Direct Tunneling Current
Direct tunneling of the conduction band electron from inversion or accumulation layers has been extensively studied [7]-[9]. As for p+ polysilicon gate p-MOSFETs, direct tunneling hole was found to dominate the gate current under channel inversion conditions [10]-[11].
The direct tunneling current appearing between the source–drain extension (SDE) and the gate overlap, so-called the edge direct tunneling (EDT), dominates off-state drive current, especially in very short channel devices [12], [13].
Gate direct tunneling current is produced by the quantum-mechanical wave function of a charged carrier through the gate oxide potential barrier into the gate, which depends not only on the device structure but also bias conditions. The various gate tunneling components in a scaled NMOSFET are illustrated in Fig. 1.1. The gate-to-channel current (Igc), the gate-to-bulk current (Igb), and the EDT currents (Igs and Igd) are shown. In long-channel devices, Igs and Igd are less important than Igc because the gate overlap length is small compared to the channel length. In very short channel devices, the portion of the gate overlap compared to the total gate length becomes larger.
Fig. 1.1 Illustration of gate direct tunneling components of a very short-channel NMOSFET. (Igs and Igd are EDT currents)
Fig. 1.2 illustrates the band diagrams and electron tunneling directions along the gate-to-channel and gate-to-SDE directions for a highly doped drain (HDD) NMOSFET. For Vg > 0V, the gate-to-channel tunneling current (Igc) is the dominant current component, since a higher gate oxide voltage (Vox) appears between the gate and the channel, as shown in Fig. 1.2(a). Here, the Vfb of an NMOSFET with an n-type polysilicon gate (i.e., n+ poly/SiO2 /p-substrate) is approximately -1V, while the Vfb along the gate-to-SDE (i.e., n+ poly/SiO2 /n+ SDE) is approximately 0 V. On the contrary, the EDT currents (Igs and Igd) can become dominant for bias conditions of Vfb < Vg < 0V. For the gate-to-SDE case, electrons accumulated in the n+ poly gate tunnel to the SDE region can lead to an appreciable off-state current. Meanwhile, operating in the depletion mode along the n+ poly/SiO2/p-substrate surface, few electrons are present in the channel that can in turn tunnel into the gate, as shown in Fig. 1.2(b). Such gate currents in ultrathin oxide transistors have been modeled in BSIM4 MOSFET model [14].
In BSIM4 model, the oxide voltage Vox is written as
Vox =Voxacc+Voxdepinv, (1.1)
Voxacc =Vfbzb +VFBeff , (1.2)
Voxdepinv =K1ox Φs +Vgsteff, (1.3) where Voxacc and Voxdepinv are the oxide voltages in accumulation and in inversion (depletion), respectively. The components of gate tunneling current include the tunneling current between gate and bulk (Igb), the current between gate and channel (Igc), and the current between gate
and source/drain diffusion regions (Igs and Igd). The gate-to-bulk current is partitioned into two components for the MOSFET in accumulation (Igbacc) and in inversion (Igbinv). Igbacc and Igbinv are given by
[
( ) (1 )]
The current between gate-to-source/drain diffusion regions are given by
⎥⎦⎤
The gate-to-channel current is formulated as
[
( ) (1 )]
With consideration of drain bias effect, Igc has been partitioned into two parts as Igcs and Igcd, which are expressed as
2 4
From equations (1.4)-(1.8), the main parameters of a MOSFET that dominate the gate current include the effective channel width, channel length, and the voltage difference between the gate and the other terminals.
(a) Vg > 0 V
(b) Vfb < Vg < 0 V
Fig. 1.2 Gate bias dependent band diagrams and electron tunneling in the channel (Igc ) and the gate edge (Igs and Igd ). (a) Vg > 0 V (inversion mode). (b) Vfb < Vg < 0 V (depletion mode).