Standby Leakage Current

The measured standby leakage current of the fabricated 2×VDD-tolerant power-rail ESD clamp circuit under different temperatures are shown in Figs. 3.8(a) and 3.8(b), where the width of the SCR device is 45μm. The standby leakage current is measured by increasing the voltage of VDD_H from 0V to 1.8V and VDD from 0V to 1V simultaneously. The standby leakage current of the prior work (shown in Fig. 3.3) is measured under the same bias condition, and the results are also shown in Fig. 3.8. From the measured results, the standby leakage current of the proposed ESD clamp circuit is only 0.15μA under the temperature of 25^oC and 1.71 μA under the temperature of 125^oC. However, the standby leakage current of the ESD detection circuit in the prior work is as high as 1.18μA under the temperature of 25^oC and 12.6 μA under the temperature of 125^oC. With the STNMOS, the standby leakage current of the prior work increases to even 5.59μA under the temperature of 25^oC and 66.6 μA under the temperature of 125^oC. The standby leakage current of both the ESD detection circuit and the ESD clamp device (SCR) in this work are much smaller than that in the prior work. The proposed 2×VDD-tolerant ESD clamp circuit can achieve a low standby leakage current compared with the prior work. With such a low leakage current, the proposed ESD clamp circuit is suitable for portable or low-power applications, especially when chips are powered by small batteries.

(a)

(b)

Fig. 3.8. The standby leakage current of the proposed ESD clamp circuit and the prior work of ESD detection circuit with and without STNMOS in Fig. 2 at (a) 25^oC and (b) 125 ^oC.

3.4.2 Turn-on Verification

The turn-on behavior of SCR device used as ESD clamp device is an important index for ESD protection. To verify the turn-on efficiency of the proposed ESD clamp circuit, a square-type voltage pulse with a rise time of ~10ns and a pulse height of 5V is used to simulate the rising edge of a positive-to-VSS HBM ESD pulse. When the positive voltage pulse is applied to VDD_H of the proposed 2×VDD-tolerant ESD clamp circuit with VSS grounded and VDD floating, the ESD-like voltage pulse will start the ESD detection circuit to trigger on the SCR device, and in turn to provide a low-impedance path from VDD_H to VSS. The voltage waveform on the VDD_H pin clamped by the ESD clamp circuit is shown in Fig. 3.9. The applied 5-V voltage pulse is clamped down quickly to a low voltage level (~2V) by the proposed ESD clamp circuit with a SCR device width of 45μm. The turn-on time is ~15ns, as observed from the maximum voltage peak to the clamped low voltage level in Fig. 3.9. From the measured voltage waveform, the excellent turn-on efficiency of the proposed ESD clamp circuit during the ESD stress event has been successfully verified.

Fig. 3.9. The measured voltage waveforms clamped by the proposed 2×VDD-tolerant ESD clamp circuit by applying a 0-to-5V voltage pulse to VDD_H of the proposed ESD clamp circuit with VSS grounded and VDD floating. (Y axis: 1V/div.; X axis: 20ns/div.)

3.4.3 ESD Robustness

To investigate the turn-on behavior of the ESD clamping device with ESD detection circuit during the ESD stress event, TLP generator with a pulse width of 100ns and a rise time of ~2ns is used to measure the It2 of the proposed 2×VDD-tolerant ESD clamp circuit. The TLP-measured I-V characteristics of the ESD clamp circuit with SCR device of different widths are shown in Fig. 3.10. The ESD clamp circuit with SCR widths of 30μm, 45μm, and 60μm can achieve It2 of 3.15A, 4,71A, and 6.17A, respectively. Without any triggered mechanism, the original trigger voltage of the stand alone SCR device is as high as ~11.5V.

However, with the proposed ESD detection circuit in this work, the trigger voltage of the SCR device is reduced to only around 3 to 4V, depending on the SCR width. Therefore, the low trigger voltage and high It2 value of the 2×VDD-tolerant ESD clamp circuit can ensure the effective ESD protection capability. The It2 level measured by TLP is proportional to the SCR device width, so the turn-on uniformity of the SCR device has been verified. By increasing the SCR device width, the higher It2 level can be achieved. The holding voltage of the 2×VDD-tolerant ESD clamp circuit is around 2V. Such a holding voltage is higher than the voltage level of VDD_H (1.8V) under the normal circuit operating condition. Even if the SCR device is mis-triggered due to any noise disturbance from the environment of applications, it will be automatically turned off after the noise source is removed. Therefore, the new proposed 2×VDD-tolerant power-rail ESD clamp circuit is free from latchup issue in this design with VDD_H of 1.8V. Once a higher holding voltage is needed for save guardband to prevent latchup issue, the stacked diode structure can be added in series with SCR to increase its overall holding voltage.

The TLP-measured I-V curve of the stacked NMOS in the mixed-voltage I/O buffer (fabricated in the same CMOS process) is shown in Fig. 3.11. The trigger voltage of the stacked NMOS in the mixed-voltage I/O buffer is around 6V, which is much higher than the trigger voltage (~4V) of the proposed ESD protection circuit, as shown in Fig. 3.10.

Therefore, the proposed ESD protection circuit can be turned on before the drain junction breakdown of the stacked NMOS in the mixed-voltage I/O buffers.

Fig. 3.10. The TLP-measured I-V characteristics of the proposed power-rail ESD clamp circuit with SCR device of different widths under positive VDD_H-to-VSS ESD stress. The TLP pulse used in this measurement is with pulse width of 100ns and rise time of ~2ns. The inset figure showed the room-in view on the snapback holding point, where the holding voltage is ~2V.

Fig. 3.11. The TLP-measured I-V curve of the stacked NMOS in the mixed-voltage I/O buffer_. The trigger voltage of the stacked NMOS in the mixed-voltage I/O buffer is around 6V.

The HBM ESD levels and MMESD levels of the proposed 2×VDD-tolerant power-rail ESD clamp circuit with SCR of different widths under positive VDD_H-to-VSS ESD stress are listed in Table 3.3. The failure criterion is defined as the I-V characteristic curve shifting over 20% from its original curve after three continuous ESD zaps at every ESD test voltage level. The HBM ESD levels of the ESD clamp circuit with SCR width of 30μm, 45μm, and 60μm are 4.25kV, 6.5kV, and larger than 8kV, respectively. Besides, the MM ESD levels of the ESD clamp circuit with SCR width of 30μm, 45μm, and 60μm are 225V, 350V, and 450V, respectively, in a 65-nm CMOS process. The corresponding It2 measured by TLP is also listed in Table 3.3.

Table 3.3

ESD Robustness of the Proposed Power-Rail ESD Clamp Circuit with SCR Device of Different Widths