In this chapter, two new ESD protection design by using only 1×VDD low-voltage devices for mixed-voltage I/O buffer with 3×VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device.
These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 130nm 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers [80]-[82].
4.1 Background
The mixed-voltage I/O design with NMOS blocking technique is applied for receiving 3×VDD, 4×VDD, and even 5×VDD input signals without the gate-oxide reliability issue. The mixed-voltage I/O buffer to receive 3×VDD input signals by using only 1×VDD low-voltage devices without suffering gate-oxide reliability issue has been proposed [83]. Nevertheless, the ESD protection design for such a 3×VDD-tolerant mixed-voltage I/O buffer was not considered. To achieve a good whole-chip ESD protection scheme for the 3×VDD-tolerant mixed-voltage I/O interface, it is required to design the low leakage power-rail ESD clamp circuit with only low-voltage devices that can sustain the high power-supply voltage (3×VDD) without suffering gate-oxide reliability. Recently, the ESD protection scheme for the 3.3-V mixed-voltage I/O buffers with 1-V/2.5-V dual gate low-voltage devices has been successfully verified in 0.13μm CMOS process [84]. However, this prior design still needs extra mask-set to implement the thick gate-oxide devices (2.5V devices). Therefore, how to design an effective ESD protection circuit with only low-voltage devices without suffering gate-oxide reliability for mixed-voltage I/O buffer with 3×VDD input tolerance is a significant challenge.
4.2 ESD Protection Scheme for 3×VDD-Tolerant Mixed-Voltage I/O Buffer
To improve ESD robustness of the mixed-voltage I/O interfaces, an ESD protection concept by using the on-chip ESD bus had been reported. However, in this prior art, the gate-oxide reliability was not considered in its circuit implementation. With consideration on the gate-oxide reliability, the new ESD protection scheme for mixed-voltage I/O buffer with 3×VDD input tolerance is shown in Fig. 4.1. The circuit design for 3×VDD-tolerant I/O buffer realized with only 1×VDD devices has been reported in [83]. In the 3×VDD I/O buffer, the dynamic gate-bias circuit controls the gate voltages of the stacked NMOS as shown in Fig.
4.1. When the I/O buffer receives a logic high (3×VDD), the gate voltages of the stacked NMOS are biased at VDD and 2×VDD from left to right, respectively. When operating at other receiving or transmitting modes, the stacked NMOS can also be well biased by the dynamic gate-bias circuit. Therefore, the 3×VDD I/O buffer can tolerate 3×VDD input signals without gate-oxide reliability issue. The detailed circuit implantation to realize such dynamic gate-bias circuit, which can trace the voltage level at the I/O pad, can be found in [83].
Fig. 4.1 The proposed ESD protection scheme for mixed-voltage I/O buffer with 3×VDD input tolerance realized with only 1×VDD devices.
To receive the input signals with 3.3-V voltage level, the traditional ESD protection with direct diode connection from I/O pad to VDD of 1.2V is forbidden. Therefore, the ESD protection circuit is realized with diodes Dp, Dn, D1, ESD bus, ESD detection circuit, ESD clamp device, and the power-rail ESD clamp circuit between VDD and VSS, as shown in Fig.
4.1.
Under positive-to-VSS (PS-mode) ESD stress on I/O pad, the ESD current can be discharged through the diode Dp to the ESD bus and then through the ESD clamp device (SCR) to the grounded VSS, instead of through stacked NMOS in the I/O buffer to ground.
Under positive-to-VDD (PD-mode) ESD stress on I/O pad, the ESD current can be discharged through Dp, ESD bus, and the ESD clamp device to VSS power line, and then through the power-rail ESD clamp circuit between VDD and VSS to the grounded VDD.
Under negative-to-VSS (NS-mode) ESD stress on I/O pad, the negative ESD current can be discharged through the diode Dn in forward-biased condition to the grounded VSS. Under negative-to-VDD (ND-mode) ESD stress on I/O pad, the negative ESD current can be discharged through Dn to the floating VSS power line, and then through the power-rail ESD clamp circuit between VDD and VSS to the grounded VDD. The four modes of ESD stresses on the mixed-voltage I/O pad to VDD or VSS have the corresponding well-designed ESD discharging paths in the proposed ESD protection scheme.
When an ESD stress is applied to the I/O pad, the transient voltage-limiting criteria of the 3×VDD tolerant I/O buffer can be expressed as
NMOS where Vmax is the maximum transient voltage that the 3×VDD I/O buffer can sustain, IESD is the ESD current, and the VBD_NMOS is the transient breakdown voltage of the stacked NMOS between the RESD and VSS in Fig. 4.1. Under the ESD stress event, all nodes in the 3×VDD I/O buffer are floating initially. The transient breakdown voltage VBD_NMOS is given by the drain breakdown voltage of the stacked NMOS in the 3×VDD I/O buffer. In order to prevent the ESD current from injecting into the 3×VDD I/O buffer, the trigger voltage and the clamp voltage of the 3×VDD-tolerant ESD clamp circuit should be less than Vmax. The clamp voltage of the 3×VDD-tolerant ESD clamp circuit can be expressed as
on 3×VDD-tolerant ESD clamp circuit, and Ron is the equivalent turn-on resistance of the diode Dp, parasitic routing resistance, and the 3×VDD-tolerant ESD clamp circuit. Therefore, RESD
should be designed to be slightly greater than some critical value to make sure that Vclamp is
In this work, VBD_NMOS of ~7.5V is measured from the breakdown voltage of the stacked NMOS. For a VD of 0.7V, Vhold of 3.3V, and Ron of 3 ohm, the resistance RESD should be greater than 0.4 ohm and 1.7 ohm for 2kV (IESD of 1.33A) and 4kV (IESD of 2.66A) HBM ESD levels, respectively. Under these criteria, the ESD current is discharged through the proposed ESD protection circuit rather than the 3×VDD I/O buffer under ESD stress, so that the stacked NMOS in the 3×VDD I/O buffer can be safely protected by the proposed ESD protection scheme in Fig. 4.1.
The power-rail ESD clamp circuit between VDD and VSS can be realized by the traditional RC-based ESD detection circuit. To solve the latch-up issue, several diodes are added in series with SCR as the ESD clamp device to increase its overall holding voltage for such (3.3-V) mixed-voltage I/O buffer. Because these two ESD protection design were implemented in two different foundries, the electrical characteristic of SCR devices used as ESD clamp device were quite different. The holding voltage of SCR device is dominated by the doping profiles correlated with the process of each foundry, and therefore the numbers of diodes added in series with SCR for two ESD clamp circuit are different to avoid the latch-up issue. In this work, three (two) diodes are added with SCR in series to increase its overall holding voltage to approximately 4V for such 3.3-V tolerant ESD clamp circuit A (B). The holding voltage a little higher than 3.3V is used to overcome overshooting supply voltage.
The device structure of the ESD clamp device used in these work is shown in Fig. 4.2. The purpose of the additional N-well region under the N+ diffusion at the cathode of the SCR device with the substrate-triggered technique is to further enhance the turn-on speed of the SCR device for better turn-on efficiency, because that can increase the equivalent substrate resistance (Rsub) in this device structure.
To avoid the ESD damage on I/O buffer before ESD clamp device is turned on, the substrate-triggered technique is used to quickly trigger on the ESD clamp device. Because ESD bus line will be biased at 3.3V through the diode Dp when 3.3-V input signals reach to the I/O pad, the ESD detection circuit connected between ESD bus and VSS must sustain the high-voltage (3.3V) stress during normal circuit operating condition. Some ESD detection circuits proposed to increase the turn-on speed of SCR device will suffer gate-oxide
reliability issue under 3.3-V bias with only 1.2-V low-voltage devices. Therefore, how to design a turn-on-efficient ESD detection circuit with only 1.2-V devices to sustain 3.3-V bias becomes a quite significant challenge to this 1.2/3.3-V mixed-voltage I/O buffer.
Fig. 4.2 Device structure of the ESD clamp device composed of substrate- triggered SCR device with diodes in series.