Issue of Mixed-Voltage I/O Interface

With the scaled-down device dimension in advanced CMOS technology, the power supply voltage is also scaled down to reduce the power consumption and to meet the gate-oxide reliability. Therefore, chip design quickly migrates to the lower voltage level with the advancement of the nanoscale CMOS technology. However, some peripheral components or other ICs in a microelectronic system are still operated at the higher voltage levels. In other words, an electronic system could have chips operated at different voltage levels. From the perspective of circuit design for whole system integration, the I/O buffers may drive or receive high-voltage signals to communicate with other ICs. Thus, some circuits must be design in low-voltage process, but still operated in the high-voltage or mixed-voltage (high-voltage and low-voltage) environments. Several problems arise in the I/O interface between these ICs, such as the gate-oxide breakdown [25]-[27] and the undesirable leakage current paths [28]. Fig. 1.6 shows the input and output stage of the traditional CMOS I/O buffer with VDD of 1V and 1-V gate oxide MOSFETs. When an external 1.8-V signal is applied to the I/O pad, the conducted channel of the pull-up PMOS and the parasitic drain-to-well junction diode in the pull-up PMOS will cause the leakage current paths from I/O pad to VDD, as the dashed lines shown in Fig. 1.6. Besides, the 1-V gate oxides of the pull-down NMOS in the output stage and the inverter in the input stage will be over-stressed by the 1.8-V input signal and then suffer the gate-oxide reliability problem.

To solve the gate-oxide reliability issue without using the additional thick gate-oxide process (called dual gate oxide in some CMOS processes), the stacked-NMOS configuration had been widely used in the mixed-voltage I/O buffer to reduce the process complexity and fabrication cost of the chip [29]–[35]. The typical 2×VDD-tolerant mixed-voltage I/O circuit (e.g. 1V/1.8V mixed-voltage I/O interface) is shown in Fig. 1.7. The gate of top NMOS in the stacked-NMOS device is biased at VDD (e.g. 1V in a 1V/1.8V mixed-voltage I/O interface), and the gate of bottom NMOS is biased by the pre-driver circuit. The independent control on the top and bottom gates of stacked-NMOS device allows the devices to meet reliability limitations during normal circuit operation with an input signals with 2×VDD voltage level (e.g. 1.8V in a 1V/1.8V mixed-voltage I/O interface). The gate tracking circuits and the N-well self-biased circuits are designed to ensure that the pull-up PMOS, between the I/O pad and the VDD power line, does not conduct current when the 1.8-V input signals enter the I/O pad. In such mixed-voltage I/O circuits, the on-chip ESD protection circuits will meet more design constraints and difficulty.

VGp

(VDD)

I/O Pad 0V

2 VDD (1.8V)

To internal

circuit

VGn

(VSS)

Leakage Current Path

Gate-Oxide Reliability

1V

Fig. 1.6. Typical circuit diagrams for the traditional CMOS I/O buffer. The leakage current and the gate-oxide reliability appear while I/O pad receives 2×VDD input signals.

Fig. 1.7. Typical circuit diagrams for the mixed-voltage I/O circuits with the stacked NMOS and the N-well self-biased PMOS.

The ESD protection design of I/O pad cooperating with power-rail ESD clamp circuit for traditional I/O circuit and 2×VDD-tolerant mixed-voltage I/O circuit are shown in Fig.

1.8(a) and 1.8(b), where a PS-mode ESD pulse is applied to the I/O pad. In the traditional I/O circuit, the PS-mode ESD pulse can be discharged via two effective paths, as shown in Fig.

1.8(a). The one is through the NMOS in the output buffer by snapback breakdown. The other is through the parasitic diode of PMOS from I/O pad to VDD and power-rail ESD clamp circuit to VSS grounded. However, due to the leakage current issue in the mixed-voltage I/O circuits, there is no diode connected from the I/O pad to VDD power line in the mixed-voltage I/O circuits, as shown in Fig. 1.8(b). Without such diode connected from the I/O pad to VDD in the mixed-voltage I/O circuits, the ESD current at I/O pad under PS-mode ESD stress cannot be discharged from the I/O pad to VDD power line, and cannot be discharged through the additional VDD-to-VSS ESD clamp circuit. Therefore, the power-rail ESD clamp circuit did not help to pull up ESD level of the mixed-voltage I/O pad under the PS-mode ESD stress. In this situation, the ESD current at the I/O pad is mainly discharged through the stacked-NMOS by snapback breakdown. Besides, comparing the single NMOS and the stacked-NMOS in the high-current snapback region, the stacked-NMOS will have a higher trigger voltage, a higher snapback holding voltage, slower turn-on speed, and a lower secondary breakdown current. Therefore, such mixed-voltage I/O circuits with stacked-NMOS often have much lower ESD level under the PS-mode ESD stress, as compared to the traditional I/O circuits with a single NMOS [36], [37]. In addition, without the diode connected from the I/O pad to VDD, the mixed-voltage I/O circuit also has a lower ESD level for I/O pad under PD-mode ESD stress. The absence of the diode between I/O pad and VDD power line in the mixed-voltage I/O circuits will seriously degrade ESD performance of the I/O pad under the PS-mode and PD-mode ESD stresses. By using extra process modification such as ESD implantation, the ESD robustness of stacked-NMOS device can be further improved [38], [39], but the process complexity and fabrication cost are increased. In addition, the induced high voltage on the gate of top NMOS transistor under ESD stress will cause high-current crowding effect in the channel region to seriously degrade ESD robustness of stacked-NMOS device in the mixed-voltage I/O circuits [40]. Therefore, effective ESD protection design without increasing process complexity is strongly requested by the mixed-voltage I/O circuits in the scaled-down CMOS processes.

VSS

Fig. 1.8. The ESD current paths of (a) the traditional I/O pad with power-rail ESD clamp circuit, and (b) the mixed-voltage I/O pad with power-rail ESD clamp circuit, under the positive-to-VSS (PS-mode) ESD stress. The ESD current paths are indicated by the dashed lines.