Conclusions and Future Works
6.2 Future Works
In mixed-voltage I/O interfaces, the effective ESD protection circuits with consideration of gate current for nanoscale have been proposed and verified in this dissertation. But, the whole-chip ESD protection design for a real IC product with more complex circuits and power domains should be considered in nanoscale CMOS technology. The cross power domain ESD protection design should be verified with proposed low-leakage ESD protection designs. The design criterion of the power bus, ESD bus, and the device dimension of low-leakage ESD protection designs could be developed for a real IC product. Moreover, in nanoscale CMOS technology, the ESD protection circuits should be designed for CDM ESD event, which will be a serious challenge to protect ultra-thin gate-oxide, especially for the SoC applications with a large chip area. In high-voltage BCD technology, the ESD robustness and turn-on speed of the ESD protection design with has been improved and verified in this dissertation. In addition, the holding voltage of the stacked-device structure can be designed higher than the supply voltage to avoid the latchup or latchup-like issues in high-voltage BCD ICs. But the layout area of the stacked-device structure will increase as compared to that of the single device, especially for high ESD robustness requirement. The design of new device with the characteristics of both high holding voltage and efficient turn-on speed from the structure design or process modification will be a useful solution. For example, the SCR device or FOX device with high-holding behavior might be a good approach. By adjusting the well profiles of each junction, a non-snapback ESD device might be achieved. Such ESD topics will be the continual future works for research.
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Vita
姓 名：王暢資 (Chang-Tzu Wang) 性 別：男
出生日期：民國72 年 7 月 23 日 出 生 地：台北市
住 址：台北市內湖區康樂街 72 巷 17 弄 76 號 5 樓
學 歷：國立交通大學電子工程學系畢業 (90 年 9 月 – 94 年 1 月) 國立交通大學電子研究所碩士班 (94 年 2 月 – 95 年 2 月) 國立交通大學電子研究所博士班 (95 年 2 月入學)
論文名稱：積體電路電源線間具低漏電流之靜電放電防護電路設計 Low-Leakage Power-Rail ESD Protection Designs in CMOS Integrated Circuits