Ultra Low-Leakage Power-Rail ESD Clamp Circuit

The proposed ultra-low-leakage power-rail ESD clamp circuit is shown in Fig. 2.5. The p-type substrate-triggered silicon-controlled rectifier (SCR) device is used as the main ESD clamping device [70]-[73]. The SCR device, which is composed of cross-coupled n-p-n and p-n-p BJTs with regenerative feedback loop, with a low holding voltage can sustain a high ESD level within a small silicon area in CMOS process. Moreover, the SCR device without poly gate structure has good immunity against the gate leakage problem. However, there are some disadvantages of using the SCR device as the ESD clamp device, such as the slow turn-on speed and the high triggered voltage. Therefore, the ESD detection circuit is used to improve the turn-on speed of the SCR device with substrate-triggered design. The new ESD detection circuit is designed with consideration of the gate current in this work. Utilizing the gate current to bias the ESD detection circuit and to reduce the voltage difference across the gates of the MOS capacitors, the gate leakage current through the MOS capacitor under the normal circuit operating condition can be further reduced. The total leakage current resulted from the MOS capacitor in the ESD detection circuit can be minimized. Therefore, the leakage currents through the ESD clamping device and the ESD detection circuit can be well controlled and minimized by this new proposed design.

Fig. 2.5. The proposed ultra-low-leakage power-rail ESD clamp circuit with p-type substrate-triggered SCR device as ESD clamp device, where the ESD detection circuit is designed with consideration of gate leakage current.

In the proposed ESD detection circuit, the PMOS Mp1 is used as substrate driver to generate the substrate-triggered current into the trigger node of the SCR device during the ESD stress event, but Mp1 is kept off under the normal circuit operating condition. The NMOS Mn is used to keep the voltage level at the trigger node (node b in Fig. 2.5) at VSS, so the ESD clamping device (SCR) is guaranteed to be turned off during the normal circuit operating condition. The RC time constant from R, Mc1, Mc2, and the parasitic gate capacitance of Mn is designed around the order of ~μs to distinguish ESD stress event from the normal power-on condition. The diode-connected Mp2 and Mp3 are acted as a start-up circuit with initial gate-to-bulk current from VDD into the ESD detection circuit, and in turn to conduct some gate current of Mc1 to bias the nodes c, d, and e. After that, the voltage level at node d will be biased at a voltage level to reduce the voltage difference across the gate of Mc1 and to minimize the gate leakage current through the MOS capacitors.

2.3.1 Design Procedure

The gate voltage of Mn should be designed higher than its threshold voltage under the normal circuit operating condition. Realized in a 65-nm CMOS process with VDD of 1V, the voltage level at node c is chosen as 0.45V to keep Mn in turned-on state but without

generating too much gate leakage current from node c to VSS under the normal circuit operating condition. While designing the dimensions of the devices in the ESD detection circuit, the voltage levels at node a and node b are assumed to be kept at VDD and VSS, respectively, under the normal circuit operating condition. With consideration of the RC time constant, Mc1 and Mc2 are designed with the same device dimension, so that the voltage level at the node d is chosen as 0.7V. The gate current of Mc1 will be slightly larger than that of Mc2, and the different parts of the gate current can be conducted by Mp2. From Kirchhoff’s Current Law, the current equation at the node c, d, and e can be expressed as

3

where IgdMn means the total gate-to-drain current of Mn including Igcd and Igd defined in [14]. The total gate current of Mc1 is equal to the total gate current through the oxide of Mn, which can be derived as

Mn Mn

Mc

Mc Idg Igd Igs

Isg ₁+ ₁= + . (2.4)

The voltage differences between the source and drain (Vds) of both Mc1 and Mn are 0V, so that the gate-to-drain current and the gate-to-source current should be the same. Therefore, equation (2.4) can be simplified to the component of only gate-to-source current for Mc1 and Mn, which can be derived as

Mn

Mc Igs

Isg ₁ = . (2.5)

The total gate-to-source current of Mc1 (IsgMc1) in the equation (2.5) can be solved by the given voltage VsgMc1 of 0.3V with the device parameters provided from foundry, which can be roughly calculated as

)

With consideration of the RC time constant, the W/L of MOS capacitor Mc1 is chosen as 5μm/5μm, and the total gate-to-source current of Mc1 can be determined by equation (2.6).

Therefore, the device dimension of Mn can also be determined by equation (2.5). Likewise, the dimension of each device in the proposed ESD detection circuit can be derived through the equations (2.1)-(2.3). With fine tuning on the voltage level at the nodes c, d, and e to achieve a minimized overall standby leakage current, the final dimension for each device in the proposed ESD detection circuit implemented in a given 65-nm CMOS process is shown in Table 2.3, where the device dimension of Mp1 can be adjusted with different triggering

current capability to turn on the main ESD clamping device (SCR). With a large device dimension of Mp1, the substrate-triggered current generated by Mp1 can be increased to accelerate the turn-on speed of the SCR device during ESD event. The discussion on the design flexibility is described in Section 2.4.

Table 2.3

Dimensions of Devices in the ESD detection Circuit of The Proposed Power-Rail ESD Clamp Circuit

2.3.2 Operation under Normal Circuit Operating Condition

Under the normal power-on condition with VDD of 1V and grounded VSS, the gate voltage of Mp1 is biased at around 1V through the resistor R with a low gate current of MOS capacitor Mc1 in the new proposed ESD detection circuit, so that Mp1 can be kept off and no trigger current is generated from the ESD detection circuit to the SCR device. In addition, node c in Fig. 2.5 is biased at some voltage level (~0.45V) to turn on Mn which in turn keeps the trigger node of SCR grounded. Fig. 2.6 shows the HSPICE-simulated voltage waveforms on the nodes of the proposed ESD detection circuit and the gate current through the MOS capacitor Mc1 under the normal power-on condition with a rise time of 1ms and VDD of 1V (VSS of 0V). The gate current of Mc1 is only around 23nA and the voltage level at node a is almost kept at 1V (overlapped with VDD in Fig. 2.6), so that Mp1 is kept in off state.

Fig. 2.6. HSPICE-simulated voltage on the nodes of the ESD detection circuit and the gate current flow through the MOS capacitor Mc1 in the proposed ultra-low leakage ESD clamp circuit in a 65-nm CMOS process under the normal power-on condition.

2.3.3 Operation under ESD Transient Event

When a positive fast-transient ESD voltage is applied to VDD with VSS grounded, the RC delay in the ESD detection circuit keeps the gate of Mp1 at a relatively low voltage level compared to the fast rising voltage level at VDD. The Mp1 can be quickly turned on by the ESD energy to generate the substrate-triggered current into the trigger node (node b) of the SCR device. Finally, the SCR device can be fully turned on into holding state to discharge ESD current from VDD to VSS. In order to simulate the fast transient voltage of HBM ESD event, a 0-to-5V voltage pulse with a rise time of 10ns is applied to VDD as “ESD-like transient pulse” in HSPICE simulation. Fig. 2.7 shows the simulated voltage and substrate-triggered current of the new proposed ESD detection circuit under the ESD transition, where a 0-to-5V voltage pulse with a rise time of 10ns is applied to VDD to simulate the fast transient voltage of human-body-model (HBM) ESD event. With a limited voltage height of 5V in the voltage pulse, the voltage transition on each node in the ESD detection circuit can be simulated to check the desired circuit function before device breakdown. With the proposed ESD detection circuit, the SCR device should be triggered on before device breakdown.

Fig. 2.7. HSPICE-simulated voltages on the nodes of the ESD detection circuit and the substrate-triggered current which flows into the SCR device under 0-to-5V ESD-like transition on VDD.