The proposed ILFD shown in Fig. 2.5 is designed and fabricated using 0.13μm bulk CMOS technology with a supply voltage of 1V. The size of the Min is only 3.6μm/0.12μm. Based on the proposed design guidelines, Q factor of the passive load should be designed as large as possible. Therefore, any finite resistor in parallel with L degrades the locking range and power consumption. Here, a low-Q ILFD with a resistor around 1kΩ connected in parallel with L to reduce the Q factor is also fabricated on the same chip to observe the relationship between the locking range and the Q factor. The low-Q ILFD circuit schematic is shown in Fig. 2.10 where Rp = 1kΩ.
The chip micrographs of both fabricated ILFDs are shown in Fig. 2.11.
The measurement setups for input power and ILFD measurement are shown in Fig. 2.12(a) and (b) respectively. After the losses from the cable and the buffer have been de-embedded, the measured output amplitudes versus the input frequencies for the various values of IDC are presented in Fig. 2.13(a). The locking range can be determined by the difference between the frequencies at the two ends of each curve in Fig. 2.13(a). Fig. 2.13(b) plots the curves of the locking range and the minimum output amplitude in throughout the locking range, versus IDC. The simulated and calculated curves are also shown for comparison. Possible sources of the error between the calculation and simulation are: 1) distributed effect of the passive load is not considered; 2) the output voltage amplitudes are different at lower and higher locking range due to the distributed effect; and 3) harmonic output components are
neglected. Moreover, the difference between the simulated and measured curves mainly results from the inaccurate RF model card provided by the foundry which is only valid up to 18GHz and for small signal simulation and is not accurate at 70GHz and for large signal simulation.
From the measured curve in Fig. 2.13(b), the locking range can be increased significantly by choosing a suitable value for IDC at the cost of a reduced output voltage amplitude. This result is consistent with those of the analysis. Notably, IDC
should be kept larger than the specific current to maintain a sufficient Gm to compensate for the power loss form the equivalent resistive load per oscillating cycle.
Otherwise, the stable output oscillating signals cannot be maintained. Thus, the locking range declines rapidly as shown in the long-broken-line regions of the measured curves in Fig. 2.13(b). The maximum measured locking range is 13.6%
(66.4-76 GHz) with an IDC of 4.4mA from a 1-V supply. Except at the low IDC, the calculated locking ranges from (10) are consistent with the measurement results.
The measured frequency locking ranges as the supply voltage decreases to 0.8V are plotted in Fig. 2.14. The locking ranges are considerably smaller than those in the 1-V case, because the drop in the supply voltage reduces the overdrive voltage of Min
and also the gq,max. Therefore, the gate voltage of Min should be connected to the maximum available voltage, i.e. usually is VDD, to maximize Vov and the locking range. This result is also consistent with analytic results.
The measured locking ranges versus the output voltage amplitudes of the proposed and low-Q ILFDs are plotted in Fig. 2.15. The value of IDC in each case is marked on the measured curves. For any required output voltage amplitude, reducing the Q factor not only increases the required IDC but also reduces the frequency locking range. The locking range declines because an increase in IDC reduces the overdrive
voltage and thereby gq,max also. The measured input sensitivities of both dividers are plotted in Fig. 2.16. The proposed ILFD also has a greater input sensitivity than the low-Q ILFD.
The measured output phase noise and the phase noise of the input signal from the Agilent mm-wave Source Module E8257DS15 [77] are both plotted in Fig. 2.17(a).
The measured curve is not sensitive to the bias condition. Fig. 2.17(a) reveals that the output phase noise is determined by the input phase noise below the 300-kHz offset frequency. Beyond the 300-kHz offset, the output phase noise is corrupted by a flat noise floor of about -120dBc/Hz. The waveform of this extra noise is flat and shapeless, so its source is not within the closed loop that is shown in Fig. 2.8(b). Since only the single-ended output signal is measured, this noise floor may be from the common-mode noise from the PMOS current source, supply voltage and ground, or the instrument itself. The output phase noise and the phase noise in free-run are both plotted in Fig. 2.17(b). Although the output signal in free-run is noisy, the output phase noise after locking is almost independent of the phase noise in free-run below the 10-MHz offset frequency. Beyond the 10-MHz offset frequency, the phase noise in free-run is also corrupted by a flat noise floor at around -120dBc/Hz. Therefore, the internal noise in the loop in Fig. 2.8(b) form the ILFD is observably suppressed before the 10-MHz offset frequency at the very least.
The performances of the proposed divider and other CMOS frequency dividers at above 40GHz are compared in TABLE I. With a smaller input device and without a varactor, the locking range of the proposed divider can be extended to 13.6% at 70GHz. Moreover, it consumes lower power and has higher frequency capability in comparison with Miller divider [38].