To integrate with a differential VCO

There are 2 general methods to integrate single-ended input ILFD with a differential VCO:

1) If a quadrature output signal is required, two independent ILFDs with single-ended input can be directly integrated with a differential VCO [26]

2) If only a differential output signal is required, a dummy input device can be used to balance the differential VCO to reduce the phase and amplitude error [92].

2.3 PHASE NOISE ANALYSIS

In this section, the noise model in an earlier work [26] is modified and used to analysis the phase noise of a direct ILFD. The block diagram of a direct ILFD is redrawn in Fig. 2.8(a) with the active Gm cell replaced by a negative resistor -Ract. Iin,ω

is now given by a single sinusoidal function:

( )

decomposed to φout and the extra phase γ. Here γ is related to the phase difference between the input and output voltage signal, and so it can be given as a function of φin/2-φout.

Fig. 2.8(b) presents the linear loop for the phase noise analysis, where φn_in and φn_out are the random variables that represent the small phase fluctuations of the input and output voltage signals. Here Z(ωm) represents the small phase response of the equivalent load in Fig. 2.8(a) and is given by

( )

the offset frequency. The values of the partial differentiations in Fig. 2.8(b) can be easily calculated using

where γ’ is the derivative of γ. From (2.13) to (2.15), the transfer function of the input and output phase noise spectral densities, Sφn_in and Sφn_out respectively, is given

For a stable oscillating signal, Ract is equal to R+Rin. Therefore, (2.17) can be rewritten as

The calculation of the transfer function of the free running and output phase noise spectral densities (Sφn_free-run and Sφn_out) is as in an earlier cited work [26]; only the result is shown here:

From (2.16), the input phase noise appears at the output with a 6-dB reduction and low-pass shaping, dominating the output phase noise when the offset frequency is less than ωP. When the offset frequency exceeds ωP, then from (2.19), the output phase noise is dominated by the phase noise of the divider in free-run. This result is similar to that of a conventional ILFD. The simulated curves of Sφn_out/Sφn_in with various ωo, Vov and vin at the central frequency are plotted in Fig. 2.9. From Fig. 2.9, ωP/2π increases with ωo/2π and generally exceeds 1GHz when ωo/2π > 35GHz and Vov > 0V.

Therefore, with respect to noise, this structure is also suitable for MMW operations because as ωo becomes large, its internal noise can be suppressed even at a large offset frequency.

2.4 EXPERIMENTAL RESULTS

The proposed ILFD shown in Fig. 2.5 is designed and fabricated using 0.13μm bulk CMOS technology with a supply voltage of 1V. The size of the Min is only 3.6μm/0.12μm. Based on the proposed design guidelines, Q factor of the passive load should be designed as large as possible. Therefore, any finite resistor in parallel with L degrades the locking range and power consumption. Here, a low-Q ILFD with a resistor around 1kΩ connected in parallel with L to reduce the Q factor is also fabricated on the same chip to observe the relationship between the locking range and the Q factor. The low-Q ILFD circuit schematic is shown in Fig. 2.10 where Rp = 1kΩ.

The chip micrographs of both fabricated ILFDs are shown in Fig. 2.11.

The measurement setups for input power and ILFD measurement are shown in Fig. 2.12(a) and (b) respectively. After the losses from the cable and the buffer have been de-embedded, the measured output amplitudes versus the input frequencies for the various values of IDC are presented in Fig. 2.13(a). The locking range can be determined by the difference between the frequencies at the two ends of each curve in Fig. 2.13(a). Fig. 2.13(b) plots the curves of the locking range and the minimum output amplitude in throughout the locking range, versus IDC. The simulated and calculated curves are also shown for comparison. Possible sources of the error between the calculation and simulation are: 1) distributed effect of the passive load is not considered; 2) the output voltage amplitudes are different at lower and higher locking range due to the distributed effect; and 3) harmonic output components are

neglected. Moreover, the difference between the simulated and measured curves mainly results from the inaccurate RF model card provided by the foundry which is only valid up to 18GHz and for small signal simulation and is not accurate at 70GHz and for large signal simulation.

From the measured curve in Fig. 2.13(b), the locking range can be increased significantly by choosing a suitable value for IDC at the cost of a reduced output voltage amplitude. This result is consistent with those of the analysis. Notably, IDC

should be kept larger than the specific current to maintain a sufficient Gm to compensate for the power loss form the equivalent resistive load per oscillating cycle.

Otherwise, the stable output oscillating signals cannot be maintained. Thus, the locking range declines rapidly as shown in the long-broken-line regions of the measured curves in Fig. 2.13(b). The maximum measured locking range is 13.6%

(66.4-76 GHz) with an IDC of 4.4mA from a 1-V supply. Except at the low IDC, the calculated locking ranges from (10) are consistent with the measurement results.

The measured frequency locking ranges as the supply voltage decreases to 0.8V are plotted in Fig. 2.14. The locking ranges are considerably smaller than those in the 1-V case, because the drop in the supply voltage reduces the overdrive voltage of Min

and also the gq,max. Therefore, the gate voltage of Min should be connected to the maximum available voltage, i.e. usually is VDD, to maximize Vov and the locking range. This result is also consistent with analytic results.

The measured locking ranges versus the output voltage amplitudes of the proposed and low-Q ILFDs are plotted in Fig. 2.15. The value of IDC in each case is marked on the measured curves. For any required output voltage amplitude, reducing the Q factor not only increases the required IDC but also reduces the frequency locking range. The locking range declines because an increase in IDC reduces the overdrive

voltage and thereby gq,max also. The measured input sensitivities of both dividers are plotted in Fig. 2.16. The proposed ILFD also has a greater input sensitivity than the low-Q ILFD.

The measured output phase noise and the phase noise of the input signal from the Agilent mm-wave Source Module E8257DS15 [77] are both plotted in Fig. 2.17(a).

The measured curve is not sensitive to the bias condition. Fig. 2.17(a) reveals that the output phase noise is determined by the input phase noise below the 300-kHz offset frequency. Beyond the 300-kHz offset, the output phase noise is corrupted by a flat noise floor of about -120dBc/Hz. The waveform of this extra noise is flat and shapeless, so its source is not within the closed loop that is shown in Fig. 2.8(b). Since only the single-ended output signal is measured, this noise floor may be from the common-mode noise from the PMOS current source, supply voltage and ground, or the instrument itself. The output phase noise and the phase noise in free-run are both plotted in Fig. 2.17(b). Although the output signal in free-run is noisy, the output phase noise after locking is almost independent of the phase noise in free-run below the 10-MHz offset frequency. Beyond the 10-MHz offset frequency, the phase noise in free-run is also corrupted by a flat noise floor at around -120dBc/Hz. Therefore, the internal noise in the loop in Fig. 2.8(b) form the ILFD is observably suppressed before the 10-MHz offset frequency at the very least.

The performances of the proposed divider and other CMOS frequency dividers at above 40GHz are compared in TABLE I. With a smaller input device and without a varactor, the locking range of the proposed divider can be extended to 13.6% at 70GHz. Moreover, it consumes lower power and has higher frequency capability in comparison with Miller divider [38].

2.5 SUMMARY

In this chapter, an analytical model for a direct ILFD is presented. From the proposed model, important design guidelines have been developed. Based on the design guidelines, a 70-GHz direct ILFD has been designed and fabricated using 0.13μm bulk CMOS technology, where a PMOS current source was used to restrict the output voltage amplitude and to increase the overdrive voltage of the input device to improve the frequency locking range. For a direct ILFD, a higher-Q passive load can release the power required without decreasing the frequency locking range. Even if the input device size is small and the varactor is not used, the frequency locking range is large. Simulation results show that the proposed direct ILFD also can be operated in the case of using 1.2-V supply voltage. Therefore, it can be integrated with other circuit using 1.2-V supply voltage. Moreover, if 90-nm CMOS technology is used in the future, 1V can be chosen as the supply voltage of the proposed circuit structure as in this design. Therefore, the proposed direct ILFD can be integrated with an MMW VCO easily and is a favorable choice for use in a CMOS MMW PLL system.

Table 2.1

Performance Comparison between the Proposed CMOS ILFD and Other CMOS Frequency Dividers

This work [35] [36] [37] [38]

Technology 0.13μm 0.13μm 90nm 0.2μm 0.18μm

Divided number 2 2 4 2 2

Input frequency 70GHz 50GHz 70GHz 55GHz 40GHz

VDD (V) 1 *1.2 1.5 0.5 1 2.5

Locking Range (%) 13.57 *20.6 0.16 12.4 5.89 5.8 With/without

varactors Without Without With Without Without Power consumption

(mW) 4.4 *5.3 3 2.75 10.1 16.8

Size of the input device

3.6μm/

0.12μm

6μm/

0.12μm N.A. N.A. N.A.

*Simulation data

Fig. 2.1 A general block diagram of a differential direct ILFD.

(a)

(b)

Fig. 2.2 Two waveforms of Vin, Vout±, and Iin as φ is equal to (a) π/2. (b) π/4.

(a)

(b)

(c)

Fig. 2.3 The simulated waveforms of Vin, Vout±, Iin, Iicos(ωt+φ), Iqsin(ωt+φ) and the equivalent model as (a) 2ω=2ωo. (b) 2ω>2ωo. (c) 2ω<2ωo.

(a)

(b)

(c)

(d)

Fig. 2.4 The contour maps of gq,max as (a) vin=0.6V. (b) vin=0.5V. (c) vin=0.4V. (d) vin=0.3V.

Fig. 2.5 Circuit structure of the proposed direct ILFD.

Fig. 2.6 The simulated frequency locking ranges and gq,max with different values of the inductor.

64 66 68 70 72 74 76 78 Length of input device= 0.144μm

(a)

Fig. 2.7 The simulated input sensitivity curves (a) in cases of different input device length. (b) in the cases of different VDD.

(a)

(b)

Fig. 2.8 (a) The block diagram of the direct ILFD. (b) the linear loop for the phase noise analysis.

(a)

(b)

(c)

Fig. 2.9 The simulated curves of Sφn_out/Sφn_in with different (a) ωo (b) Vov (c) vin at the central frequency

V

_in

VDD

V

_bias

V

_out+

V

out-I

_in

M1 M2

M

_in

I

_DC

M

R_x

V

_dummy

GSG pad

A buffer for measurement

L/2 L/2

10kΩ

R_p

Fig. 2.10 Circuit structure of the Low-Q ILFD.

Fig. 2.11 The micrographs of ILFDs.

Ext. Mixer Sourece

Module

Signal Generator Spectrum Analyzer

(a)

Sourece Module Signal Generator

DUT

MMW probe

MMW probe Spectrum Analyzer

probe Power Supply

Bias Tee

(b)

Fig. 2.12 (a) The measurement setup for input power measurement. (b) the measurement setup for divider measurement.

(a)

(b)

Fig. 2.13 (a) The measured output amplitude versus input frequency. (b) the measured and calculated/simulated locking range and the minimum output

amplitude versus IDC.

Fig. 2.15 The measured locking ranges versus output voltage amplitudes of both proposed and low-Q ILFDs.

Fig. 2.14 The locking range as the supply voltages are 0.8V and 1V.

Fig. 2.16 The measured input sensitivities of both ILFDs.

(a)

(b)

Fig. 2.17 (a) The measured output phase noise and the phase noise of input signal from Agilent mm-wave Source Module E8257DS15 [77]. (b) The measured output

phase noise and the free-run phase noise.

CHAPTER 3 THIRD-ORDER SUB-HARMONIC MIXER WITH AN ON-CHIP WIDE-TUNING-RANGE VCO

3.1 FREQUENCY TUNING RANGE OF COMVENTIONAL CMOS VCO

In order to analyze the relationship between the frequency tuning range and oscillating frequency, a conventional high-frequency VCO is used, as shown in Fig.

3.1(a), where Mv1 and Mv2 are varactors implemented by accumulation-mode MOS’s (A-MOS’s). The model of the equivalent circuit of the VCO is shown in Fig. 3.1(b), where the broken line in the middle represents either the common mode or ground.

The integrated spiral inductor Lint is modeled with gL, Lind, and Cind. Because the impedance of the varactor Mv1/Mv2 is a function of the tuning voltage Vtune, it is modeled with a capacitive function Cvar(Vtune) and a conductive function gvar(Vtune).

The cross-coupled pair formed by M1 and M2 is modeled with –gccp and Cccp. Cload

represents the load capacitance from the next stage.

From the equivalent model in Fig. 3.1(b), the frequency tuning range α of the VCO can be calculated as

where fmax (fmin) is the maximum (minimum) oscillating frequency of the VCO, Cmin = C +C (VDD)+C +C ≈ C (VDD)+C +C , and ΔC = C (0)–C (VDD).

The startup condition is considered to find the relationship between α and fmin. When Vtune = 0V, gvar(Vtune) is maximum and the oscillation frequency is minimum (fmin). For a large fmin (e.g. 60GHz), gvar(0) is usually much larger than gL. Therefore, the startup condition in the worst case (i.e. at fmin) with a small-signal loop gain of β can be expressed as

( )

(

g g_var 0

)

g_var

( )

g_ccp =β _L+ ≈β . (3.2)

In order to express gccp by process parameters, the small-signal model shown in Fig. 3.2 is applied to M1/M2 in Fig. 3.1(a), where rg is the parasitic gate resistor; Cgs, the parasitic gate-to-source capacitor; Cgd, the parasitic gate-to-drain capacitor; Vgs, the voltage on Cgs; and gm the small-signal transconductance. Considering the gate-to-channel and overlap capacitance, Cgs and Cgd can be written as

respectively, where Cox is the gate-oxide capacitance per unit area; Cov, the overlap capacitance per unit width; and W (L), the MOS width (length). If the quality factor Qg = (2πfrgCgs)^–1looking into the gate terminal at frequency f is much larger than 1, gmrg << 1, and the minimum length Lmin is chosen for M1/M2, from (3.3) and (3.4), gccp

can be calculated as

( )

2πf ²γ₁ g

g_ccp ≈ _m− , (3.5)

where

Moreover, to express gvar(0), the equivalent model of a single-finger A-MOS varactor is shown in Fig. 3.3(a), where Cvar,s is a function of Vtune and Rs,s represents the parasitic resistors of the poly gate and channel. When Vtune = 0, for a frequency f, the equivalent parallel model using impedance transformation is as shown in Fig. 3.3(b), where

with the definition that

)

ΔC in (3.1) can be calculated at fmin from (3.2), (3.5), and (3.9). By replacing the result

where the parameters γ1 and γ2 are independent of frequency. From the above equation, it can be observed that α exhibits a drastic decrease for an increase in the oscillating frequency fmin.

In order to observe the relationship between α and fmin in (3.11), simulations of the circuit shown in Fig. 3.1(a) are performed using 0.13μm CMOS technology. All simulations are performed by assuming Cload = 30fF and the gate voltage of M1/M2 is designed as VDD/2 = 0.6V in order to achieve the maximum tuning range as Vtune

ranges from 0 to VDD = 1.2V. For simplification, the finger sizes of M1/M2 and Mv1/Mv2 are fixed, and their sizes are changed by their finger numbers FM and Fv, respectively. The single-turn spiral inductor shown in Fig. 3.4 is used and all inductor models are obtained by using an EM simulator. For different values of FM, the corresponding inductor radii Rind and Fv are decided by the required fmin and the startup condition in (3.2) with β = 3 [78]. The simulation results of α for different size of M1/M2 and fmin are shown in Fig. 3.5(a). The corresponding values of Rind for all simulations are shown in Fig. 3.5(b). From Fig. 3.5(a), it can be observed that the maximum frequency tuning ranges are 22.9%, 8.47%, and 2.16% when fmin is 20, 40, and 60GHz, respectively. The results agree with (3.11), where a drastic decrease is observed in α for an increase in fmin.

From the above results, it can be seen that a 60-GHz conventional VCO is

difficult to cover the entire unlicensed band from 57 to 64GHz (i.e. 11.57% at 60.5 GHz). Therefore, a 60-GHz third-order sub-harmonic mixer with a 20-GHz VCO is proposed in this chapter for wideband applications.

3.2 OPERATIONAL PRINCIPLE

Consider a common-gate amplifier, as shown in Fig. 3.6. The LO signal VLO(t) at the gate terminal results in a time-varying transconductance Gm(t), which is the dominant contributor to frequency conversion. Fig. 3.7(a) shows the simulation results of the relationship between Gm(t) and VLO(t). Moreover, for a sinusoidal VLO(t),

( )

t V v

(

)

V_LO = _G+ _LOcosω_LO , (3.12)

where VG is the DC gate voltage, and vLO and ωLO are the LO amplitude and radian frequency, respectively, the corresponding Gm(t), as shown in Fig. 3.7(b), can be generally expressed as

( )

t =G +G

(

)

(

)

(

)

G_m _m₀ _m₁cosω_LO _m₂cos 2ω_LO _m₃cos3ω_LO . (3.13)

If an RF signal with an amplitude (radian frequency) of vRF (ωRF) is applied to the source terminal, as shown in Fig. 3.6, the desired IF current IIF for the third-order sub-harmonic mixer can be calculated as

( )

From the above equation, it is apparent that Gm3 should be maximized for higher conversion gain. As shown in Fig. 3.7(a), in an LO period, Mmix operates in three different regions—cut-off, weak-inversion, and strong-inversion. Therefore, it is

difficult to frame a general equation for Gm3 based on the process parameters of Mmix. Hence, in this section, HSPICE simulations are used to observe the relationship between Gm3, Gm0, VG, vLO, and the DC current IDC of Mmix and also to find a proper bias voltage VG.

For a given MOS size, the value of Gm3 is dependent on VG and vLO. Fig. 3.8(a) shows a simulation contour map of Gm3 for various VG and vLO. In the simulation, Mmix

has 15 fingers and the width (length) of each finger is 2.6μm (0.13μm). From Fig.

3.8(a), the maximum value of Gm3 is obtained when VG = 0.45V irrespective of the value of vLO. Therefore, without considering IDC and Gm0, for a given Gm3, VG should be set as 0.45V in order to use the smallest Mmix.

However, if IDC is considered, Gm3/IDC should be used as a criterion to compare the efficiency for different conditions of VG and vLO. The simulation results of Gm3/IDC

are plotted against VG for different vLO, as shown in Fig. 3.8(b). In general, vLO is determined by the VCO for other more important specifications in a receiver, e.g.

phase noise. From Fig. 3.8(b), it can be observed that for all values of vLO, the efficiency can be improved significantly by decreasing VG, which results in a larger Mmix for a given Gm3. However, because the LO frequency is only 1/3 of the RF input frequency, the limitation on the size of Mmix, which loads the integrated VCO, is extended significantly.

When the previous stage of the mixer is an LNA, Gm0 of Mmix also acts as an important parameter. In general, the performance of an LNA degrades with the increase in Gm0. Fig. 3.8(c) shows the simulation contour map of Gm0 for various VG

and vLO. In order to make an unbiased comparison between the different conditions, the simulation contour map of Gm3/Gm0 is shown in Fig. 3.8(d). For a fixed vLO and

required Gm3, lower VG results in lower Gm0 and this results in an improved LNA design.

In summary, for a given Gm3, lower VG provides two advantages—lower power consumption and lower Gm0, with the cost that a larger size of Mmix is required.

3.3 CIRCUIT DESIGN

A 60-GHz single-balanced third-order sub-harmonic active mixer with a 20-GHz integrated VCO is designed and fabricated using 0.13μm CMOS technology. The circuit schematic is shown in Fig. 3.9(a). A conventional VCO structure is used for high-frequency operations. In order to reduce the capacitance at the oscillating nodes to obtain a wider tuning range, an NMOS cross-coupled pair formed by Mccp1 and Mccp2 is used in the VCO. The varactors are implemented using two n-type A-MOS’s (i.e. Mvar1 and Mvar2 in Fig. 3.9(a)). Each A-MOS has 26 fingers and the finger width (length) is 2μm (0.4μm). From the simulation, it is observed that the maximum to minimum capacitance ratio of the varactor is approximately 3.57 with a quality factor of 9.7 at 20GHz. A PMOS current source Mp is used in the VCO to limit the amplitude of the output voltage. Moreover, by using Mp, the DC voltage at the oscillating nodes can be easily designed to 0.6V in order to achieve the maximum tuning range as Vtune ranges from 0 to 1.2V.

The differential LO signals from the VCO are applied to the gate terminals of Mmix1 and Mmix2, which are the core mixing devices and VG is set to 0V for higher efficiency, as mentioned in Section 3.2. The RF signal is applied to the common

source terminal through a transmission line T1, which is used to match the RF port to a 50-Ω system for measurement. Due to the balanced structure of the mixer, the fundamental and odd harmonic components of the LO signal are cancelled at the RF port. Therefore, the power leakage from the LO to the RF port mainly results from the even harmonic components. The transmission lines T2 and T3 are used to filter out the

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