Receiver

is used here for the stability simulation. Fig. 4.17 shows the simulation results of μ.

From 1k to 100 GHz, μ is larger than 1 which necessarily and sufficiently proves that the LNA is unconditional stable within the frequency range.

4.3.3 Receiver

The simulation voltage gains of the receiver within the entire QVCO frequency tuning range when the IF frequency is fixed at 500MHz are drawn in Fig. 4.18.

Considering the unlicensed band of 57 to 64 GHz, the voltage gain varies from 25 to 29.25 dB and the input frequencies for the extreme cases are 57.5 and 61.88 GHz, respectively. The simulation baseband frequency responses with different LO frequencies are shown in Fig. 4.19. In all simulations, when the QVCO frequency is fixed at fLO, the input frequency varies between 3 × fLO + 50 MHz and 3 × fLO + 3 GHz, corresponding to an IF frequency varying between 50 MHz and 3 GHz. Among all cases, the minimum and maximum 3-dB bandwidths are 2.7 and 1.1 GHz and the

corresponding 3 × fLO are 57 and 63.57 GHz, respectively.

The simulation noise figures as 3 × fLO ranges from 57 to 64 GHz are shown in Fig. 4.20, where the noise figure varies from 11.11 to 13.4 dB and fLO for the extreme cases are 20.25 and 19 GHz (i.e. 3 × fLO = 60.75 and 57 GHz), respectively. By the way, the noise figure of the sub-harmonic mixer is around 24dB. It should be noted that different corner cases results in different device unity gain frequencies which vary the receiver performance in the most simulations.

The simulated baseband output power versus RF input power is shown in Fig.

4.21. The input 1-dB compression point is around -28 dBm. A two-tone simulation is used to find the input IIP3 and the results are shown in Fig. 4.22. The input IIP3 is around -18.2 dBm. The transient waveforms of quadrature LO signals and the I/Q baseband output signals are shown in Fig. 4.23 (a) and (b), respectively. The whole receiver consumes 35.6 mW from a 1.2-V supply.

The performances of the proposed and other 3-stage LNAs operated around 60 GHz are compared in Table 4.1. The power consumption of the proposed LNA is smallest among them because the LNA can directly connect to the mixers which can be seen as capacitive load instead of resistive load. Moreover, the LNA has the widest input matching bandwidth due to the single common-source structure of the first stage.

The performances of the proposed receiver and other CMOS receivers operated around 60 GHz are compared in Table 4.2. Even though the homodyne strategy is adopted, a QVCO can be integrated into the receiver successfully while its frequency tuning range can cover the unlicensed band of 57 to 64 GHz. Due to the simple structure, the power consumption of the proposed receiver is lower than other heterodyne and low-IF receivers, although some of them are implemented using more

advanced technology. The 1-dB compression point of the proposed receiver is lower because a high gain LNA is required to suppress the noise from sub-harmonic mixers and maintain the noise figure. Therefore, the main expense of using sub-harmonic mixers for broadband operation is a stricter trade-off between the noise and linearity.

4.4 SUMMARY

In this chapter, a 60-GHz homodyne receiver is proposed and analyzed. The receiver consists of: 1) an integrated QVCO for qudrature down conversion; 2) an LNA with low noise figure and wide input matching bandwidth; 3) third-order sub-harmonic mixers in I/Q paths; and 4) baseband amplifiers and output buffers in I/Q paths.

The proposed receiver is highly integrated and its operating frequency range is sufficiently to cover the unlicensed band of 57 to 64 GHz. Moreover, the power consumption of the receiver is lower than heterodyne or low-IF receivers because its structure is much simpler. Therefore, the proposed homodyne receiver is a favorable choice for use in future 60-GHz UWB applications.

Table 4.1

Performance Benchmark of 3-stage LNAs

References *This work [61] [63] ***[66]

Technology 0.13μm 0.13μm 0.13μm 90nm

VDD 1.2 1.2 1.5 1.2

Load type Capacitive Resistive Resistive Resistive

Frequency (GHz) 60 50 60 60

Gain (dB) **17.2 18 12 16.3

NF (dB) 5.89 *5.8 8.8 7.8

Matching bandwidth S11<-12dB 57-80GHz

S11<-8dB 49-51GHz

S11<-12dB 51-65GHz

S11<-10dB 60-66GHz Power consumption 7.3mW 17.8mW 36mW 42.84mW

* Simulation data ** Voltage gain *** Differential LNA

Table 4.2

Performance Comparison between the Proposed Receiver and Other Receivers Operated around 60GHz

References *This

work [63] [64] [65] [66]

Technology 0.13μm 0.13μm 90nm 0.13μm 90nm Structure homodyne heterodyne half-IF homodyne homodyne

LO integration with with with without with

Quadrature down conversion

with without with without without

Operating freq.

consumption 35.6mW 64mW 36mW 9mW

(without VCO) **60mW

VDD 1.2V 1.2V 1.2V 1.2V 1.2V

* Simulation data

** Exclusive of the frequency synthesizer for a fair comparison

Sub-harmonicmixerIn-band signal(57~64 GHz)

QVCO(19~21.33 GHz) LNABSF BasebandAmp. Outputbuffer

Antenna andband-selectedfilter I path

Q path Baseband signalprocessor ormeaurement equipments

T h e proposed homodyne receiver

Fig. 4.1 Architecture of the proposed receiver.

M_LNA1 M_LNA2

Fig. 4.2 Proposed LNA circuit schematic.

M_LNA1

Fig. 4.3 LNA using conventional cascode structure as the first stage.

40 50 60 70 80 4

8 12 16 20 24 28

3.3dB

NF

min

(dB )

Frequency (GHz)

NFmin of the LNA in FIg. 4.2 NFmin of the LNA in FIg. 4.3 NFmin of the LNA in FIg. 4.3, replacing M

cc by an ideal current buffer

4.6dB

Fig. 4.4 The simulated NFmin.

40 50 60 70 80 90 -36

-32 -28 -24 -20 -16 -12 -8 -4 0

13GHz

S11 (dB)

Frequency (GHz)

S11 of the LNA in Fig. 4.2 S11 of the LNA in Fig. 4.3 23GHz

Fig. 4.5 The simulated S11.

MMixer1 LMixer VDD

MMixer2,3MMixer4,5Vbias

MMixer6 MMixer7MMixer8 input fromLNA To basebandamplifier

LO inputfrom QVCO RMixerRMixer omixer +omix

er

-Fig. 4.6 Circuit schematic of the proposed third-order sub-harmonic mixer.

V

tune

VDD

V

tune

M

QVCO1,2

M

QVCO3,4

M

QVCO5

M

QVCO6

M

QVCO7

M

QVCO8

M

QVCO9

M

QVCO10

To I mixer To I mixer To Q mixer ToQ mixer

Fig. 4.7 Circuit schematic of the QVCO.

VDD I/Q baseband output

Output buffer Input from

mixer

Baseband Amplifier

Fig. 4.8 Circuit schematic of the baseband amplifier and output buffer.

RF input

Baseband output (Q channel) Baseband output (I channel)

DC pads

LNA

IQ Mixers

QVCO

Baseband amp. and buffer Baseband amp. and buffer

C_LNA3 C_LNA5

Fig. 4.9 Circuit layout of the receiver.

(a)

(b)

L

_LNA2

L

_LNA3

L

_LNA4

L

_LNA5

L

_LNA6

L

_LNA7

L

_Mixer

L

_Mixer

To the inductor of QVCO

To the inductor of QVCO

To the varactors of QVCO QV

C O o u tp u ts to t h e m

ix e rs

Fig. 4.10 Interconnections on the (a) RF (b) LO signal path for EM simulation.

M

_LNA3

or M

_LNA5

VDD

M

_LNA2

or M

_LNA4

L

_pg

negative resistance

Fig. 4.11 Cascode stage of the LNA.

0.0 0.2 0.4 0.6 0.8 1.0 1.2

Fig. 4.12 Simulation frequency tuning ranges and phase noises of the integrated QVCO

(a)

Fig. 4.13 Monte-Carlo simulation results of (a) phase (b) amplitude errors.

40 45 50 55 60 65 70 75 80 -40

-35 -30 -25 -20 -15 -10 -5 0

S1 1 (d B)

Frequency (GHz)

TT

In FF corner In SS corner

Fig. 4.14 Simulation results of S11.

40 45 50 55 60 65 70 75 80 -25

-20 -15 -10 -5 0 5 10 15 20 25

Voltage Gain (dB)

Frequency (GHz)

TT

In FF corner In SS corner

Fig. 4.15 Simulation results of LNA voltage gains.

40 45 50 55 60 65 70 75 80 5.0

7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5

Noise Figure (dB)

Frequency (GHz)

TT

In FF corner In SS corner

Fig. 4.16 Simulation results of LNA noise figures.

0 20 40 60 80 100 1.0

1.5 2.0 2.5 3.0 3.5

Stability Factor

μ

Frequency (GHz)

TT

in FF corner in SS corner

Fig. 4.17 Simulation results of stability factor μ.

56 58 60 62 64 66 68 12

14 16 18 20 22 24 26 28 30 32

Voltage Gain (dB)

Input Frequency (GHz)

TT

In FF corner In SS corner

Fig. 4.18 Simulation results of receiver voltage gains.

100 1000 16

18 20 22 24 26 28 30

Voltage Gain (dB)

Baseband Frequency (MHz)

3f_LO = 57GHz 3f_LO = 58.95GHz 3f_LO = 61.32GHz 3f_LO = 63.57GHz

Fig. 4.19 Simulation baseband frequency responses with different LO frequencies.

55 56 57 58 59 60 61 62 63 64 10

11 12 13 14 15 16 17 18 19 20

Noise Figure (dB)

3f

LO

Frequency (GHz)

TT

In FF corner In SS corner

Fig. 4.20 Simulation receiver noise figures.

-40 -35 -30 -25 -12

-10 -8 -6 -4 -2 0 2 4

Simulated output power Ideal output power

Output Power (dBm)

Input Power (dBm)

P

_1dB

=-28dBm

Fig. 4.21 Simulation input P1dB.

-40 -35 -30 -25 -20 -15 -10 -60

-50 -40 -30 -20 -10 0 10 20

Ideal output power

Output Power (dBm)

Input Power (dBm)

IIP3=-18.2dBm

Simulated output power

Fig. 4.22 Simulation IIP3.

(a)

(b) 0.0

0.2 0.4 0.6 0.8 1.0 1.2

t+0.2ns

Quadrature LO Signals (V)

t Time

-80.0m -60.0m -40.0m -20.0m 0.0 20.0m 40.0m 60.0m 80.0m 100.0m

t+10ns

I/Q Baseband Signals (V)

t Time

Fig. 4.23 Waveforms of (a) LO (b) baseband output signals.

CHAPTER 5

MILLIMETER-WAVE AND RF

VOLTAGE-CONTROLLED OSCILLATORS USING VARIABLE INDUCTORS

5.1 MMW VCO

5.1.1 VARIABLE INDUCTOR

Fig. 5.1(a) illustrates the schematic of the proposed variable inductor (VID), which consists of a transformer T1 and a variable resistor Rv. L1 and L2 represent the self inductance of the primary and secondary coils of T1, respectively. k is the coupling factor of the primary and secondary coils and Cv is the parasitic capacitor at the secondary coil. The VID can be modeled by a variable inductor Leq in parallel with a variable resistor Req as shown in Fig. 5.1(b). Both Leq and Req are functions of Rv and the radian frequency ω. It can be derived that

( ) [ ( ) ] ( )

If the resonant frequency of Cv and L2 is larger than the operating frequency ω, i.e.

ω²CvL2 < 1, Leq is minimum when Rv is equal to 0 (i.e. Leq(0,ω)) and maximum when Rv is infinite (i.e. Leq(∞,ω)). In this saturation, the Leq monotonically increases with the increases in Rv and the inductance tuning ratio α, defined as [Leq(∞,ω)-Leq(0,ω)]/Leq(∞,ω), can be calculated as

The realization of the VID is shown in Fig. 5.2(a). Here Rv is implemented by an NMOS Mv operated in triode region. Thus Rv and Leq are tunable by adjusting Vtune. The second coil is center tapped to ground, so as to diminish DC power dissipation. In the experimental prototype, using 90-nm CMOS technology, a single-turn 1:1 transformer is adopted in the VID. Fig 5.2 (b) shows the detailed layout of the transformer. The inner radius of the primary (secondary) coil is 25 μm (37 μm); the metal width is 9 μm; and the space between the first and second coils is 3 μm. By EM simulation (using Ansoft HFSS), the self-resonant frequency of the transformer is about 194 GHz. The self inductance of the primary (secondary) coil is about 123 pH (175 pH) and the coupling factor is about 0.45. The width of Mv is 25.8 μm with the minimum length and its turn-on resistance is about 40 Ω with the parasitic capacitance of 20 fF.

The simulated Leq around 60 GHz are illustrated in Fig. 5.3. When Vtune changes from -0.3 to 1.2 V, the Leq is tunable from 142 to 103 pH, and the quality factor is changed from 11.35 to 3.6. The frequency response curve of the quality factor has a U shape, which reveals that the VID has a better quality factor in the extreme cases when Mv is nearly fully turned on or off. In either case the magnetic energy dissipated in the passive Req can be minimized.

5.1.2 MULTI-BAND OPERATION

The proposed VID can be modified to achieve multi-band operation. Here Mv in Fig. 5.2(a) is decomposed into several smaller devices Mv1 … Mvn in parallel, as is shown in Fig. 5.4. Each smaller device is separately controlled by voltages Vb1 … Vbn. As the device size of Mv is equal to those of Mv1 … Mvn in total, the parasitic capacitance at node X in Fig. 4 is almost the same as that in Fig. 5.2(a). Thus multi-band operation can be achieved without severely decreasing the oscillating frequency. This is a significant advantage in contrast to conventional capacitor-bank structure, where the parasitic capacitance in general limited the oscillating frequency and tuning range. Moreover, due to the absence of capacitors in the proposed multi-band tuning strategy, the area occupation of the tuning circuit is also much smaller than that of the conventional capacitor bank.

5.1.3 CIRCUIT DESIGN

By using the proposed VID, a 60-GHz multi-band varactorless VCO is designed and fabricated in a 90-nm CMOS technology. The circuit schematic is shown in Fig.

5.5, where the transformer T1 is implemented by the single-turn 1:1 transformer as shown in Fig. 5.2(b). The primary coil is center tapped by metal 8 to VDD as a DC current path while secondary coil is center tapped to ground by metal 9. In this experimental prototype, the variable resistor consists of six binary-weighted NMOSFETs (Mc1-Mc6) controlled by digital codes (Vb1-Vb6) for band switching, and an NMOS Mf controlled by Vfine for fine frequency tuning. It should be noted that more digitally controlled NMOSFETs results in smaller maximum VCO gain. In order to reduce the capacitance at the oscillating nodes, an NMOS cross-coupled pair formed by M and M is used in the VCO. M is an output buffer to drive the 50-Ω

load form the measurement equipment. M4 is a dummy buffer to balance the parasitic capacitance from M3 at the oscillating node.

Incorporating with the VID model shown in Fig. 5.1(b), the equivalent small-signal model of the VCO is shown in Fig. 5.6. Ct in Fig. 5.6 represents the total capacitance at the resonator, including the parasitic capacitances of the cross-coupled pair M1/M2, the output buffer M3/M4, and the parasitic capacitance of the transformer T1. Req is the equivalent resistance looking into the primary coil of the VID as derived in (5.2). The negative resistance provided by the cross-coupled pair M1 and M2 is denoted as –Rneg which is approximately equal to –2/gm, where gm is the small-signal transconductance of M1/M2. Rneg must be smaller than Req to guarantee oscillation start-up. In this design, Rneg is chosen to be smaller than Req/2.5 within the entire frequency range. From Fig. 5.6 and (5.1), the radian oscillating frequency is the solution of ω of the following equation,

( )

However, the boundary of the VCO frequency tuning range can be found easily without solving such complex equation. As mentioned in sub-Section 5.1.1, when the radian resonant frequency of Cv and L2, denoted by ω2, is larger than the radian oscillation frequency (i.e. ω2 > ω), the minimum Leq is Leq(0,ω) which can be written as

( )

0, L1

( )

1 k²

L_eq ω = − , (5.5)

and the maximum Leq is Leq(∞,ω) which can be written as

Using (5.5) and (5.6), the maximum and minimum radian oscillation frequencies, ωmax and ωmin, can be calculated as

respectively. Based on (5.7) and (5.8), the lower bound of the frequency tuning range β of the VCO can be derived as

which is determined by only one parameter, the coupling factor k of the transformer.

Therefore, for a given transformer to implement the VID, the minimum frequency tuning range of the VCO using the VID can be quickly estimated even before the VCO circuit design. In this design, the simulated resonant frequency of Cv and L2 is over 85 GHz which is larger than the target oscillation frequency, i.e. 60 GHz. With the coupling factor around 0.45, the minimum frequency tuning range of the VCO is

about 10.125%. Therefore, such VCO can be integrated in fundamental front-end system for low-noise and high-linearity MMW broadband applications. Moreover, if the VCO is used in a sub-harmonic front-end system for broadband applications, the operating frequency can be boosted higher than using a conventional VCO.

To integrate with other circuit using 1-V supply voltage, a PMOS current source Mp can be used to raise VDD to 1V with the same DC current as shown in Fig. 5.7(a).

Fig. 5.7(b) shows the simulation results in this situation. It can be observed that such current source can be used without degrading the frequency tuning range and the phase noise.

5.2 RF VCO

5.2.1 INVERSION-MODE VARACTOR

Fig. 5.8 shows circuit schematic of the I-MOS varactor using in the RF VCO for frequency tuning. A large poly resistor Rbulk connects the NMOS bulk and ac ground Vbulk. When the terminal DS in Fig. 5.8 is biased at the positive end voltage, the I-MOS is operated in the depletion mode and Fig. 5.9 (a) shows the equivalent model.

The parasitic capacitance Cparasitic is dominated by the gate-to-source and gate-to-drain overlap capacitance; Cox is the gate-oxide capacitance; and Cd is the depletion capacitance. The conductance looking into terminal G in Fig. 5.8, Gdep, can be calculated as

where ω is the radian frequency and Gbulk is the inverse of the resistance of Rbulk. If

Gbulk is much smaller than ω(Cox||Cd) and ωCparasitic within the entire frequency tuning range, Gdep is approximately equal to jωCparasitic and the minimum capacitance Cmin

can be estimated by Cparasitic. However, if the NMOS bulk is connected directly to the ac ground (i.e. case of infinite Gs), Cmin will become Cparasitic+Cox||Cd. Thus, Cmin can be decreased by Cox||Cd by using a large resistance Rbulk in Fig. 5.8. When DS is biased at the negative end, a sheet of electrons accumulates at the surface of the channel and the IMOS is operated in the inversion mode. Fig. 5.9 (b) shows the equivalent model. Rch is the channel resistance, which can be estimated by following equation [86], (overdrive voltage). To simplify, assuming Rbulk goes to infinite, the conductance looking into terminal G, Ginv, in Fig. 5.9(b) is imaginary part of Ginv is approximately equal to ω(Cox+Cparasitic) and the maximum capacitance Cmax can be estimated by Cox+Cparasitic.

Using 0.18-μm CMOS technology, the HSPICE simulated C-V characteristics of an I-MOS varactor are shown in Fig. 5.10. The resistance of Rbulk is 10k in this simulation. The voltage of terminal G in Fig. 5.8 is set to a fixed voltage, 0.8 V, and the voltage of DS is swept from 0 to 0.8 V. The improvement of the C /C ratio

using the modified I-MOS varactor of Fig. 5.8(a) is close to 25%. It should be noted that the center voltage Vc in Fig. 5.10 can be right-shifted by increasing the bulk biased voltage, Vbulk in Fig. 5.8. In the simulation, Vbulk is 0.4V.

5.2.2 MULTI-BAND OPERATION

A large varactor sensitivity kv [87] degrades of phase noise performance. The effect of kv on phase noise can be shown by the following equation [87],

( )

where fo is the oscillating frequency, Q is the quality factor of the LC tank, Δf is the offset frequency from the carrier, F is the noise factor of the gain element, k is Boltzmann’s constant, T is the flicker noise corner frequency, and kCL is a function of C and L in the resonator. If the required tuning range is large, a bandswitching topology is suggested to reduce varactor sensitivity kv [87]. However, Fig. 5.11 shows the C-V characteristics of an A-MOS varactor with the same size and bias condition as the I-MOS varactor simulated in Fig. 5.10.The A-MOS varactor cannot be fully switched when tuned from 0 to 0.8V. Thus, there is no benefit to implement bandswitching topology with A-MOS varactors to reduce kv in the case of a low tuning voltage. On the other hand, from Fig. 5.10, the gradients of the I-MOS C-V curve are relatively small when the voltages at terminal DS is 0 and 0.8V. Therefore, it makes sense using I-MOS as on/off only varactors in a bandswitching topology to reduce kv and improve phase noise performance with low tuning voltages.

5.2.3 CIRCUIT DESIGN

The VCO is designed using 0.18-μm CMOS technology. Fig. 5.12 shows the circuit schematic for the VCO. It is an LC-tank VCO with an NMOS cross-coupled pair to generate the negative resistance for oscillation. The current source Idc draws 1.5mA. The bandswitching I-MOS varactor array consists of one continuous tuning varactor controlled by tuning voltage Vc1 and two on/off only digital switching varactors controlled by Vc2 and Vc3. Gate terminal (G in Fig. 5.8) of each IMOS connects to the oscillation ports and the drain and source terminal (DS in Fig. 5.8) connects to the tuning ports (Vc1 to Vc3 in Fig. 5.12). The equivalent C-V curve of the three varactors on each side is shown in Fig. 5.10.

Fig. 5.13 shows the detail layout and equivalent model of the spiral inductor. The spiral inductor is implanted using the thick top metal and the inner radius is 80 μm. A symmetrical architecture with center tapping is used to save chip area. ADS Momentum is used for EM simulation. The two-turn inductor provides 1.55nH of inductance, and the quality factor is from 9.5 to 11 across the entire tuning range.

5.3 EXPERIMENTAL AND SIMULATION RESULTS

5.3.1 MMW VCO

Fig. 5.14(a) shows the circuit schematic of the fabricated MMW VCO in 90-nm bulk-CMOS technology. The chip micrograph is shown in Fig. 5.14(b). However, all PMOS’s and MIM capacitors are failed in the shuttle. Therefore, the debug pad which connects node Y and VDD is used in the measurement. Moreover, FIB is used to connect the output node to the output GSG pad.

The measurement setup and environment is shown in Fig. 5.15. The core size is

0.28 × 0.36 mm². The chip is measured on-wafer on a high-frequency probe station.

With VDD = 0.7 V, the measured and simulated frequency tuning characteristics are shown in Fig. 5.16. The tuning voltages of Vb1-Vb6 and Vfine are tied together and varied from -0.3 to 1.2 V, and the VCO frequency is changed from 52.2 to 61.32 GHz.

The corresponding tuning percentage is 16.07%. If the tuning voltage range reduces to 0 to 0.7 V, the tuning percentage becomes 13.98%. The difference of the central frequency between measurement and simulation is about 1.14 GHz. After the loss from the output buffer, probes, cables, adapters, and external mixer have been deembedded, the measured single-end oscillating voltage amplitudes are also shown in Fig. 5.16, where the simulation results also are shown for comparison. From the measurement results, the oscillating voltage amplitude varies from -10.55 to -4.55 dBV within the entire frequency tuning range.

The oscillation of the VCO is started as VDD is larger than 0.37 V. The measured

The oscillation of the VCO is started as VDD is larger than 0.37 V. The measured

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