CHAPTER 6 CONCLUSIONS AND FUTURE WORK
6.2 FUTURE WORKS
The proposed analytical model of a direct ILFD is simple and useful in the direct
ILFD design. In the future, the analysis methodology which is to decompose the injection current into in-phase and quadrature terms, can be used to develop a simple analytical model for a conventional ILFD. As in the case of direct ILFD, some design guidelines can be obtained from the model to help designers to optimize the frequency locking range of a conventional ILFD.
A down-conversion third-order sub-harmonic mixer in receiving path for MMW UWB applications is proposed and analyzed. The conversion gain of the mixer is sensitive to the threshold voltage variation. A bias circuit which compensates such variation can be used to bias the mixer for a robust design. Moreover, the on-chip LO signals are usually shared between receiving and transmitting paths in an integrated transceiver. Therefore, if a third-order sub-harmonic mixer is used in the receiving path for down conversion, an up-conversion third-order sub-harmonic mixer is necessary in the transmitting path. Because the design issues of an up-conversion mixer are quite different from a down-conversion mixer, a different design methodology and circuit topology of an up-conversion third-order sub-harmonic mixer should be developed for an MMW UWB integrated transceiver.
In the implementation of the homodyne receiver for MMW UWB applications, current or gain control technique can be incorporated to improve the linearity.
Because the currents of the sub-harmonic mixers are relatively low in the receiver for higher efficiency, the linearity of the receiver is limited by the mixer. However, to handle the large signals, sufficient linearity is necessary. To improve the linearity, the currents or gains of the mixers can be adjusted. One possible gain control technique is to switch the supply voltage of the mixers to ground such that the mixer becomes a passive mixer and the linearity can be improved significantly. Therefore, the receiver
can be operated in high-gain low-linearity mode for a weak input signal, but operated in low-gain high-linearity mode for a strong signal. Such technique can be implemented in the future. Furthermore, the proposed structure is beneficial for integration. Thus, more than a VCO, a frequency synthesizer also can be integrated with the proposed homodyne receiver as shown in Fig. 6.1 in the future.
An MMW VCO using a variable inductor to achieve wide-frequency-tuning range and multi-band operations is proposed. However, the oscillating voltage amplitude of the VCO is not fixed within the frequency tuning range because of the variable quality factor of the variable inductor. Therefore, an amplitude control technique can be incorporated to maintain a fixed oscillating voltage amplitude.
Moreover, the VCO gains are not fixed in all bands. If a constant VCO gain is required, a more complex resistor network or gm-controlled circuit should replace the variable resistor in the variable inductor. Moreover, based on the proposed MMW frequency divider and VCO, which are the main blocks with the highest operating frequency in a PLL system, a frequency synthesizer can be implemented for MMW UWB applications in the future. Such frequency synthesizer can be integrated with a conventional fundamental UWB front-end system as shown in Fig. 6.2 for the applications simultaneously require low noise and high linearity (i.e. sub-harmonic technique is not suitable). The fundamental receiver and the direct ILFD can be implemented using 90-nm CMOS technology to integration with the MMW VCO proposed in Chapter 5. In this situation, 1V can be chosen as the supply voltage of the whole system in Fig. 6.2. However, if the proposed MMW VCO is implemented in 0.13μm to integrate with the sub-harmonic UWB receiver and the direct ILFD proposed in Chapter 4 and Chapter 2 as shown in Fig. 6.3, the operating frequency can be boosted even higher while the operating frequency range still can be kept wide.
In this situation, 1.2V can be chosen as the supply voltage of the whole system in Fig.
6.3. Finally, when 90-nm or more advanced technologies are used in the future, gate leakage current should be modeled and considered in the MMW circuit or system (e.g.
LNA and receiver) design.
VCO
Fig. 6.1 The sub-harmonic receiver with a frequency synthesizer.
VCO with variable inductor
Fig. 6.2 The fundamental receiver and a frequency synthesizer using the proposed direct ILFD in Chapter 2 and MMW VCO in Chapter 5.
VCO with variable inductor
Fig. 6.3 The sub-harmonic receiver and a frequency synthesizer using the proposed direct ILFD in Chapter 2 and MMW VCO in Chapter 5.
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簡 歷
姓名 ：虞繼堯
性別 ：男
出生日期 ：民國 67 年 2 月 19 日 出生地 ：台灣省 台北市
住址 ：新竹縣竹北市勝利六街七號七樓
學歷 ：
國立清華大學電機工程系畢業 (85 年 9 月- 89 年 6 月) 國立清華大學通訊工程所畢業 (89 年 9 月- 91 年 6 月) 國立交通大學電子研究所博士班 (91 年 9 月入學)
經歷 ：
加拿大渥太華卡爾登大學短期研究 (93 年 8 月- 93 年 10 月)
論文名稱 ： 應用於超寬頻通訊系統之互補式金氧半毫米波積體電路 設計與分析
The Design and Analysis of CMOS Millimeter-Wave Integrated Circuits for Ultra-Wideband Communication Systems
著作 ：(見附件)
PUBLICATION LIST
(A)JOURNAL PAPERS
[1] Chung-Yu Wu and Chi-Yao Yu, “Design and analysis of a millimeter-wave direct injection locked frequency divider with large frequency locking range,”
IEEE Trans. Microwave and Theory Techniques, vol. 55, no. 8, pp. 1649-1658, Aug. 2007.
[2] Chi-Yao Yu and Chung-Yu Wu, “A 60-GHz CMOS Third-Order Sub-Harmonic Mixer with an On-Chip Wide-Tuning-Range VCO,” submitted to IEEE
Journal of Solid-State Circuits.
[3] Cheng-Shang Chang, Duan-Shin Lee, and Chi-Yao Yu, “Providing Guarantee Rate Services in the Load Balanced Birkhoff-von Neumann Switches,”
IEEE/ACM Trans. Networking, vol. 14, no. 3, pp. 644–656, Jun. 2006.
(B) CONFERENCE PAPERS
[1] Chung Yu Wu, and Chi-Yao Yu,“A 0.8-V 5.9-GHz Wide-Tuning-Range CMOS
[1] Chung Yu Wu, and Chi-Yao Yu,“A 0.8-V 5.9-GHz Wide-Tuning-Range CMOS