CHAPTER 3 THIRD-ORDER SUB-HARMONIC MIXER
3.4 EXPERIMENTAL RESULTS
The die micrograph of the proposed mixer with an integrated VCO is shown in Fig. 3.10. The chip is measured on-wafer on a high-frequency probe station. The measurement setup and environment are shown in Fig. 3.11. The LO frequency is measured by the LO power leakage at the IF port. The measured and simulation frequency tuning ranges of the integrated VCO are shown in Fig. 3.12. The measured LO frequency range is from 18.18 to 20.78GHz and the corresponding RF frequency range is from 54.54 to 62.34GHz. Using either set of information, it can be determined that the tuning percentage is 13.35%. The simulation phase noise within the tuning range is also shown in Fig. 3.12. The average phase noise at 1-MHz offset is around –100dBc/Hz. The power consumption of the VCO is 6.6mW from a 1.2-V supply.
The measured and simulation conversion gains of the mixer within the tuning range when VG = 0 and the IF frequency is fixed at 100MHz are shown in Fig. 3.13.
The measured results indicate that the average conversion gain is 7.8dB and the gain variation is smaller than 2.2dB within the tuning range. Moreover, the average power consumption of the mixer core (i.e. Mmix1 and Mmix2) is 0.36mW from a 1.2-V supply.
The measured and simulation IF frequency response is shown in Fig. 3.14 for VG = 0 and 0.1V. In both cases, the VCO frequency is fixed at 20GHz, while the RF frequency varies between 60.05 and 61GHz, corresponding to an IF frequency varying between 50MHz and 1GHz. When VG = 0 V, the measured conversion gain is 8.5dB, the 3-dB bandwidth is around 300MHz, and the DC current of the mixer core
is 0.27mA. However, when VG = 0.1V, the measured conversion gain, 3-dB bandwidth, and the DC current become 3.45dB, 500MHz, and 0.72mA, respectively. The changes in the 3-dB bandwidth and conversion gain mainly result from the variant output resistances of the active loads due to different DC currents. It should be noted that if the load resistance of the output buffer increases from 50 Ω to a few kΩ when the mixer is used in practice, the bandwidth of the mixer can be extended because the required output buffer size becomes much smaller. The measured IF power versus RF power when VG = 0 is shown in Fig. 3.15. The input 1-dB compression point is around –10.2dBm.
Fig. 3.16 presents the measured power leakages of the 2LO and LO signals at the RF port. The 2LO and LO leakages in power are less than –35dBm and –42.5dBm, respectively, within the operating frequency range. Fig. 3.17 and Fig. 3.18 are the measured spectrums of IF power, LO-to-IF leakage, and LO/2LO-to-RF leakages. The output SNR for 1Hz is measured using a spectrum analyzer for an input frequency (intermediate frequency) of 60.1GHz (100MHz). The input power level is measured by a power meter. Based on this data, the noise figure is determined to be 27.6dB.
The fundamental conversion gain of the mixer is also measured and the measured results within the tuning range are shown in Fig. 3.19. When the input frequency around 20 GHz, the fundamental gain is 7 dB larger than the third-order gain. This implies that in the fundamental operation, the noise figure of the mixer is also 7-dB better than that in the third-order operation.
Table 3.1 presents a comparison of the performances of the integrated LO generators. As there is no doubler or buffer, the VCO can be directly connected to the proposed mixer and has a relatively larger operating frequency range and lower power
consumption. A comparison of mixer performances is shown in Table 3.2. The proposed active third-order sub-harmonic mixer has a performance comparable to that of the fundamental mixer when used in a homodyne receiver [65]. Additionally, in comparison with other sub-harmonic mixers [43], [53], the proposed mixer provides a much larger conversion gain and better isolation. Moreover, it consumes the least amount of power among all the other active mixers. The main expense of using the sub-harmonic mixer is a higher noise figure. To suppress the noise from the mixer, a high-gain LNA can be used in front of the mixer in a receiver system.
3.5 SUMMARY
In this chapter, a CMOS third-order sub-harmonic active mixer is proposed and analyzed. The required oscillating frequency of the integrated VCO is 3 times less than that required by a conventional fundamental mixer. Therefore, for a 60-GHz system, the problems in the integration of the LO due to the increase in the LO frequency can be significantly reduced. Based on the experimental results, it is apparent that in percentage, the tuning range of the integrated VCO is sufficient to cover the unlicensed band from 57 to 64GHz. In addition, the performance of the proposed mixer is comparable to that of the fundamental mixer. Moreover, due to the balanced structure and proper bias strategy, the mixer also has the advantages of good isolation and low power consumption. Therefore, this mixer has potential to be used in a CMOS 60-GHz receiver for wideband applications.
TABLE 3.1
Performance Comparison between the Integrated LO Generators in this and Other Works
*Simulation data (internal node cannot be measured)
** Only the power consumption of the input and core stage of the stand-alone doubler
TABLE 3.2
Performance Comparison Between the Mixers in this and Other Works
This work [43] [53] [65]
Technology 0.13 μm SiGe 90 nm 0.13 μm
Type Active Active Passive Active
RF frequency (GHz) 60 77 33 60
IF frequency (GHz) 0.1 1 1 0.1
LO harm. no. 3rd 2nd 3rd 1st
Conversion gain (dB) 7.8 -10.3 -14 ***12
P1dB (dBm) –10.2 2.4 **–2.6 N.A.
LO/2LO-to-RF iso.
(dB) *42.5/35 30/25 21.7/29.4 N.A.
Noise figure (dB) 27.6 ***23 N.A. ***18.5 Power consumption 0.36 mW 22 mW 0 ***1.08 mW
*Measured power leakage at RF port in –dBm ** Measured IIP3 – 9.6 dB
*** Simulation data
VDD
Fig. 3.1 (a) Conventional high-speed VCO (b) equivalent model of the VCO.
Fig. 3.2 Small signal model for M1/M2.
Fig. 3.3 (a) Equivalent model of a single-finger varactor and (b) equivalent parallel model when Vtune = 0.
Fig. 3.4 Single-turn spiral inductor.
(a)
Fig. 3.5 Simulation results of: (a) frequency tuning range and (b) Rind.
Fig. 3.6 Common-gate amplifier with time-varying transconductance.
(a)
(a)
(b)
0.0 0.2 0.4 0.6 0.8 1.0
0 5 10 15 20 25
G
m3/I
DC(V
-1)
V
G(V)
v
LO=0.3V
v
LO=0.4V
v
LO=0.5V
v
LO=0.6V
(c)
(d)
Fig. 3.8 Simulation results of (a) Gm3, (b) Gm3/IDC, (c) Gm3, and (d) Gm3/Gm0.
(a)
Fig. 3.9 (a) Circuit schematic and (b) notch filter and its frequency response.
Fig. 3.10 Die micrograph.
Sourece Module Signal Generator
Atteuneator
DUT
MMW probe
RF GSGSG probe Spectrum Analyzer
DC
probe Power Supply
Bias Tee
Bias Tee Terminal
Power Sensor
Power Meter
coupler
Fig. 3.11 Sub-harmonic mixer measurement setup and environment.
Fig. 3.12 Frequency tuning range and phase noise.
Fig. 3.13 Conversion gain within tuning range.
100 1000 -4
-2 0 2 4 6 8 10
VG=0V, measured data VG=0.1V, measured data VG=0V, simulation data VG=0.1V, simulation data
Conversion G a in (dB)
IF frequency (MHz)
Fig. 3.14 Conversion gain versus IF frequency for different VG.
Fig. 3.15 IF power versus RF power.
Fig. 3.16 Power leakages of the 2LO and LO signals at RF port.
Fig. 3.17 Measured spectrum of IF power and LO-to-IF leakage.
IF tone
LO-to-IF leakage
Fig. 3.18 Measured spectrum of LO/2LO-to-IF leakages.
LO-to-RF leakage
2LO-to-RF leakage
0.0 0.2 0.4 0.6 0.8 1.0 1.2 0
2 4 6 8 10 12 14 16 18 20
Third-order gain Fundamental gain
Conversion Gain (dB)
Tuning Voltage of the VCO (V)
Fig. 3.19 Measured fundamental and third-order conversion gain.
CHAPTER 4
MILLIMETER-WAVE UWB HOMODYNE RECEIVER
4.1 STRUCTURE
For future UWB applications in the unlicensed band from 57 to 64 GHz, a homodyne receiver is proposed in this chapter. Fig. 4.1 shows the architecture of the proposed receiver. Through the antenna and the band-selected filter, all in-band signals are fed to the LNA input port. Therefore, within the unlicensed band, the LNA input impedance need match to the output impedance of the previous stage, which usually is 50 Ω. After the LNA, two third-order sub-harmonic mixers proposed in Chapter 3 are used in in-phase (I) and quadrature (Q) paths respectively to directly convert the RF signals to baseband signals. A quadrature VCO (QVCO) is used to generate quadrature local oscillating (LO) signals for frequency conversion. By using the sub-harmonic mixer, the required LO frequency is three times less the input frequency. Thus, corresponding to the unlicensed band from 57 to 64 GHz, the required LO frequency range is from 19 to 21.33 GHz, i.e. 11.55% at 20.165GHz. The baseband amplifier in each path has two stages and is used to enhance the voltage gain and extend the baseband bandwidth of the receiver while driving the output buffer. Finally, unit-gain output buffers are used to drive 50-Ω system for measurement in both paths.
The architecture shown in Fig. 4.1 offers several advantages over other published 60-GHz homodyne and heterodyne counterparts [60]-[69].
1) The system requires a single frequency synthesizer operating around 20GHz which is lowest among all published works, relaxing the requirement of the QVCO and prescaler.
2) Due to lower LO frequency, the frequency tuning range of the integrated LO signal generator can be extended. Therefore, the architecture is suitable for UWB applications.
3) The LO emission produced by the receiver is well out of the band and heavily suppressed by the selectivity of the antenna and LNA.
4) The architecture does not need a RF-to-IF mixer which is required in a heterodyne receiver [60]-[64]. The mixer consumes extra power. Moreover, its inductive load occupies a large area and results in a long routing path from LNA to the mixer whose parasitic effect needs to be predicted accurately.
5) In comparison with low-IF heterodyne receivers [61]-[63], the proposed receiver is immune to the image problem. Any phase-shift circuit in the RF signal path (e.g. poly phase filter) is not required. So, its area can be saved and RF routing path in layout is simplified. Moreover, the LNA performances can be improved because it need not drive a 50-Ω load.
6) The architecture is simple.
Critical design issues of a homodyne receiver are LO leakage, DC offsets, and flicker noise [40]. In a conventional homodyne receiver, the finite reverse isolation allows the LO leakage to couple to the antenna and the radiated LO power can affect nearby receivers. However, in the proposed architecture, the LO signal is well out of
the band so the LO-leakage problem can be significantly reduced.
One conventional method to remove the DC offsets is employing ac coupling [79]-[81], i.e. high-pass filtering. For the signal degradation to be negligible, the corner frequency of the high-pass filter should be less than 0.1% of the symbol rate [79]. For example, in IS-54, a data rate of 48.6 kb/s mandates a corner frequency less than 50 Hz. Such a low value requires a prohibitively large capacitors and resistors.
However, the reasonable symbol rate of 60-GHz UWB applications should be larger than 1 GHz. Therefore, the corner frequency of the high-pass filter becomes around 1 MHz which is large enough to be integrated on-chip. Moreover, because the typical 1/f noise corner frequency of a submicron MOS is in the vicinity of 1 MHz, flicker noise also can be filtered out by the high-pass filter.
From above discussions, the homodyne receiver with sub-harmonic mixer as shown in Fig. 4.1 is suitable to be used in 60-GHz UWB applications.
4.2 CIRCUIT DESIGN
4.2.1 LNA
The proposed LNA circuit schematic is shown in Fig. 4.2. A three-stage LNA is used to provide sufficient gain to suppress the noise from the following circuit blocks.
The second and third stages of the LNA are implemented by conventional cascode structures where LLNA4 and LLNA6 are used to resonate with the parasitic capacitances at sources of MLNA3 and MLNA5 for higher gain and better noise performance. However, design of the first stage of the LNA is most critical because it dominates noise figure and input matching performances of the LNA. As shown in Fig. 4.2, a single
common-source transistor MLNA1 with source degeneration inductor LLNA2 and gate inductor LLNA1 are adopted as the first stage in the proposed LNA instead of the conventional cascade structure as shown in Fig. 4.3. This is because the noise performance of the cascade structure is degraded rapidly when the operating frequency is on the same order of the unit-gain frequency (fT) of the transistor. The degradation of the noise performance mainly results from two reasons. Firstly, the pole at drain of MLNA1 due to the parasitic capacitance Cp is typically on the order of fT
/2 [65]. When the operating frequency is well below fT, Cp can be neglected so most noise current of MCC, in in Fig. 4.3, is trapped in the loop p1 and does not affect the output voltage of this stage (i.e. drain of MCC). However, when the operating frequency is close to fT, a considerable portion of in flows from output node to ground along the path p2 as shown in Fig. 4.3. Thus, it produces noise voltage at output node, thereby degrading the noise performance. Secondly, Cp also lowers the LNA gain because it shunts a considerable portion of the RF signal current to ground. This raises the noise contributed by in and degrades the noise performance further.
Some ADS simulations using 0.13μm CMOS technology are performed to observe the noise performances in both structures. Fig. 4.4 shows the simulated minimum noise figures (NFmin) of the LNAs in Fig. 4.2 and 4.3. In the simulations, all devices in Fig. 4.3 have the same sizes as the counterparts in Fig. 4.2 and the additional NMOS Mcc in Fig. 4.3 has the same size as MLNA1. It can be observed that the NFmin increases 3.3 dB if Mcc is used. To find actual noise contribution from non-ideal effect of Mcc as mentioned before, Mcc in Fig. 4.3 is replaced by a noiseless current buffer with infinite fT in another simulation and the result is also shown in Fig.
4.4. It can be found that Mcc contributes NFmin of 4.6 dB and the NFmin of the proposed LNA in Fig. 4.2 is much closer to this ideal case with increase in NFmin of only 1.3
dB.
Another important design issue of an LNA is the input matching performance.
The Miller capacitor provided by the gate-to-drain parasitic capacitor of MLNA1
decreases after the resonance at drain node of MLNA1. This characteristic significantly extends the input bandwidth to cover the frequency after the resonance. Fig. 4.5 shows simulated S11 of the LNAs in Fig. 4.2 and Fig. 4.3. For a fair comparison, in the simulations, LLNA1 in Fig. 4.2 and Fig. 4.3 both are optimized for the input matching bandwidth, defined as the frequency range when S11 < -12dB, to cover the unlicensed band. From Fig. 4.5, by using the proposed LNA, the input matching bandwidth can be extended from 13 GHz to 23 GHz and the improvement is 76.9%.
In summary, when the operating frequency is on the same order of transistor fT, using a simple common-source structure as the first stage of an LNA has not only better noise performance but also a wider input matching bandwidth than using the conventional cascode structure. Therefore, it is a better choice to be adopted in a receiver for 60-GHz UWB applications.
4.2.2 Sub-Harmonic Mixer
Third-order sub-harmonic mixers are used in the proposed receiver to reduce the required LO frequency (e.g. 20-GHz LO signal for 60-GHz RF signal). Fig. 4.6 shows the circuit schematic of the proposed third-order sub-harmonic mixer. MMixer1 can be seen as a voltage buffer provided a capacitive load to the previous stage, i.e. LNA.
MMixer2 and MMixer3 are the differential common-gate amplifier whose transconductances are modulated by LO signals. As mentioned in Chapter 3, they dominate the frequency conversion. Because a high-gain stage follows the mixer and
provides enough gain, passive resistor are chosen as output load in this situation for wider baseband bandwidth. Moreover, it is very important to reduce LO-to-output leakage to prevent the saturation of the high-gain stage. Therefore, MMixer3 and MMixer4
whose sizes are equal to MMixer2 and MMixer3 are used to improve the LO-to-output isolation even their extra load effect slightly degrades gain and bandwidth. At the output node omixer+ (omixer -), the LO leakage from MMixer2 (MMixer3) can be cancelled by the opposite-phase leakage from MMixer4 (MMixer5). On the other hand, because the previous stage is a 3-stage LNA with good reverse isolation, the matching network reported in Chapter 3 is replaced NMOS current sources, MMixer6 and MMixer7. The current sources fix the output DC voltages which bias the following gain stages in the non-saturation operation region.
As mentioned in Chapter 3, the transconductance Gm(t) of MMixer2 or MMixer3 can be represented as
( )
t =G +G(
t)
+G(
t)
+G(
t)
+"Gm m0 m1cosωLO m2 cos 2ωLO m3cos3ωLO , (4.1)
where ωLO is the radian LO frequency. If the input voltage is vRFcos(ωRFt) where vRF
(ωRF) is the input RF voltage amplitude (radian frequency), the desired differential output mixing term VIF can be calculated as
( )
where gm1 is the small signal transconductance of MMixer1 and Rmixer is the load resistance as shown in Fig. 4.6. From (4.2), the differential conversion gain Amixer of the third-order sub-harmonic mixer can be calculated as
0
which is proportional to Gm3/Gm0. The simulated contour map of Gm3/Gm0 is shown in Fig. 3.8(d) in Chapter 3. In this case, a current source Mmixer6 (Mmixer7) is used to control bias current of MMixer2 and MMixer3 (MMixer4 and MMixer5), which determines the gate-to-source DC voltages of MMixer2 and MMixer3 (MMixer4 and MMixer5). Therefore, as the analysis in Chapter 3, for a given Gm3/Gm0, the bias current should be designed as low as possible until the total size of MMixer2 to MMixer5 reaches the maximum which can be accepted by the previous stage, i.e. the integrated QVCO.
4.2.3 Quadrature VCO
Due to the reduction of the required LO frequency, for a 60-GHz direct-conversion receiver, the conventional QVCO [81] can be integrated in the system easily while covering entire unlicensed band from 57 to 64 GHz (the corresponding LO frequency is from 19 to 21.33 GHz). Fig. 4.7 shows the circuit schematic of the QVCO.
In order to reduce the capacitance at the oscillating nodes to obtain a wider frequency tuning range, NMOS cross-coupled pairs formed by MQVCO1 to MQVCO4 are used in the QVCO. MQVCO5 to MQVCO8 provide coupling between the output ports for quadrature outputs. The varactors are implemented using n-type A-MOS’s. Each A-MOS has 29 fingers and the finger width (length) is 2μm (0.5μm). The simulated maximum to minimum capacitance ratio of the varactor is approximately 3 with a quality factor of 8.49 at 20GHz. MQVCO9 and MQVCO10 are biased in the triode region and the DC voltages at the output nodes are designed as VDD/2 (0.6 V in this case) in order to achieve the maximum tuning range as Vtune ranges from 0 to VDD (1.2 V in this case).
4.2.4 Baseband Amplifier and output buffer
Fig. 4.8 shows the circuit schematic of the baseband amplifier and the output buffer. The baseband amplifier consists of two cascaded differential pairs and is used to enhance the receiver gain and extend the bandwidth while driving the output buffer.
The output buffer provides unit voltage gain when the off-chip 50-Ω loads is connected to its output ports.
4.2.5 Layout consideration
Layout is an important step in designing the receiver when the operating frequency is up to 60 GHz, because a different shape or length of each interconnecting metal line may significantly affect the performances of the receiver. Therefore, all parasitic effects from the interconnections on the MMW signal path are considered in the circuit design by using an EM simulator (Ansoft HFSS). Using 0.13-μm CMOS technology, the circuit layout of the receiver is shown in Fig. 4.9. The interconnections between the LNA and mixers are extracted with the inductors as a 17-ports component for EM simulation as shown in Fig. 4.10 (a). Moreover, the parasitic inductances of the interconnections between QVCO and mixers significantly reduce the down-conversion gain, so the interconnections should be designed as short as possible. In this design, they are extracted as a 12-ports component for EM simulation as shown in Fig. 4.10 (b).
Except the interconnections on the RF and LO paths, the layout of the cascode devices, i.e. MLNA3 and MLNA5 in Fig. 4.2, should be designed carefully as well.
Except the interconnections on the RF and LO paths, the layout of the cascode devices, i.e. MLNA3 and MLNA5 in Fig. 4.2, should be designed carefully as well.